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ARM: dts: artpec6.dtsi updates

PATCH Applied Lars Persson 2 participants 5 messages Aug 23, 2016 – Sep 13, 2016 Device tree bindings

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Lars Persson

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#0 lore raw

cover ARM: dts: artpec6.dtsi updates

This brings the dtsi up to date with with tested and optimized settings from the Axis tree.

Lars Persson (3):
ARM: dts: artpec: use clock binding header
ARM: dts: artpec: use optimized pl310 settings
ARM: dts: artpec: set irq affinity on pmu interrupts

 arch/arm/boot/dts/artpec6.dtsi | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH 1/3 ARM: dts: artpec: use clock binding header

Use defines from the clock binding header as clock indexes.

Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/boot/dts/artpec6.dtsi | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)
arch/arm/boot/dts/artpec6.dtsi +12 -11
index 3fac4c4..db41b52 100644
@@ -41,6 +41,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
 #include "skeleton.dtsi"
 
 / {

@@ -109,14 +110,14 @@
 		compatible = "arm,cortex-a9-global-timer";
 		reg = <0xfaf00200 0x20>;
 		interrupts = <GIC_PPI 11 0xf01>;
-		clocks = <&clkctrl 1>;
+		clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
 	};
 
 	timer at faf00600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0xfaf00600 0x20>;
 		interrupts = <GIC_PPI 13 0xf04>;
-		clocks = <&clkctrl 1>;
+		clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
 		status = "disabled";
 	};
 

@@ -157,7 +158,7 @@
 		ethernet: ethernet at f8010000 {
 			clock-names = "phy_ref_clk", "apb_pclk";
 			clocks = <&eth_phy_ref_clk>,
-				<&clkctrl 4>;
+				<&clkctrl ARTPEC6_CLK_ETH_ACLK>;
 			compatible = "snps,dwc-qos-ethernet-4.10";
 			interrupt-parent = <&intc>;
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

@@ -175,8 +176,8 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0xf8036000 0x1000>;
 			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkctrl 13>,
-				<&clkctrl 12>;
+			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
+				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
 			clock-names = "uart_clk", "apb_pclk";
 			status = "disabled";
 		};

@@ -184,8 +185,8 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0xf8037000 0x1000>;
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkctrl 13>,
-				<&clkctrl 12>;
+			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
+				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
 			clock-names = "uart_clk", "apb_pclk";
 			status = "disabled";
 		};

@@ -193,8 +194,8 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0xf8038000 0x1000>;
 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkctrl 13>,
-				<&clkctrl 12>;
+			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
+				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
 			clock-names = "uart_clk", "apb_pclk";
 			status = "disabled";
 		};

@@ -202,8 +203,8 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0xf8039000 0x1000>;
 			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkctrl 13>,
-				<&clkctrl 12>;
+			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
+				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
 			clock-names = "uart_clk", "apb_pclk";
 			status = "disabled";
 		};
Signature · 1 line
2.1.4
author
#2 lore raw

PATCH 2/3 ARM: dts: artpec: use optimized pl310 settings

In reply to Lars Persson

Use the cache settings that were determined to give best performance on artpec-6 typical workloads.

Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/boot/dts/artpec6.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm/boot/dts/artpec6.dtsi +7 -0
index db41b52..4e40d55 100644
@@ -137,6 +137,13 @@
 		arm,data-latency = <1 1 1>;
 		arm,tag-latency = <1 1 1>;
 		arm,filter-ranges = <0x0 0x80000000>;
+		arm,double-linefill = <1>;
+		arm,double-linefill-incr = <0>;
+		arm,double-linefill-wrap = <0>;
+		prefetch-data = <1>;
+		prefetch-instr = <1>;
+		arm,prefetch-offset = <0>;
+		arm,prefetch-drop = <1>;
 	};
 
 	pmu {
Signature · 1 line
2.1.4
author
#3 lore raw

PATCH 3/3 ARM: dts: artpec: set irq affinity on pmu interrupts

In reply to Lars Persson

The irq affinity is required for pmu interrupts.

Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/boot/dts/artpec6.dtsi | 1 +
 1 file changed, 1 insertion(+)
arch/arm/boot/dts/artpec6.dtsi +1 -0
index 4e40d55..3489019c 100644
@@ -150,6 +150,7 @@
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>;
 		interrupt-parent = <&intc>;
 	};
Signature · 1 line
2.1.4
Applied
#4 lore raw
In reply to Lars Persson
Quoted 12 lines · CEST Lars Persson

This brings the dtsi up to date with with tested and optimized settings from the Axis tree.

Lars Persson (3):
ARM: dts: artpec: use clock binding header
ARM: dts: artpec: use optimized pl310 settings
ARM: dts: artpec: set irq affinity on pmu interrupts

 arch/arm/boot/dts/artpec6.dtsi | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

Applied all three to next/dt, thanks for your patience and sorry for the delay on my side.

Arnd