staging: comedi: Fix checkpatch warning
v3 cover staging: comedi: Fix checkpatch warning
Fix checkpath.pl warning:
line over 80 characters
Block comments use * on subsequent lines
Block comments use a trailing */ on a separate line Statements should start on a tabstop
Comparisons should place the constant on the right side of the test
Changes in V2:
Remove extra space after /*
Align single line comment
Block comments starts with /* followed by comments on the next line
Changes in V3:
Fix trailing space
Fix checkpatch.pl warning for blank line after enum declaration Move macro definition to the top of the file
Align macro definitions
Anson Jacob (8):
staging: comedi: cb_pcidas64.c: Fix checkpatch warning
staging: comedi: cb_pcidas64: Fix commenting style
staging: comedi: jr3_pci.h: Fix checkpatch warning
staging: comedi: ni_atmio.c: Fix checkpatch warning
staging: comedi: s626.h: Fix checkpatch warning
staging: comedi: jr3_pci.c: Fix checkpatch warning
staging: comedi: ni_at_a2150: Fix checkpatch warning
staging: comedi: cb_pcidas64: Fix checkpath warning
drivers/staging/comedi/drivers/cb_pcidas64.c | 573 ++++++++++++++------------- drivers/staging/comedi/drivers/jr3_pci.c | 13 +- drivers/staging/comedi/drivers/jr3_pci.h | 290 ++++++++------ drivers/staging/comedi/drivers/ni_at_a2150.c | 170 ++++---- drivers/staging/comedi/drivers/ni_atmio.c | 11 +- drivers/staging/comedi/drivers/s626.h | 4 +- 6 files changed, 562 insertions(+), 499 deletions(-)
Signature · 1 line
2.7.4
PATCH v3 1/8 staging: comedi: cb_pcidas64.c: Fix checkpatch warning
Fix checkpatch.pl warning:
Block comments use * on subsequent lines Block comments use a trailing */ on a separate line
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/cb_pcidas64.c | 148 ++++++++++++++------------- 1 file changed, 77 insertions(+), 71 deletions(-)
drivers/staging/comedi/drivers/cb_pcidas64.c +77 -71
@@ -1,34 +1,34 @@/* -comedi/drivers/cb_pcidas64.c -This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS -64xx, 60xx, and 4020 cards. - -Author: Frank Mori Hess <[email protected]> -Copyright (C) 2001, 2002 Frank Mori Hess - -Thanks also go to the following people: - -Steve Rosenbluth, for providing the source code for -his pci-das6402 driver, and source code for working QNX pci-6402 -drivers by Greg Laird and Mariusz Bogacz. None of the code was -used directly here, but it was useful as an additional source of -documentation on how to program the boards. - -John Sims, for much testing and feedback on pcidas-4020 support. - -COMEDI - Linux Control and Measurement Device Interface -Copyright (C) 1997-8 David A. Schleef <[email protected]> - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. -*/ +* comedi/drivers/cb_pcidas64.c +* This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS +* 64xx, 60xx, and 4020 cards. +* +* Author: Frank Mori Hess <[email protected]> +* Copyright (C) 2001, 2002 Frank Mori Hess +* +* Thanks also go to the following people: +* +* Steve Rosenbluth, for providing the source code for +* his pci-das6402 driver, and source code for working QNX pci-6402 +* drivers by Greg Laird and Mariusz Bogacz. None of the code was +* used directly here, but it was useful as an additional source of +* documentation on how to program the boards. +* +* John Sims, for much testing and feedback on pcidas-4020 support. +* +* COMEDI - Linux Control and Measurement Device Interface +* Copyright (C) 1997-8 David A. Schleef <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ /* * Driver: cb_pcidas64
@@ -66,19 +66,18 @@*/ /* - -TODO: -make it return error if user attempts an ai command that uses the -external queue, and an ao command simultaneously user counter subdevice -there are a number of boards this driver will support when they are -fully released, but does not yet since the pci device id numbers -are not yet available. - -support prescaled 100khz clock for slow pacing (not available on 6000 -series?) - -make ao fifo size adjustable like ai fifo -*/ +* TODO: +* make it return error if user attempts an ai command that uses the +* external queue, and an ao command simultaneously user counter subdevice +* there are a number of boards this driver will support when they are +* fully released, but does not yet since the pci device id numbers +* are not yet available. +* +* support prescaled 100khz clock for slow pacing (not available on 6000 +* series?) +* +* make ao fifo size adjustable like ai fifo +*/ #include <linux/module.h> #include <linux/delay.h>
@@ -90,53 +89,55 @@ TODO:#include "plx9080.h" #define TIMER_BASE 25/* 40MHz master clock */ -/* 100kHz 'prescaled' clock for slow acquisition, -* maybe I'll support this someday */ +/* +* 100kHz 'prescaled' clock for slow acquisition, +* maybe I'll support this someday +*/ #define PRESCALED_TIMER_BASE 10000#define DMA_BUFFER_SIZE 0x1000 -/* maximum value that can be loaded into board's 24-bit counters*/ +/* maximum value that can be loaded into board's 24-bit counters */ static const int max_counter_value =0xffffff ;/* PCI-DAS64xxx base addresses */ /* devpriv->main_iobase registers */ enum write_only_registers { -INTR_ENABLE_REG =0x0 ,/* interrupt enable register */ -HW_CONFIG_REG =0x2 ,/* hardware config register */ +INTR_ENABLE_REG =0x0 ,/* interrupt enable register */ +HW_CONFIG_REG =0x2 ,/* hardware config register */ DAQ_SYNC_REG =0xc ,DAQ_ATRIG_LOW_4020_REG =0xc , -ADC_CONTROL0_REG =0x10 ,/* adc control register 0 */ -ADC_CONTROL1_REG =0x12 ,/* adc control register 1 */ +ADC_CONTROL0_REG =0x10 ,/* adc control register 0 */ +ADC_CONTROL1_REG =0x12 ,/* adc control register 1 */ CALIBRATION_REG =0x14 , -/* lower 16 bits of adc sample interval counter */ +/* lower 16 bits of adc sample interval counter */ ADC_SAMPLE_INTERVAL_LOWER_REG =0x16 , -/* upper 8 bits of adc sample interval counter */ +/* upper 8 bits of adc sample interval counter */ ADC_SAMPLE_INTERVAL_UPPER_REG =0x18 , -/* lower 16 bits of delay interval counter */ +/* lower 16 bits of delay interval counter */ ADC_DELAY_INTERVAL_LOWER_REG =0x1a , -/* upper 8 bits of delay interval counter */ +/* upper 8 bits of delay interval counter */ ADC_DELAY_INTERVAL_UPPER_REG =0x1c , -/* lower 16 bits of hardware conversion/scan counter */ +/* lower 16 bits of hardware conversion/scan counter */ ADC_COUNT_LOWER_REG =0x1e , -/* upper 8 bits of hardware conversion/scan counter */ +/* upper 8 bits of hardware conversion/scan counter */ ADC_COUNT_UPPER_REG =0x20 , -ADC_START_REG =0x22 ,/* software trigger to start acquisition */ -ADC_CONVERT_REG =0x24 ,/* initiates single conversion */ -ADC_QUEUE_CLEAR_REG =0x26 ,/* clears adc queue */ -ADC_QUEUE_LOAD_REG =0x28 ,/* loads adc queue */ +ADC_START_REG =0x22 ,/* software trigger to start acquisition */ +ADC_CONVERT_REG =0x24 ,/* initiates single conversion */ +ADC_QUEUE_CLEAR_REG =0x26 ,/* clears adc queue */ +ADC_QUEUE_LOAD_REG =0x28 ,/* loads adc queue */ ADC_BUFFER_CLEAR_REG =0x2a , -/* high channel for internal queue, use adc_chan_bits() inline above */ +/* high channel for internal queue, use adc_chan_bits() inline above */ ADC_QUEUE_HIGH_REG =0x2c , -DAC_CONTROL0_REG =0x50 ,/* dac control register 0 */ -DAC_CONTROL1_REG =0x52 ,/* dac control register 0 */ -/* lower 16 bits of dac sample interval counter */ +DAC_CONTROL0_REG =0x50 ,/* dac control register 0 */ +DAC_CONTROL1_REG =0x52 ,/* dac control register 0 */ +/* lower 16 bits of dac sample interval counter */ DAC_SAMPLE_INTERVAL_LOWER_REG =0x54 , -/* upper 8 bits of dac sample interval counter */ +/* upper 8 bits of dac sample interval counter */ DAC_SAMPLE_INTERVAL_UPPER_REG =0x56 ,DAC_SELECT_REG =0x60 ,DAC_START_REG =0x64 , -DAC_BUFFER_CLEAR_REG =0x66 ,/* clear dac buffer */ +DAC_BUFFER_CLEAR_REG =0x66 ,/* clear dac buffer */ };static inline unsigned int dac_convert_reg (unsigned int channel)
@@ -216,7 +217,8 @@ enum hw_config_contents {/* use 225 nanosec strobe when loading dac instead of 50 nanosec */ SLOW_DAC_BIT =0x400 ,/* bit with unknown function yet given as default value in pci-das64 -* manual */ +* manual +*/ HW_CONFIG_DUMMY_BITS =0x2000 ,/* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ DMA_CH_SELECT_BIT = 0x8000,
@@ -1138,12 +1140,14 @@ struct pcidas64_private {/* physical addresses of ai dma buffers */ dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT ];/* array of ai dma descriptors read by plx9080, -* allocated to get proper alignment */ +* allocated to get proper alignment +*/ struct plx_dma_desc *ai_dma_desc;/* physical address of ai dma descriptor array */ dma_addr_t ai_dma_desc_bus_addr;/* index of the ai dma descriptor/buffer -* that is currently being used */ +* that is currently being used +*/ unsigned int ai_dma_index;/* dma buffers for analog output */ uint16_t *ao_buffer[AO_DMA_RING_COUNT ];
@@ -1314,10 +1318,12 @@ static void init_plx9080(struct comedi_device *dev)/* enable dma chaining */ bits |=PLX_DMAMODE_CHAINEN ;/* enable interrupt on dma done -* (probably don't need this, since chain never finishes) */ +* (probably don't need this, since chain never finishes) +*/ bits |=PLX_DMAMODE_DONEIEN ;/* don't increment local address during transfers -* (we are transferring from a fixed fifo register) */ +* (we are transferring from a fixed fifo register) +*/ bits |=PLX_DMAMODE_LACONST ;/* route dma interrupt to pci bus */ bits |=PLX_DMAMODE_INTRPCI ;
Signature · 1 line
2.7.4
PATCH v3 2/8 staging: comedi: cb_pcidas64: Fix commenting style
In reply to Anson JacobRemove additional space after /*
Convert single line block comment into single line comment
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/cb_pcidas64.c | 431 +++++++++++++-------------- 1 file changed, 214 insertions(+), 217 deletions(-)
drivers/staging/comedi/drivers/cb_pcidas64.c +214 -217
@@ -169,8 +169,8 @@ enum read_only_registers { };enum read_write_registers { -I8255_4020_REG =0x48 ,/* 8255 offset, for 4020 only */ -/* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */ +I8255_4020_REG =0x48 ,/* 8255 offset, for 4020 only */ +/* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */ ADC_QUEUE_FIFO_REG =0x100 ,ADC_FIFO_REG =0x200 ,/* adc data fifo */ /* dac data fifo, has weird interactions with external channel queue */
@@ -189,51 +189,52 @@ enum dio_counter_registers {/* bit definitions for write-only registers */ enum intr_enable_contents { -ADC_INTR_SRC_MASK =0x3 ,/* adc interrupt source mask */ -ADC_INTR_QFULL_BITS =0x0 ,/* interrupt fifo quarter full */ -ADC_INTR_EOC_BITS =0x1 ,/* interrupt end of conversion */ -ADC_INTR_EOSCAN_BITS =0x2 ,/* interrupt end of scan */ -ADC_INTR_EOSEQ_BITS =0x3 ,/* interrupt end of sequence mask */ -EN_ADC_INTR_SRC_BIT =0x4 ,/* enable adc interrupt source */ -EN_ADC_DONE_INTR_BIT =0x8 ,/* enable adc acquisition done intr */ +ADC_INTR_SRC_MASK =0x3 ,/* adc interrupt source mask */ +ADC_INTR_QFULL_BITS =0x0 ,/* interrupt fifo quarter full */ +ADC_INTR_EOC_BITS =0x1 ,/* interrupt end of conversion */ +ADC_INTR_EOSCAN_BITS =0x2 ,/* interrupt end of scan */ +ADC_INTR_EOSEQ_BITS =0x3 ,/* interrupt end of sequence mask */ +EN_ADC_INTR_SRC_BIT =0x4 ,/* enable adc interrupt source */ +EN_ADC_DONE_INTR_BIT =0x8 ,/* enable adc acquisition done intr */ DAC_INTR_SRC_MASK =0x30 ,DAC_INTR_QEMPTY_BITS =0x0 ,DAC_INTR_HIGH_CHAN_BITS =0x10 , -EN_DAC_INTR_SRC_BIT =0x40 ,/* enable dac interrupt source */ +EN_DAC_INTR_SRC_BIT =0x40 ,/* enable dac interrupt source */ EN_DAC_DONE_INTR_BIT =0x80 , -EN_ADC_ACTIVE_INTR_BIT =0x200 ,/* enable adc active interrupt */ -EN_ADC_STOP_INTR_BIT =0x400 ,/* enable adc stop trigger interrupt */ -EN_DAC_ACTIVE_INTR_BIT =0x800 ,/* enable dac active interrupt */ -EN_DAC_UNDERRUN_BIT =0x4000 ,/* enable dac underrun status bit */ -EN_ADC_OVERRUN_BIT =0x8000 ,/* enable adc overrun status bit */ +EN_ADC_ACTIVE_INTR_BIT =0x200 ,/* enable adc active interrupt */ +EN_ADC_STOP_INTR_BIT =0x400 ,/* enable adc stop trigger interrupt */ +EN_DAC_ACTIVE_INTR_BIT =0x800 ,/* enable dac active interrupt */ +EN_DAC_UNDERRUN_BIT =0x4000 ,/* enable dac underrun status bit */ +EN_ADC_OVERRUN_BIT =0x8000 ,/* enable adc overrun status bit */ };enum hw_config_contents { -MASTER_CLOCK_4020_MASK =0x3 ,/* master clock source mask for 4020 */ -INTERNAL_CLOCK_4020_BITS =0x1 ,/* use 40 MHz internal master clock */ -BNC_CLOCK_4020_BITS =0x2 ,/* use BNC input for master clock */ -EXT_CLOCK_4020_BITS =0x3 ,/* use dio input for master clock */ -EXT_QUEUE_BIT =0x200 ,/* use external channel/gain queue */ -/* use 225 nanosec strobe when loading dac instead of 50 nanosec */ +MASTER_CLOCK_4020_MASK =0x3 ,/* master clock source mask for 4020 */ +INTERNAL_CLOCK_4020_BITS =0x1 ,/* use 40 MHz internal master clock */ +BNC_CLOCK_4020_BITS =0x2 ,/* use BNC input for master clock */ +EXT_CLOCK_4020_BITS =0x3 ,/* use dio input for master clock */ +EXT_QUEUE_BIT =0x200 ,/* use external channel/gain queue */ +/* use 225 nanosec strobe when loading dac instead of 50 nanosec */ SLOW_DAC_BIT =0x400 , -/* bit with unknown function yet given as default value in pci-das64 -* manual +/* +* bit with unknown function yet given as default value in pci-das64 +* manual */ HW_CONFIG_DUMMY_BITS =0x2000 , -/* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ +/* bit selects channels 1/0 for analog input/output, otherwise 0/1 */ DMA_CH_SELECT_BIT =0x8000 , -FIFO_SIZE_REG =0x4 ,/* allows adjustment of fifo sizes */ -DAC_FIFO_SIZE_MASK =0xff00 ,/* bits that set dac fifo size */ -DAC_FIFO_BITS =0xf800 ,/* 8k sample ao fifo */ +FIFO_SIZE_REG =0x4 ,/* allows adjustment of fifo sizes */ +DAC_FIFO_SIZE_MASK =0xff00 ,/* bits that set dac fifo size */ +DAC_FIFO_BITS =0xf800 ,/* 8k sample ao fifo */ };#define DAC_FIFO_SIZE 0x2000enum daq_atrig_low_4020_contents { -/* use trig/ext clk bnc input for analog gate signal */ +/* use trig/ext clk bnc input for analog gate signal */ EXT_AGATE_BNC_BIT =0x8000 , -/* use trig/ext clk bnc input for external stop trigger signal */ +/* use trig/ext clk bnc input for external stop trigger signal */ EXT_STOP_TRIG_BNC_BIT =0x4000 , -/* use trig/ext clk bnc input for external start trigger signal */ +/* use trig/ext clk bnc input for external start trigger signal */ EXT_START_TRIG_BNC_BIT =0x2000 , };
@@ -243,38 +244,38 @@ static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold) }enum adc_control0_contents { -ADC_GATE_SRC_MASK =0x3 ,/* bits that select gate */ -ADC_SOFT_GATE_BITS =0x1 ,/* software gate */ -ADC_EXT_GATE_BITS =0x2 ,/* external digital gate */ -ADC_ANALOG_GATE_BITS =0x3 ,/* analog level gate */ -/* level-sensitive gate (for digital) */ +ADC_GATE_SRC_MASK =0x3 ,/* bits that select gate */ +ADC_SOFT_GATE_BITS =0x1 ,/* software gate */ +ADC_EXT_GATE_BITS =0x2 ,/* external digital gate */ +ADC_ANALOG_GATE_BITS =0x3 ,/* analog level gate */ +/* level-sensitive gate (for digital) */ ADC_GATE_LEVEL_BIT =0x4 , -ADC_GATE_POLARITY_BIT =0x8 ,/* gate active low */ +ADC_GATE_POLARITY_BIT =0x8 ,/* gate active low */ ADC_START_TRIG_SOFT_BITS =0x10 ,ADC_START_TRIG_EXT_BITS =0x20 ,ADC_START_TRIG_ANALOG_BITS =0x30 ,ADC_START_TRIG_MASK =0x30 , -ADC_START_TRIG_FALLING_BIT =0x40 ,/* trig 1 uses falling edge */ -/* external pacing uses falling edge */ +ADC_START_TRIG_FALLING_BIT =0x40 ,/* trig 1 uses falling edge */ +/* external pacing uses falling edge */ ADC_EXT_CONV_FALLING_BIT =0x800 , -/* enable hardware scan counter */ +/* enable hardware scan counter */ ADC_SAMPLE_COUNTER_EN_BIT =0x1000 , -ADC_DMA_DISABLE_BIT =0x4000 ,/* disables dma */ -ADC_ENABLE_BIT =0x8000 ,/* master adc enable */ +ADC_DMA_DISABLE_BIT =0x4000 ,/* disables dma */ +ADC_ENABLE_BIT =0x8000 ,/* master adc enable */ };enum adc_control1_contents { -/* should be set for boards with > 16 channels */ +/* should be set for boards with > 16 channels */ ADC_QUEUE_CONFIG_BIT =0x1 ,CONVERT_POLARITY_BIT =0x10 ,EOC_POLARITY_BIT =0x20 , -ADC_SW_GATE_BIT =0x40 ,/* software gate of adc */ -ADC_DITHER_BIT =0x200 ,/* turn on extra noise for dithering */ +ADC_SW_GATE_BIT =0x40 ,/* software gate of adc */ +ADC_DITHER_BIT =0x200 ,/* turn on extra noise for dithering */ RETRIGGER_BIT =0x800 ,ADC_LO_CHANNEL_4020_MASK =0x300 ,ADC_HI_CHANNEL_4020_MASK =0xc00 , -TWO_CHANNEL_4020_BITS =0x1000 ,/* two channel mode for 4020 */ -FOUR_CHANNEL_4020_BITS =0x2000 ,/* four channel mode for 4020 */ +TWO_CHANNEL_4020_BITS =0x1000 ,/* two channel mode for 4020 */ +FOUR_CHANNEL_4020_BITS =0x2000 ,/* four channel mode for 4020 */ CHANNEL_MODE_4020_MASK =0x3000 ,ADC_MODE_MASK =0xf000 , };
@@ -298,10 +299,10 @@ enum calibration_contents {SELECT_8800_BIT =0x1 ,SELECT_8402_64XX_BIT =0x2 ,SELECT_1590_60XX_BIT =0x2 , -CAL_EN_64XX_BIT =0x40 ,/* calibration enable for 64xx series */ +CAL_EN_64XX_BIT =0x40 ,/* calibration enable for 64xx series */ SERIAL_DATA_IN_BIT =0x80 ,SERIAL_CLOCK_BIT =0x100 , -CAL_EN_60XX_BIT =0x200 ,/* calibration enable for 60xx series */ +CAL_EN_60XX_BIT =0x200 ,/* calibration enable for 60xx series */ CAL_GAIN_BIT = 0x800, };
@@ -328,12 +329,12 @@ static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel) };enum adc_queue_load_contents { -UNIP_BIT =0x800 ,/* unipolar/bipolar bit */ -ADC_SE_DIFF_BIT =0x1000 ,/* single-ended/ differential bit */ -/* non-referenced single-ended (common-mode input) */ +UNIP_BIT =0x800 ,/* unipolar/bipolar bit */ +ADC_SE_DIFF_BIT =0x1000 ,/* single-ended/ differential bit */ +/* non-referenced single-ended (common-mode input) */ ADC_COMMON_BIT =0x2000 , -QUEUE_EOSEQ_BIT =0x4000 ,/* queue end of sequence */ -QUEUE_EOSCAN_BIT =0x8000 ,/* queue end of scan */ +QUEUE_EOSEQ_BIT =0x4000 ,/* queue end of sequence */ +QUEUE_EOSCAN_BIT =0x8000 ,/* queue end of scan */ };static inline uint16_t adc_chan_bits (unsigned int channel)
@@ -342,7 +343,7 @@ static inline uint16_t adc_chan_bits(unsigned int channel) };enum dac_control0_contents { -DAC_ENABLE_BIT =0x8000 ,/* dac controller enable bit */ +DAC_ENABLE_BIT =0x8000 ,/* dac controller enable bit */ DAC_CYCLIC_STOP_BIT =0x4000 ,DAC_WAVEFORM_MODE_BIT =0x100 ,DAC_EXT_UPDATE_FALLING_BIT =0x80 ,
@@ -362,7 +363,7 @@ enum dac_control1_contents {DAC_WRITE_POLARITY_BIT =0x800 ,/* board-dependent setting */ DAC1_EXT_REF_BIT =0x200 ,DAC0_EXT_REF_BIT =0x100 , -DAC_OUTPUT_ENABLE_BIT =0x80 ,/* dac output enable bit */ +DAC_OUTPUT_ENABLE_BIT =0x80 ,/* dac output enable bit */ DAC_UPDATE_POLARITY_BIT =0x40 ,/* board-dependent setting */ DAC_SW_GATE_BIT =0x20 , DAC1_UNIPOLAR_BIT = 0x8,
@@ -411,9 +412,9 @@ enum i2c_addresses { };enum range_cal_i2c_contents { -/* bits that set what source the adc converter measures */ +/* bits that set what source the adc converter measures */ ADC_SRC_4020_MASK =0x70 , -/* make bnc trig/ext clock threshold 0V instead of 2.5V */ +/* make bnc trig/ext clock threshold 0V instead of 2.5V */ BNC_TRIG_THRESHOLD_0V_BIT =0x80 , };
@@ -424,7 +425,7 @@ static inline uint8_t adc_src_4020_bits(unsigned int source)static inline uint8_t attenuate_bit (unsigned int channel) { -/* attenuate channel (+-5V input range) */ +/* attenuate channel (+-5V input range) */ return 1 << (channel &0x3 ); };
@@ -629,18 +630,18 @@ enum pcidas64_boardid {struct pcidas64_board {const char *name; -int ai_se_chans;/* number of ai inputs in single-ended mode */ -int ai_bits;/* analog input resolution */ -int ai_speed;/* fastest conversion period in ns */ +int ai_se_chans;/* number of ai inputs in single-ended mode */ +int ai_bits;/* analog input resolution */ +int ai_speed;/* fastest conversion period in ns */ const struct comedi_lrange *ai_range_table;const uint8_t *ai_range_code; -int ao_nchan;/* number of analog out channels */ -int ao_bits;/* analog output resolution */ -int ao_scan_speed;/* analog output scan speed */ +int ao_nchan;/* number of analog out channels */ +int ao_bits;/* analog output resolution */ +int ao_scan_speed;/* analog output scan speed */ const struct comedi_lrange *ao_range_table;const int *ao_range_code;const struct hw_fifo_info *const ai_fifo; -/* different board families have slightly different registers */ +/* different board families have slightly different registers */ enum register_layout layout;unsigned has_8255:1 ; };
@@ -701,7 +702,7 @@ static const struct pcidas64_board pcidas64_boards[] = { .has_8255 = 1, }, [BOARD_PCIDAS6402_12] = { - .name = "pci-das6402/12", /* XXX check */ + .name = "pci-das6402/12", /* XXX check */ .ai_se_chans = 64, .ai_bits = 12, .ai_speed = 5000,
@@ -998,7 +999,7 @@ static const struct pcidas64_board pcidas64_boards[] = { .ai_speed = 50, .ao_bits = 12, .ao_nchan = 2, - .ao_scan_speed = 0, /* no hardware pacing on ao */ + .ao_scan_speed = 0, /* no hardware pacing on ao */ .layout = LAYOUT_4020, .ai_range_table = &ai_ranges_4020, .ao_range_table = &ao_ranges_4020,
@@ -1007,9 +1008,7 @@ static const struct pcidas64_board pcidas64_boards[] = { .has_8255 = 1, },#if 0 -/* -* The device id for these boards is unknown - */ + /* The device id for these boards is unknown */ [BOARD_PCIDAS6402_16_JR] = { .name = "pci-das6402/16/jr",
@@ -1118,64 +1117,66 @@ static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev, }struct ext_clock_info { -/* master clock divisor to use for scans with external master clock */ +/* master clock divisor to use for scans with external master clock */ unsigned int divisor; -/* chanspec for master clock input when used as scan begin src */ +/* chanspec for master clock input when used as scan begin src */ unsigned int chanspec; };/* this structure is for data unique to this hardware driver. */ struct pcidas64_private { -/* base addresses (physical) */ +/* base addresses (physical) */ resource_size_t main_phys_iobase;resource_size_t dio_counter_phys_iobase; -/* base addresses (ioremapped) */ +/* base addresses (ioremapped) */ void __iomem *plx9080_iobase;void __iomem *main_iobase; -/* local address (used by dma controller) */ +/* local address (used by dma controller) */ uint32_t local0_iobase;uint32_t local1_iobase; -/* dma buffers for analog input */ +/* dma buffers for analog input */ uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT ]; -/* physical addresses of ai dma buffers */ +/* physical addresses of ai dma buffers */ dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT ]; -/* array of ai dma descriptors read by plx9080, -* allocated to get proper alignment +/* +* array of ai dma descriptors read by plx9080, +* allocated to get proper alignment */ struct plx_dma_desc *ai_dma_desc; -/* physical address of ai dma descriptor array */ +/* physical address of ai dma descriptor array */ dma_addr_t ai_dma_desc_bus_addr; -/* index of the ai dma descriptor/buffer -* that is currently being used +/* +* index of the ai dma descriptor/buffer +* that is currently being used */ unsigned int ai_dma_index; -/* dma buffers for analog output */ +/* dma buffers for analog output */ uint16_t *ao_buffer[AO_DMA_RING_COUNT ]; -/* physical addresses of ao dma buffers */ +/* physical addresses of ao dma buffers */ dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT ];struct plx_dma_desc *ao_dma_desc;dma_addr_t ao_dma_desc_bus_addr; -/* keeps track of buffer where the next ao sample should go */ +/* keeps track of buffer where the next ao sample should go */ unsigned int ao_dma_index; -unsigned int hw_revision;/* stc chip hardware revision number */ -/* last bits sent to INTR_ENABLE_REG register */ +unsigned int hw_revision;/* stc chip hardware revision number */ +/* last bits sent to INTR_ENABLE_REG register */ unsigned int intr_enable_bits; -/* last bits sent to ADC_CONTROL1_REG register */ +/* last bits sent to ADC_CONTROL1_REG register */ uint16_t adc_control1_bits; -/* last bits sent to FIFO_SIZE_REG register */ +/* last bits sent to FIFO_SIZE_REG register */ uint16_t fifo_size_bits; -/* last bits sent to HW_CONFIG_REG register */ +/* last bits sent to HW_CONFIG_REG register */ uint16_t hw_config_bits;uint16_t dac_control1_bits; -/* last bits written to plx9080 control register */ +/* last bits written to plx9080 control register */ uint32_t plx_control_bits; -/* last bits written to plx interrupt control and status register */ +/* last bits written to plx interrupt control and status register */ uint32_t plx_intcsr_bits; -/* index of calibration source readable through ai ch0 */ +/* index of calibration source readable through ai ch0 */ int calibration_source; -/* bits written to i2c calibration/range register */ +/* bits written to i2c calibration/range register */ uint8_t i2c_cal_range_bits; -/* configure digital triggers to trigger on falling edge */ +/* configure digital triggers to trigger on falling edge */ unsigned int ext_trig_falling;short ai_cmd_running;unsigned int ai_fifo_segment_length;
@@ -1228,7 +1229,7 @@ static void abort_dma(struct comedi_device *dev, unsigned int channel)struct pcidas64_private *devpriv = dev->private;unsigned long flags; -/* spinlock for plx dma control/status reg */ +/* spinlock for plx dma control/status reg */ spin_lock_irqsave (&dev->spinlock, flags);plx9080_abort_dma (devpriv->plx9080_iobase, channel);
@@ -1275,7 +1276,7 @@ static void enable_ai_interrupts(struct comedi_device *dev,* if CMDF_WAKE_EOS flag is set. */ if (cmd->flags &CMDF_WAKE_EOS ) { -/* 4020 doesn't support pio transfers except for fifo dregs */ +/* 4020 doesn't support pio transfers except for fifo dregs */ if (board->layout !=LAYOUT_4020 ) bits |=ADC_INTR_EOSCAN_BITS |EN_ADC_INTR_SRC_BIT ; }
@@ -1309,38 +1310,40 @@ static void init_plx9080(struct comedi_device *dev)abort_dma (dev,0 );abort_dma (dev,1 ); -/* configure dma0 mode */ +/* configure dma0 mode */ bits =0 ; -/* enable ready input, not sure if this is necessary */ +/* enable ready input, not sure if this is necessary */ bits |=PLX_DMAMODE_READYIEN ; -/* enable bterm, not sure if this is necessary */ +/* enable bterm, not sure if this is necessary */ bits |=PLX_DMAMODE_BTERMIEN ; -/* enable dma chaining */ +/* enable dma chaining */ bits |=PLX_DMAMODE_CHAINEN ; -/* enable interrupt on dma done -* (probably don't need this, since chain never finishes) +/* +* enable interrupt on dma done +* (probably don't need this, since chain never finishes) */ bits |=PLX_DMAMODE_DONEIEN ; -/* don't increment local address during transfers -* (we are transferring from a fixed fifo register) +/* +* don't increment local address during transfers +* (we are transferring from a fixed fifo register) */ bits |=PLX_DMAMODE_LACONST ; -/* route dma interrupt to pci bus */ +/* route dma interrupt to pci bus */ bits |=PLX_DMAMODE_INTRPCI ; -/* enable demand mode */ +/* enable demand mode */ bits |=PLX_DMAMODE_DEMAND ; -/* enable local burst mode */ +/* enable local burst mode */ bits |=PLX_DMAMODE_BURSTEN ; -/* 4020 uses 32 bit dma */ +/* 4020 uses 32 bit dma */ if (board->layout ==LAYOUT_4020 ) bits |=PLX_DMAMODE_WIDTH_32 ; -else /* localspace0 bus is 16 bits wide */ +else /* localspace0 bus is 16 bits wide */ bits |=PLX_DMAMODE_WIDTH_16 ;writel (bits, plx_iobase +PLX_REG_DMAMODE1 );if (ao_cmd_is_supported (board))writel (bits, plx_iobase +PLX_REG_DMAMODE0 ); -/* enable interrupts on plx 9080 */ +/* enable interrupts on plx 9080 */ devpriv->plx_intcsr_bits |=PLX_INTCSR_LSEABORTEN |PLX_INTCSR_LSEPARITYEN |PLX_INTCSR_PIEN | PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
@@ -1382,7 +1385,7 @@ static int set_ai_fifo_segment_length(struct comedi_device *dev,if (num_entries > fifo->max_segment_length) num_entries = fifo->max_segment_length; -/* 1 == 256 entries, 2 == 512 entries, etc */ +/* 1 == 256 entries, 2 == 512 entries, etc */ num_increments =DIV_ROUND_CLOSEST (num_entries, increment_size); bits = (~(num_increments -1 )) & fifo->fifo_size_reg_mask;
@@ -1448,7 +1451,7 @@ static void init_stc_registers(struct comedi_device *dev)writew (devpriv->adc_control1_bits, devpriv->main_iobase +ADC_CONTROL1_REG ); -/* 6402/16 manual says this register must be initialized to 0xff? */ +/* 6402/16 manual says this register must be initialized to 0xff? */ writew (0xff , devpriv->main_iobase +ADC_SAMPLE_INTERVAL_UPPER_REG ); bits =SLOW_DAC_BIT |DMA_CH_SELECT_BIT ;
@@ -1463,7 +1466,7 @@ static void init_stc_registers(struct comedi_device *dev)spin_unlock_irqrestore (&dev->spinlock, flags); -/* set fifos to maximum size */ +/* set fifos to maximum size */ devpriv->fifo_size_bits |=DAC_FIFO_BITS ;set_ai_fifo_segment_length (dev, board->ai_fifo->max_segment_length);
@@ -1484,7 +1487,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev)struct pcidas64_private *devpriv = dev->private;int i; -/* allocate pci dma buffers */ +/* allocate pci dma buffers */ for (i =0 ; i <ai_dma_ring_count (board); i++) { devpriv->ai_buffer[i] = dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
@@ -1505,7 +1508,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev)return -ENOMEM ; } } -/* allocate dma descriptors */ +/* allocate dma descriptors */ devpriv->ai_dma_desc = dma_alloc_coherent(&pcidev->dev, sizeof(struct plx_dma_desc) * ai_dma_ring_count(board),
@@ -1523,7 +1526,7 @@ static int alloc_and_init_dma_members(struct comedi_device *dev)if (!devpriv->ao_dma_desc)return -ENOMEM ; } -/* initialize dma descriptors */ +/* initialize dma descriptors */ for (i =0 ; i <ai_dma_ring_count (board); i++) { devpriv->ai_dma_desc[i].pci_start_addr =cpu_to_le32 (devpriv->ai_buffer_bus_addr[i]);
@@ -1624,13 +1627,11 @@ static void i2c_set_sda(struct comedi_device *dev, int state)void __iomem *plx_control_addr = devpriv->plx9080_iobase +PLX_REG_CNTRL ; -if (state) { -/* set data line high */ +if (state) {/* set data line high */ devpriv->plx_control_bits &= ~data_bit;writel (devpriv->plx_control_bits, plx_control_addr);udelay (i2c_high_udelay); - }else {/* set data line low */ - + }else {/* set data line low */ devpriv->plx_control_bits |= data_bit;writel (devpriv->plx_control_bits, plx_control_addr);udelay (i2c_low_udelay);
@@ -1645,13 +1646,11 @@ static void i2c_set_scl(struct comedi_device *dev, int state)void __iomem *plx_control_addr = devpriv->plx9080_iobase +PLX_REG_CNTRL ; -if (state) { -/* set clock line high */ +if (state) {/* set clock line high */ devpriv->plx_control_bits &= ~clock_bit;writel (devpriv->plx_control_bits, plx_control_addr);udelay (i2c_high_udelay); - }else {/* set clock line low */ - + }else {/* set clock line low */ devpriv->plx_control_bits |= clock_bit;writel (devpriv->plx_control_bits, plx_control_addr);udelay (i2c_low_udelay);
@@ -1680,7 +1679,7 @@ static int i2c_read_ack(struct comedi_device *dev)i2c_set_sda (dev,1 );i2c_set_scl (dev,1 ); -return 0 ;/* return fake acknowledge bit */ +return 0 ;/* return fake acknowledge bit */ }/* send start bit */
@@ -1713,23 +1712,23 @@ static void i2c_write(struct comedi_device *dev, unsigned int address,* eeprom and i2c bus */ -/* make sure we dont send anything to eeprom */ +/* make sure we dont send anything to eeprom */ devpriv->plx_control_bits &= ~PLX_CNTRL_EECS ;i2c_stop (dev);i2c_start (dev); -/* send address and write bit */ +/* send address and write bit */ bitstream = (address <<1 ) & ~read_bit;i2c_write_byte (dev, bitstream); -/* get acknowledge */ +/* get acknowledge */ if (i2c_read_ack (dev) !=0 ) {dev_err (dev->class_dev,"failed: no acknowledge\n" );i2c_stop (dev);return ; } -/* write data bytes */ +/* write data bytes */ for (i =0 ; i < length; i++) {i2c_write_byte (dev, data[i]);if (i2c_read_ack (dev) !=0 ) {
@@ -1776,8 +1775,8 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, range =CR_RANGE (insn->chanspec); aref =CR_AREF (insn->chanspec); -/* disable card's analog input interrupt sources and pacing */ -/* 4020 generates dac done interrupts even though they are disabled */ +/* disable card's analog input interrupt sources and pacing */ +/* 4020 generates dac done interrupts even though they are disabled */ disable_ai_pacing (dev);spin_lock_irqsave (&dev->spinlock, flags);
@@ -1790,12 +1789,12 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,spin_unlock_irqrestore (&dev->spinlock, flags);if (board->layout !=LAYOUT_4020 ) { -/* use internal queue */ +/* use internal queue */ devpriv->hw_config_bits &= ~EXT_QUEUE_BIT ;writew (devpriv->hw_config_bits, devpriv->main_iobase +HW_CONFIG_REG ); -/* ALT_SOURCE is internal calibration reference */ +/* ALT_SOURCE is internal calibration reference */ if (insn->chanspec &CR_ALT_SOURCE ) {unsigned int cal_en_bit;
@@ -1817,19 +1816,19 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,*/ writew (0 , devpriv->main_iobase +CALIBRATION_REG ); } -/* load internal queue */ +/* load internal queue */ bits =0 ; -/* set gain */ +/* set gain */ bits |=ai_range_bits_6xxx (dev,CR_RANGE (insn->chanspec)); -/* set single-ended / differential */ +/* set single-ended / differential */ bits |=se_diff_bit_6xxx (dev, aref ==AREF_DIFF );if (aref ==AREF_COMMON ) bits |=ADC_COMMON_BIT ; bits |=adc_chan_bits (channel); -/* set stop channel */ +/* set stop channel */ writew (adc_chan_bits (channel), devpriv->main_iobase +ADC_QUEUE_HIGH_REG ); -/* set start channel, and rest of settings */ +/* set start channel, and rest of settings */ writew (bits, devpriv->main_iobase +ADC_QUEUE_LOAD_REG ); }else {uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
@@ -1841,7 +1840,7 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, }else {/* select BNC inputs */ devpriv->i2c_cal_range_bits |=adc_src_4020_bits (4 ); } -/* select range */ +/* select range */ if (range ==0 ) devpriv->i2c_cal_range_bits |=attenuate_bit (channel);else
@@ -1868,14 +1867,14 @@ static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, }for (n =0 ; n < insn->n; n++) { -/* clear adc buffer (inside loop for 4020 sake) */ +/* clear adc buffer (inside loop for 4020 sake) */ writew (0 , devpriv->main_iobase +ADC_BUFFER_CLEAR_REG );/* trigger conversion, bits sent only matter for 4020 */ writew (adc_convert_chan_4020_bits (CR_CHAN (insn->chanspec)), devpriv->main_iobase +ADC_CONVERT_REG ); -/* wait for data */ +/* wait for data */ ret =comedi_timeout (dev, s, insn, cb_pcidas64_ai_eoc,0 );if (ret)return ret;
@@ -2255,7 +2254,7 @@ static void setup_sample_counters(struct comedi_device *dev, {struct pcidas64_private *devpriv = dev->private; -/* load hardware conversion counter */ +/* load hardware conversion counter */ if (use_hw_sample_counter (cmd)) {writew (cmd->stop_arg &0xffff , devpriv->main_iobase +ADC_COUNT_LOWER_REG );
@@ -2283,7 +2282,7 @@ static inline unsigned int dma_transfer_size(struct comedi_device *dev)static uint32_t ai_convert_counter_6xxx (const struct comedi_device *dev,const struct comedi_cmd *cmd) { -/* supposed to load counter with desired divisor minus 3 */ +/* supposed to load counter with desired divisor minus 3 */ return cmd->convert_arg /TIMER_BASE -3 ; }
@@ -2292,7 +2291,7 @@ static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev, {uint32_t count; -/* figure out how long we need to delay at end of scan */ +/* figure out how long we need to delay at end of scan */ switch (cmd->scan_begin_src) {case TRIG_TIMER : count = (cmd->scan_begin_arg -
@@ -2321,13 +2320,13 @@ static uint32_t ai_convert_counter_4020(struct comedi_device *dev,case TRIG_OTHER : divisor = devpriv->ext_clock.divisor;break ; -default :/* should never happen */ +default :/* should never happen */ dev_err (dev->class_dev,"bug! failed to set ai pacing!\n" ); divisor =1000 ;break ; } -/* supposed to load counter with desired divisor minus 2 for 4020 */ +/* supposed to load counter with desired divisor minus 2 for 4020 */ return divisor -2 ; }
@@ -2336,7 +2335,7 @@ static void select_master_clock_4020(struct comedi_device *dev, {struct pcidas64_private *devpriv = dev->private; -/* select internal/external master clock */ +/* select internal/external master clock */ devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK ;if (cmd->scan_begin_src ==TRIG_OTHER ) {int chanspec = devpriv->ext_clock.chanspec;
@@ -2372,7 +2371,7 @@ static inline void dma_start_sync(struct comedi_device *dev,struct pcidas64_private *devpriv = dev->private;unsigned long flags; -/* spinlock for plx dma control/status reg */ +/* spinlock for plx dma control/status reg */ spin_lock_irqsave (&dev->spinlock, flags);writeb (PLX_DMACSR_ENABLE |PLX_DMACSR_START |PLX_DMACSR_CLEARINTR , devpriv->plx9080_iobase +PLX_REG_DMACSR (channel));
@@ -2396,16 +2395,16 @@ static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd) scan_counter =ai_scan_counter_6xxx (dev, cmd); } -/* load lower 16 bits of convert interval */ +/* load lower 16 bits of convert interval */ writew (convert_counter &0xffff , devpriv->main_iobase +ADC_SAMPLE_INTERVAL_LOWER_REG ); -/* load upper 8 bits of convert interval */ +/* load upper 8 bits of convert interval */ writew ((convert_counter >>16 ) &0xff , devpriv->main_iobase +ADC_SAMPLE_INTERVAL_UPPER_REG ); -/* load lower 16 bits of scan delay */ +/* load lower 16 bits of scan delay */ writew (scan_counter &0xffff , devpriv->main_iobase +ADC_DELAY_INTERVAL_LOWER_REG ); -/* load upper 8 bits of scan delay */ +/* load upper 8 bits of scan delay */ writew ((scan_counter >>16 ) &0xff , devpriv->main_iobase +ADC_DELAY_INTERVAL_UPPER_REG ); }
@@ -2441,26 +2440,26 @@ static int setup_channel_queue(struct comedi_device *dev,writew (devpriv->hw_config_bits, devpriv->main_iobase +HW_CONFIG_REG ); bits =0 ; -/* set channel */ +/* set channel */ bits |=adc_chan_bits (CR_CHAN (cmd->chanlist[0 ])); -/* set gain */ +/* set gain */ bits |=ai_range_bits_6xxx (dev,CR_RANGE (cmd->chanlist[0 ])); -/* set single-ended / differential */ +/* set single-ended / differential */ bits |=se_diff_bit_6xxx (dev,CR_AREF (cmd->chanlist[0 ]) ==AREF_DIFF );if (CR_AREF (cmd->chanlist[0 ]) ==AREF_COMMON ) bits |=ADC_COMMON_BIT ; -/* set stop channel */ +/* set stop channel */ writew (adc_chan_bits (CR_CHAN (cmd->chanlist[cmd->chanlist_len -1 ])), devpriv->main_iobase +ADC_QUEUE_HIGH_REG ); -/* set start channel, and rest of settings */ +/* set start channel, and rest of settings */ writew (bits, devpriv->main_iobase +ADC_QUEUE_LOAD_REG ); }else { -/* use external queue */ +/* use external queue */ if (dev->write_subdev && dev->write_subdev->busy) {warn_external_queue (dev);return -EBUSY ;
@@ -2468,30 +2467,30 @@ static int setup_channel_queue(struct comedi_device *dev, devpriv->hw_config_bits |=EXT_QUEUE_BIT ;writew (devpriv->hw_config_bits, devpriv->main_iobase +HW_CONFIG_REG ); -/* clear DAC buffer to prevent weird interactions */ +/* clear DAC buffer to prevent weird interactions */ writew (0 , devpriv->main_iobase +DAC_BUFFER_CLEAR_REG ); -/* clear queue pointer */ +/* clear queue pointer */ writew (0 , devpriv->main_iobase +ADC_QUEUE_CLEAR_REG ); -/* load external queue */ +/* load external queue */ for (i =0 ; i < cmd->chanlist_len; i++) { bits =0 ; -/* set channel */ +/* set channel */ bits |=adc_chan_bits (CR_CHAN (cmd-> chanlist[i])); -/* set gain */ +/* set gain */ bits |=ai_range_bits_6xxx (dev,CR_RANGE (cmd-> chanlist [i])); -/* set single-ended / differential */ +/* set single-ended / differential */ bits |=se_diff_bit_6xxx (dev,CR_AREF (cmd-> chanlist[i]) ==AREF_DIFF );if (CR_AREF (cmd->chanlist[i]) ==AREF_COMMON ) bits |=ADC_COMMON_BIT ; -/* mark end of queue */ +/* mark end of queue */ if (i == cmd->chanlist_len -1 ) bits |=QUEUE_EOSCAN_BIT |QUEUE_EOSEQ_BIT ;
@@ -2504,7 +2503,7 @@ static int setup_channel_queue(struct comedi_device *dev,* but required for reliable operation */ writew (0 , devpriv->main_iobase +ADC_QUEUE_CLEAR_REG ); -/* prime queue holding register */ +/* prime queue holding register */ writew (0 , devpriv->main_iobase +ADC_QUEUE_LOAD_REG ); } }else {
@@ -2513,7 +2512,7 @@ static int setup_channel_queue(struct comedi_device *dev, devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK ;/* select BNC inputs */ devpriv->i2c_cal_range_bits |=adc_src_4020_bits (4 ); -/* select ranges */ +/* select ranges */ for (i =0 ; i < cmd->chanlist_len; i++) {unsigned int channel =CR_CHAN (cmd->chanlist[i]);unsigned int range =CR_RANGE (cmd->chanlist[i]);
@@ -2585,7 +2584,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)if (retval <0 )return retval; -/* make sure internal calibration source is turned off */ +/* make sure internal calibration source is turned off */ writew (0 , devpriv->main_iobase +CALIBRATION_REG );set_ai_pacing (dev, cmd);
@@ -2601,10 +2600,10 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)if (board->layout !=LAYOUT_4020 ) { devpriv->adc_control1_bits &= ~ADC_MODE_MASK ;if (cmd->convert_src ==TRIG_EXT ) -/* good old mode 13 */ +/* good old mode 13 */ devpriv->adc_control1_bits |=adc_mode_bits (13 );else -/* mode 8. What else could you need? */ +/* mode 8. What else could you need? */ devpriv->adc_control1_bits |=adc_mode_bits (8 ); }else { devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK ;
@@ -2624,20 +2623,20 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->main_iobase + ADC_CONTROL1_REG);spin_unlock_irqrestore (&dev->spinlock, flags); -/* clear adc buffer */ +/* clear adc buffer */ writew (0 , devpriv->main_iobase +ADC_BUFFER_CLEAR_REG );if ((cmd->flags &CMDF_WAKE_EOS ) ==0 || board->layout ==LAYOUT_4020 ) { devpriv->ai_dma_index =0 ; -/* set dma transfer size */ +/* set dma transfer size */ for (i =0 ; i <ai_dma_ring_count (board); i++) devpriv->ai_dma_desc[i].transfer_size =cpu_to_le32 (dma_transfer_size (dev) *sizeof (uint16_t )); -/* give location of first dma descriptor */ +/* give location of first dma descriptor */ load_first_dma_descriptor(dev, 1, devpriv->ai_dma_desc_bus_addr | PLX_DMADPR_DESCPCI |
@@ -2663,7 +2662,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) bits =ADC_ENABLE_BIT |ADC_SOFT_GATE_BITS |ADC_GATE_LEVEL_BIT ;if (cmd->flags &CMDF_WAKE_EOS ) bits |=ADC_DMA_DISABLE_BIT ; -/* set start trigger */ +/* set start trigger */ if (cmd->start_src ==TRIG_EXT ) { bits |=ADC_START_TRIG_EXT_BITS ;if (cmd->start_arg &CR_INVERT )
@@ -2679,7 +2678,7 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)spin_unlock_irqrestore (&dev->spinlock, flags); -/* start acquisition */ +/* start acquisition */ if (cmd->start_src ==TRIG_NOW )writew (0 , devpriv->main_iobase +ADC_START_REG );
@@ -2697,7 +2696,7 @@ static void pio_drain_ai_fifo_16(struct comedi_device *dev)int num_samples; do { - /* get least significant 15 bits */ + /* get least significant 15 bits */ read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff; write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
@@ -2802,14 +2801,14 @@ static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) pci_addr_reg = devpriv->plx9080_iobase +PLX_REG_DMAPADR (channel); -/* loop until we have read all the full buffers */ +/* loop until we have read all the full buffers */ for (j =0 , next_transfer_addr =readl (pci_addr_reg); (next_transfer_addr < devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] || next_transfer_addr >= devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +DMA_BUFFER_SIZE ) && j <ai_dma_ring_count (board); j++) { -/* transfer data from dma buffer to comedi buffer */ +/* transfer data from dma buffer to comedi buffer */ num_samples =comedi_nsamples_left (s,dma_transfer_size (dev)); comedi_buf_write_samples(s, devpriv->ai_buffer[devpriv->ai_dma_index],
@@ -2835,15 +2834,15 @@ static void handle_ai_interrupt(struct comedi_device *dev,uint8_t dma1_status;unsigned long flags; -/* check for fifo overrun */ +/* check for fifo overrun */ if (status &ADC_OVERRUN_BIT ) {dev_err (dev->class_dev,"fifo overrun\n" ); async->events |=COMEDI_CB_ERROR ; } -/* spin lock makes sure no one else changes plx dma control reg */ +/* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave (&dev->spinlock, flags); dma1_status =readb (devpriv->plx9080_iobase +PLX_REG_DMACSR1 ); -if (plx_status &PLX_INTCSR_DMA1IA ) {/* dma chan 1 interrupt */ +if (plx_status &PLX_INTCSR_DMA1IA ) {/* dma chan 1 interrupt */ writeb ((dma1_status &PLX_DMACSR_ENABLE ) |PLX_DMACSR_CLEARINTR , devpriv->plx9080_iobase +PLX_REG_DMACSR1 );
@@ -2852,7 +2851,7 @@ static void handle_ai_interrupt(struct comedi_device *dev, }spin_unlock_irqrestore (&dev->spinlock, flags); -/* drain fifo with pio */ +/* drain fifo with pio */ if ((status & ADC_DONE_BIT) || ((cmd->flags & CMDF_WAKE_EOS) && (status & ADC_INTR_PENDING_BIT) &&
@@ -2865,7 +2864,7 @@ static void handle_ai_interrupt(struct comedi_device *dev,spin_unlock_irqrestore (&dev->spinlock, flags); } } -/* if we are have all the data, then quit */ +/* if we are have all the data, then quit */ if ((cmd->stop_src ==TRIG_COUNT && async->scans_done >= cmd->stop_arg) || (cmd->stop_src ==TRIG_EXT && (status &ADC_STOP_BIT )))
@@ -3018,7 +3017,7 @@ static void handle_ao_interrupt(struct comedi_device *dev, async = s->async; cmd = &async->cmd; -/* spin lock makes sure no one else changes plx dma control reg */ +/* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave (&dev->spinlock, flags); dma0_status =readb (devpriv->plx9080_iobase +PLX_REG_DMACSR0 );if (plx_status &PLX_INTCSR_DMA0IA ) {/* dma chan 0 interrupt */
@@ -3112,15 +3111,15 @@ static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,int chan =CR_CHAN (insn->chanspec);int range =CR_RANGE (insn->chanspec); -/* do some initializing */ +/* do some initializing */ writew (0 , devpriv->main_iobase +DAC_CONTROL0_REG ); -/* set range */ +/* set range */ set_dac_range_bits (dev, &devpriv->dac_control1_bits, chan, range);writew (devpriv->dac_control1_bits, devpriv->main_iobase +DAC_CONTROL1_REG ); -/* write to channel */ +/* write to channel */ if (board->layout ==LAYOUT_4020 ) {writew (data[0 ] &0xff , devpriv->main_iobase +dac_lsb_4020_reg (chan));
@@ -3130,7 +3129,7 @@ static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,writew (data[0 ], devpriv->main_iobase +dac_convert_reg (chan)); } -/* remember output value */ +/* remember output value */ s->readback[chan] = data[0 ];return 1 ;
@@ -3562,7 +3561,7 @@ static int caldac_i2c_write(struct comedi_device *dev,uint8_t serial_bytes[3 ];uint8_t i2c_addr;enum pointer_bits { -/* manual has gain and offset bits switched */ +/* manual has gain and offset bits switched */ OFFSET_0_2 =0x1 ,GAIN_0_2 =0x2 ,OFFSET_1_3 =0x4 ,
@@ -3573,35 +3572,35 @@ static int caldac_i2c_write(struct comedi_device *dev, };switch (caldac_channel) { -case 0 :/* chan 0 offset */ +case 0 :/* chan 0 offset */ i2c_addr =CALDAC0_I2C_ADDR ; serial_bytes[0 ] =OFFSET_0_2 ;break ; -case 1 :/* chan 1 offset */ +case 1 :/* chan 1 offset */ i2c_addr =CALDAC0_I2C_ADDR ; serial_bytes[0 ] =OFFSET_1_3 ;break ; -case 2 :/* chan 2 offset */ +case 2 :/* chan 2 offset */ i2c_addr =CALDAC1_I2C_ADDR ; serial_bytes[0 ] =OFFSET_0_2 ;break ; -case 3 :/* chan 3 offset */ +case 3 :/* chan 3 offset */ i2c_addr =CALDAC1_I2C_ADDR ; serial_bytes[0 ] =OFFSET_1_3 ;break ; -case 4 :/* chan 0 gain */ +case 4 :/* chan 0 gain */ i2c_addr =CALDAC0_I2C_ADDR ; serial_bytes[0 ] =GAIN_0_2 ;break ; -case 5 :/* chan 1 gain */ +case 5 :/* chan 1 gain */ i2c_addr =CALDAC0_I2C_ADDR ; serial_bytes[0 ] =GAIN_1_3 ;break ; -case 6 :/* chan 2 gain */ +case 6 :/* chan 2 gain */ i2c_addr =CALDAC1_I2C_ADDR ; serial_bytes[0 ] =GAIN_0_2 ;break ; -case 7 :/* chan 3 gain */ +case 7 :/* chan 3 gain */ i2c_addr =CALDAC1_I2C_ADDR ; serial_bytes[0 ] =GAIN_1_3 ;break ;
@@ -3724,24 +3723,24 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)udelay (eeprom_udelay); devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS ; -/* make sure we don't send anything to the i2c bus on 4020 */ +/* make sure we don't send anything to the i2c bus on 4020 */ devpriv->plx_control_bits |=PLX_CNTRL_USERO ;writel (devpriv->plx_control_bits, plx_control_addr); -/* activate serial eeprom */ +/* activate serial eeprom */ udelay (eeprom_udelay); devpriv->plx_control_bits |=PLX_CNTRL_EECS ;writel (devpriv->plx_control_bits, plx_control_addr); -/* write read command and desired memory address */ +/* write read command and desired memory address */ for (bit =1 << (bitstream_length -1 ); bit; bit >>=1 ) { -/* set bit to be written */ +/* set bit to be written */ udelay (eeprom_udelay);if (bitstream & bit) devpriv->plx_control_bits |=PLX_CNTRL_EEWB ;else devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB ;writel (devpriv->plx_control_bits, plx_control_addr); -/* clock in bit */ +/* clock in bit */ udelay (eeprom_udelay); devpriv->plx_control_bits |=PLX_CNTRL_EESK ;writel (devpriv->plx_control_bits, plx_control_addr);
@@ -3749,10 +3748,10 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) devpriv->plx_control_bits &= ~PLX_CNTRL_EESK ;writel (devpriv->plx_control_bits, plx_control_addr); } -/* read back value from eeprom memory location */ +/* read back value from eeprom memory location */ value =0 ;for (bit =1 << (value_length -1 ); bit; bit >>=1 ) { -/* clock out bit */ +/* clock out bit */ udelay (eeprom_udelay); devpriv->plx_control_bits |=PLX_CNTRL_EESK ;writel (devpriv->plx_control_bits, plx_control_addr);
@@ -3764,7 +3763,7 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) value |= bit; } -/* deactivate eeprom serial input */ +/* deactivate eeprom serial input */ udelay (eeprom_udelay); devpriv->plx_control_bits &= ~PLX_CNTRL_EECS ;writel (devpriv->plx_control_bits, plx_control_addr);
@@ -3781,9 +3780,7 @@ static int eeprom_read_insn(struct comedi_device *dev,return 1 ; } -/* -* Allocate and initialize the subdevice structures. -*/ +/* Allocate and initialize the subdevice structures. */ static int setup_subdevices (struct comedi_device *dev) {const struct pcidas64_board *board = dev->board_ptr;
@@ -3822,7 +3819,7 @@ static int setup_subdevices(struct comedi_device *dev)* (not internal calibration sources) */ devpriv->i2c_cal_range_bits =adc_src_4020_bits (4 ); -/* set channels to +-5 volt input ranges */ +/* set channels to +-5 volt input ranges */ for (i =0 ; i < s->n_chan; i++) devpriv->i2c_cal_range_bits |=attenuate_bit (i); data = devpriv->i2c_cal_range_bits;
@@ -3855,7 +3852,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type =COMEDI_SUBD_UNUSED ; } -/* digital input */ +/* digital input */ s = &dev->subdevices[2 ];if (board->layout ==LAYOUT_64XX ) { s->type =COMEDI_SUBD_DI ;
@@ -3868,7 +3865,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type =COMEDI_SUBD_UNUSED ; } -/* digital output */ +/* digital output */ if (board->layout ==LAYOUT_64XX ) { s = &dev->subdevices[3 ]; s->type =COMEDI_SUBD_DO ;
@@ -3897,7 +3894,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type =COMEDI_SUBD_UNUSED ; } -/* 8 channel dio for 60xx */ +/* 8 channel dio for 60xx */ s = &dev->subdevices[5 ];if (board->layout ==LAYOUT_60XX ) { s->type =COMEDI_SUBD_DIO ;
@@ -3911,7 +3908,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type =COMEDI_SUBD_UNUSED ; } -/* caldac */ +/* caldac */ s = &dev->subdevices[6 ]; s->type =COMEDI_SUBD_CALIB ; s->subdev_flags =SDF_READABLE |SDF_WRITABLE |SDF_INTERNAL ;
@@ -3931,7 +3928,7 @@ static int setup_subdevices(struct comedi_device *dev) s->readback[i] = s->maxdata /2 ; } -/* 2 channel ad8402 potentiometer */ +/* 2 channel ad8402 potentiometer */ s = &dev->subdevices[7 ];if (board->layout ==LAYOUT_64XX ) { s->type =COMEDI_SUBD_CALIB ;
@@ -3965,7 +3962,7 @@ static int setup_subdevices(struct comedi_device *dev) s->type =COMEDI_SUBD_UNUSED ; } -/* user counter subd XXX */ +/* user counter subd XXX */ s = &dev->subdevices[9 ]; s->type =COMEDI_SUBD_UNUSED ;
@@ -4011,7 +4008,7 @@ static int auto_attach(struct comedi_device *dev,return -ENOMEM ; } -/* figure out what local addresses are */ +/* figure out what local addresses are */ local_range =readl (devpriv->plx9080_iobase +PLX_REG_LAS0RR ) &PLX_LASRR_MEM_MASK ; local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
Signature · 1 line
2.7.4
PATCH v3 3/8 staging: comedi: jr3_pci.h: Fix checkpatch warning
In reply to Anson JacobFix checkpatch.pl warning:
Block comments use * on subsequent lines Block comments use a trailing */ on a separate line
Block comments starts with /* followed by comments on the next line
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/jr3_pci.h | 290 ++++++++++++++++++------------- 1 file changed, 172 insertions(+), 118 deletions(-)
drivers/staging/comedi/drivers/jr3_pci.h +172 -118
@@ -1,4 +1,5 @@ -/* Helper types to take care of the fact that the DSP card memory +/* +* Helper types to take care of the fact that the DSP card memory * is 16 bits, but aligned on a 32 bit PCI boundary */
@@ -22,7 +23,8 @@ static inline void set_s16(s32 __iomem *p, s16 val)writel (val, p); } -/* The raw data is stored in a format which facilitates rapid +/* +* The raw data is stored in a format which facilitates rapid * processing by the JR3 DSP chip. The raw_channel structure shows the * format for a single channel of data. Each channel takes four, * two-byte words.
@@ -47,7 +49,8 @@ struct raw_channel {s32 reserved[2 ]; }; -/* The force_array structure shows the layout for the decoupled and +/* +* The force_array structure shows the layout for the decoupled and * filtered force data. */ struct force_array {
@@ -61,7 +64,8 @@ struct force_array {s32 v2; }; -/* The six_axis_array structure shows the layout for the offsets and +/* +* The six_axis_array structure shows the layout for the offsets and * the full scales. */ struct six_axis_array {
@@ -74,7 +78,8 @@ struct six_axis_array { };/* VECT_BITS */ -/* The vect_bits structure shows the layout for indicating +/* +* The vect_bits structure shows the layout for indicating * which axes to use in computing the vectors. Each bit signifies * selection of a single axis. The V1x axis bit corresponds to a hex * value of 0x0001 and the V2z bit corresponds to a hex value of
@@ -100,12 +105,14 @@ enum { };/* WARNING_BITS */ -/* The warning_bits structure shows the bit pattern for the warning +/* +* The warning_bits structure shows the bit pattern for the warning * word. The bit fields are shown from bit 0 (lsb) to bit 15 (msb). */ -/* XX_NEAR_SET */ -/* The xx_near_sat bits signify that the indicated axis has reached or +/* XX_NEAR_SET */ +/* +* The xx_near_sat bits signify that the indicated axis has reached or * exceeded the near saturation value. */
@@ -118,12 +125,13 @@ enum { mz_near_sat = 0x0020 }; -/* ERROR_BITS */ -/* XX_SAT */ -/* MEMORY_ERROR */ -/* SENSOR_CHANGE */ +/* ERROR_BITS */ +/* XX_SAT */ +/* MEMORY_ERROR */ +/* SENSOR_CHANGE */ -/* The error_bits structure shows the bit pattern for the error word. +/* +* The error_bits structure shows the bit pattern for the error word. * The bit fields are shown from bit 0 (lsb) to bit 15 (msb). The * xx_sat bits signify that the indicated axis has reached or exceeded * the saturation value. The memory_error bit indicates that a problem
@@ -134,9 +142,10 @@ enum {* */ -/* SYSTEM_BUSY */ +/* SYSTEM_BUSY */ -/* The system_busy bit indicates that the JR3 DSP is currently busy +/* +* The system_busy bit indicates that the JR3 DSP is currently busy * and is not calculating force data. This occurs when a new * coordinate transformation, or new sensor full scale is set by the * user. A very fast system using the force data for feedback might
@@ -146,9 +155,10 @@ enum {* calibration CRC. */ -/* CAL_CRC_BAD */ +/* CAL_CRC_BAD */ -/* The cal_crc_bad bit indicates that the calibration CRC has not +/* +* The cal_crc_bad bit indicates that the calibration CRC has not * calculated to zero. CRC is short for cyclic redundancy code. It is * a method for determining the integrity of messages in data * communication. The calibration data stored inside the sensor is
@@ -168,7 +178,8 @@ enum {/* WATCH_DOG */ /* WATCH_DOG2 */ -/* The watch_dog and watch_dog2 bits are sensor, not processor, watch +/* +* The watch_dog and watch_dog2 bits are sensor, not processor, watch * dog bits. Watch_dog indicates that the sensor data line seems to be * acting correctly, while watch_dog2 indicates that sensor data and * clock are being received. It is possible for watch_dog2 to go off
@@ -192,9 +203,10 @@ enum error_bits_t { watch_dog = 0x8000 }; -/* THRESH_STRUCT */ +/* THRESH_STRUCT */ -/* This structure shows the layout for a single threshold packet inside of a +/* +* This structure shows the layout for a single threshold packet inside of a * load envelope. Each load envelope can contain several threshold structures. * 1. data_address contains the address of the data for that threshold. This * includes filtered, unfiltered, raw, rate, counters, error and warning data
@@ -210,9 +222,10 @@ struct thresh_struct {s32 bit_pattern; }; -/* LE_STRUCT */ +/* LE_STRUCT */ -/* Layout of a load enveloped packet. Four thresholds are showed ... for more +/* +* Layout of a load enveloped packet. Four thresholds are showed ... for more * see manual (pag.25) * 1. latch_bits is a bit pattern that show which bits the user wants to latch. * The latched bits will not be reset once the threshold which set them is
@@ -228,8 +241,9 @@ struct le_struct {s32 reserved; }; -/* LINK_TYPES */ -/* Link types is an enumerated value showing the different possible transform +/* LINK_TYPES */ +/* +* Link types is an enumerated value showing the different possible transform * link types. * 0 - end transform packet * 1 - translate along X axis (TX)
@@ -252,8 +266,8 @@ enum link_types {neg }; -/* TRANSFORM */ -/* Structure used to describe a transform. */ +/* TRANSFORM */ +/* Structure used to describe a transform. */ struct intern_transform { struct { u32 link_type;
@@ -261,23 +275,29 @@ struct intern_transform { } link[8 ]; }; -/* JR3 force/torque sensor data definition. For more information see sensor -* and hardware manuals. +/* +* JR3 force/torque sensor data definition. For more information see sensor +* and hardware manuals. */ struct jr3_channel { -/* Raw_channels is the area used to store the raw data coming from */ -/* the sensor. */ +/* +* Raw_channels is the area used to store the raw data coming from +* the sensor. +*/ struct raw_channel raw_channels[16 ];/* offset 0x0000 */ -/* Copyright is a null terminated ASCII string containing the JR3 */ -/* copyright notice. */ +/* +* Copyright is a null terminated ASCII string containing the JR3 +* copyright notice. +*/ u32 copyright[0x0018 ];/* offset 0x0040 */ s32 reserved1[0x0008 ];/* offset 0x0058 */ -/* Shunts contains the sensor shunt readings. Some JR3 sensors have +/* +* Shunts contains the sensor shunt readings. Some JR3 sensors have * the ability to have their gains adjusted. This allows the * hardware full scales to be adjusted to potentially allow * better resolution or dynamic range. For sensors that have
@@ -298,25 +318,29 @@ struct jr3_channel {* command (10) set new full scales (pg. 38). */ -struct six_axis_array shunts;/* offset 0x0060 */ -s32 reserved2[2 ];/* offset 0x0066 */ +struct six_axis_array shunts;/* offset 0x0060 */ +s32 reserved2[2 ];/* offset 0x0066 */ -/* Default_FS contains the full scale that is used if the user does */ -/* not set a full scale. */ +/* +* Default_FS contains the full scale that is used if the user does +* not set a full scale. +*/ struct six_axis_array default_FS;/* offset 0x0068 */ -s32 reserved3;/* offset 0x006e */ +s32 reserved3;/* offset 0x006e */ -/* Load_envelope_num is the load envelope number that is currently +/* +* Load_envelope_num is the load envelope number that is currently * in use. This value is set by the user after one of the load * envelopes has been initialized. */ -s32 load_envelope_num;/* offset 0x006f */ +s32 load_envelope_num;/* offset 0x006f */ /* Min_full_scale is the recommend minimum full scale. */ -/* These values in conjunction with max_full_scale (pg. 9) helps +/* +* These values in conjunction with max_full_scale (pg. 9) helps * determine the appropriate value for setting the full scales. The * software allows the user to set the sensor full scale to an * arbitrary value. But setting the full scales has some hazards. If
@@ -342,30 +366,35 @@ struct jr3_channel {*/ struct six_axis_array min_full_scale;/* offset 0x0070 */ -s32 reserved4;/* offset 0x0076 */ +s32 reserved4;/* offset 0x0076 */ -/* Transform_num is the transform number that is currently in use. +/* +* Transform_num is the transform number that is currently in use. * This value is set by the JR3 DSP after the user has used command * (5) use transform # (pg. 33). */ -s32 transform_num;/* offset 0x0077 */ +s32 transform_num;/* offset 0x0077 */ -/* Max_full_scale is the recommended maximum full scale. See */ -/* min_full_scale (pg. 9) for more details. */ +/* +* Max_full_scale is the recommended maximum full scale. +* See min_full_scale (pg. 9) for more details. +*/ struct six_axis_array max_full_scale;/* offset 0x0078 */ -s32 reserved5;/* offset 0x007e */ +s32 reserved5;/* offset 0x007e */ -/* Peak_address is the address of the data which will be monitored +/* +* Peak_address is the address of the data which will be monitored * by the peak routine. This value is set by the user. The peak * routine will monitor any 8 contiguous addresses for peak values. * (ex. to watch filter3 data for peaks, set this value to 0x00a8). */ -s32 peak_address;/* offset 0x007f */ +s32 peak_address;/* offset 0x007f */ -/* Full_scale is the sensor full scales which are currently in use. +/* +* Full_scale is the sensor full scales which are currently in use. * Decoupled and filtered data is scaled so that +/- 16384 is equal * to the full scales. The engineering units used are indicated by * the units value discussed on page 16. The full scales for Fx, Fy,
@@ -377,9 +406,10 @@ struct jr3_channel {* axes used for each vector respectively. */ -struct force_array full_scale;/* offset 0x0080 */ +struct force_array full_scale;/* offset 0x0080 */ -/* Offsets contains the sensor offsets. These values are subtracted from +/* +* Offsets contains the sensor offsets. These values are subtracted from * the sensor data to obtain the decoupled data. The offsets are set a * few seconds (< 10) after the calibration data has been received. * They are set so that the output data will be zero. These values
@@ -392,23 +422,26 @@ struct jr3_channel {* about Z by 90 degrees, FY would be 5 and all others would be zero. */ -struct six_axis_array offsets;/* offset 0x0088 */ +struct six_axis_array offsets;/* offset 0x0088 */ -/* Offset_num is the number of the offset currently in use. This +/* +* Offset_num is the number of the offset currently in use. This * value is set by the JR3 DSP after the user has executed the use * offset # command (pg. 34). It can vary between 0 and 15. */ -s32 offset_num;/* offset 0x008e */ +s32 offset_num;/* offset 0x008e */ -/* Vect_axes is a bit map showing which of the axes are being used +/* +* Vect_axes is a bit map showing which of the axes are being used * in the vector calculations. This value is set by the JR3 DSP * after the user has executed the set vector axes command (pg. 37). */ -u32 vect_axes;/* offset 0x008f */ +u32 vect_axes;/* offset 0x008f */ -/* Filter0 is the decoupled, unfiltered data from the JR3 sensor. +/* +* Filter0 is the decoupled, unfiltered data from the JR3 sensor. * This data has had the offsets removed. * * These force_arrays hold the filtered data. The decoupled data is
@@ -420,23 +453,27 @@ struct jr3_channel {* cutoff at 125 Hz, 31.25 Hz, 7.813 Hz, 1.953 Hz and 0.4883 Hz. */ -struct force_array filter[7 ];/* offset 0x0090, -offset 0x0098, -offset 0x00a0, -offset 0x00a8, -offset 0x00b0, -offset 0x00b8 , -offset 0x00c0 */ - -/* Rate_data is the calculated rate data. It is a first derivative +struct force_array filter[7 ];/* +* offset 0x0090, +* offset 0x0098, +* offset 0x00a0, +* offset 0x00a8, +* offset 0x00b0, +* offset 0x00b8, +* offset 0x00c0 +*/ + +/* +* Rate_data is the calculated rate data. It is a first derivative * calculation. It is calculated at a frequency specified by the * variable rate_divisor (pg. 12). The data on which the rate is * calculated is specified by the variable rate_address (pg. 12). */ -struct force_array rate_data;/* offset 0x00c8 */ +struct force_array rate_data;/* offset 0x00c8 */ -/* Minimum_data & maximum_data are the minimum and maximum (peak) +/* +* Minimum_data & maximum_data are the minimum and maximum (peak) * data values. The JR3 DSP can monitor any 8 contiguous data items * for minimums and maximums at full sensor bandwidth. This area is * only updated at user request. This is done so that the user does
@@ -451,7 +488,8 @@ struct jr3_channel {struct force_array minimum_data;/* offset 0x00d0 */ struct force_array maximum_data;/* offset 0x00d8 */ -/* Near_sat_value & sat_value contain the value used to determine if +/* +* Near_sat_value & sat_value contain the value used to determine if * the raw sensor is saturated. Because of decoupling and offset * removal, it is difficult to tell from the processed data if the * sensor is saturated. These values, in conjunction with the error
@@ -465,10 +503,11 @@ struct jr3_channel {* sat_value = 32768 - 2^(16 - ADC bits) */ -s32 near_sat_value;/* offset 0x00e0 */ -s32 sat_value;/* offset 0x00e1 */ +s32 near_sat_value;/* offset 0x00e0 */ +s32 sat_value;/* offset 0x00e1 */ -/* Rate_address, rate_divisor & rate_count contain the data used to +/* +* Rate_address, rate_divisor & rate_count contain the data used to * control the calculations of the rates. Rate_address is the * address of the data used for the rate calculation. The JR3 DSP * will calculate rates for any 8 contiguous values (ex. to
@@ -485,11 +524,12 @@ struct jr3_channel {* will minimize the time necessary to start the rate calculations. */ -s32 rate_address;/* offset 0x00e2 */ -u32 rate_divisor;/* offset 0x00e3 */ -u32 rate_count;/* offset 0x00e4 */ +s32 rate_address;/* offset 0x00e2 */ +u32 rate_divisor;/* offset 0x00e3 */ +u32 rate_count;/* offset 0x00e4 */ -/* Command_word2 through command_word0 are the locations used to +/* +* Command_word2 through command_word0 are the locations used to * send commands to the JR3 DSP. Their usage varies with the command * and is detailed later in the Command Definitions section (pg. * 29). In general the user places values into various memory
@@ -502,11 +542,12 @@ struct jr3_channel {* command_word1). */ -s32 command_word2;/* offset 0x00e5 */ -s32 command_word1;/* offset 0x00e6 */ -s32 command_word0;/* offset 0x00e7 */ +s32 command_word2;/* offset 0x00e5 */ +s32 command_word1;/* offset 0x00e6 */ +s32 command_word0;/* offset 0x00e7 */ -/* Count1 through count6 are unsigned counters which are incremented +/* +* Count1 through count6 are unsigned counters which are incremented * every time the matching filters are calculated. Filter1 is * calculated at the sensor data bandwidth. So this counter would * increment at 8 kHz for a typical sensor. The rest of the counters
@@ -518,14 +559,15 @@ struct jr3_channel {* once. */ -u32 count1;/* offset 0x00e8 */ -u32 count2;/* offset 0x00e9 */ -u32 count3;/* offset 0x00ea */ -u32 count4;/* offset 0x00eb */ -u32 count5;/* offset 0x00ec */ -u32 count6;/* offset 0x00ed */ +u32 count1;/* offset 0x00e8 */ +u32 count2;/* offset 0x00e9 */ +u32 count3;/* offset 0x00ea */ +u32 count4;/* offset 0x00eb */ +u32 count5;/* offset 0x00ec */ +u32 count6;/* offset 0x00ed */ -/* Error_count is a running count of data reception errors. If this +/* +* Error_count is a running count of data reception errors. If this * counter is changing rapidly, it probably indicates a bad sensor * cable connection or other hardware problem. In most installations * error_count should not change at all. But it is possible in an
@@ -535,75 +577,84 @@ struct jr3_channel {* where this counter counts a bad sample, that sample is ignored. */ -u32 error_count;/* offset 0x00ee */ +u32 error_count;/* offset 0x00ee */ -/* Count_x is a counter which is incremented every time the JR3 DSP +/* +* Count_x is a counter which is incremented every time the JR3 DSP * searches its job queues and finds nothing to do. It indicates the * amount of idle time the JR3 DSP has available. It can also be * used to determine if the JR3 DSP is alive. See the Performance * Issues section on pg. 49 for more details. */ -u32 count_x;/* offset 0x00ef */ +u32 count_x;/* offset 0x00ef */ -/* Warnings & errors contain the warning and error bits +/* +* Warnings & errors contain the warning and error bits * respectively. The format of these two words is discussed on page * 21 under the headings warnings_bits and error_bits. */ -u32 warnings;/* offset 0x00f0 */ -u32 errors;/* offset 0x00f1 */ +u32 warnings;/* offset 0x00f0 */ +u32 errors;/* offset 0x00f1 */ -/* Threshold_bits is a word containing the bits that are set by the +/* +* Threshold_bits is a word containing the bits that are set by the * load envelopes. See load_envelopes (pg. 17) and thresh_struct * (pg. 23) for more details. */ -s32 threshold_bits;/* offset 0x00f2 */ +s32 threshold_bits;/* offset 0x00f2 */ -/* Last_crc is the value that shows the actual calculated CRC. CRC +/* +* Last_crc is the value that shows the actual calculated CRC. CRC * is short for cyclic redundancy code. It should be zero. See the * description for cal_crc_bad (pg. 21) for more information. */ -s32 last_CRC;/* offset 0x00f3 */ +s32 last_CRC;/* offset 0x00f3 */ -/* EEProm_ver_no contains the version number of the sensor EEProm. +/* +* EEProm_ver_no contains the version number of the sensor EEProm. * EEProm version numbers can vary between 0 and 255. * Software_ver_no contains the software version number. Version * 3.02 would be stored as 302. */ -s32 eeprom_ver_no;/* offset 0x00f4 */ -s32 software_ver_no;/* offset 0x00f5 */ +s32 eeprom_ver_no;/* offset 0x00f4 */ +s32 software_ver_no;/* offset 0x00f5 */ -/* Software_day & software_year are the release date of the software +/* +* Software_day & software_year are the release date of the software * the JR3 DSP is currently running. Day is the day of the year, * with January 1 being 1, and December 31, being 365 for non leap * years. */ -s32 software_day;/* offset 0x00f6 */ -s32 software_year;/* offset 0x00f7 */ +s32 software_day;/* offset 0x00f6 */ +s32 software_year;/* offset 0x00f7 */ -/* Serial_no & model_no are the two values which uniquely identify a +/* +* Serial_no & model_no are the two values which uniquely identify a * sensor. This model number does not directly correspond to the JR3 * model number, but it will provide a unique identifier for * different sensor configurations. */ -u32 serial_no;/* offset 0x00f8 */ -u32 model_no;/* offset 0x00f9 */ +u32 serial_no;/* offset 0x00f8 */ +u32 model_no;/* offset 0x00f9 */ -/* Cal_day & cal_year are the sensor calibration date. Day is the +/* +* Cal_day & cal_year are the sensor calibration date. Day is the * day of the year, with January 1 being 1, and December 31, being * 366 for leap years. */ -s32 cal_day;/* offset 0x00fa */ -s32 cal_year;/* offset 0x00fb */ +s32 cal_day;/* offset 0x00fa */ +s32 cal_year;/* offset 0x00fb */ -/* Units is an enumerated read only value defining the engineering +/* +* Units is an enumerated read only value defining the engineering * units used in the sensor full scale. The meanings of particular * values are discussed in the section detailing the force_units * structure on page 22. The engineering units are setto customer
@@ -626,20 +677,22 @@ struct jr3_channel {* received. */ -u32 units;/* offset 0x00fc */ -s32 bits;/* offset 0x00fd */ -s32 channels;/* offset 0x00fe */ +u32 units;/* offset 0x00fc */ +s32 bits;/* offset 0x00fd */ +s32 channels;/* offset 0x00fe */ -/* Thickness specifies the overall thickness of the sensor from +/* +* Thickness specifies the overall thickness of the sensor from * flange to flange. The engineering units for this value are * contained in units (pg. 16). The sensor calibration is relative * to the center of the sensor. This value allows easy coordinate * transformation from the center of the sensor to either flange. */ -s32 thickness;/* offset 0x00ff */ +s32 thickness;/* offset 0x00ff */ -/* Load_envelopes is a table containing the load envelope +/* +* Load_envelopes is a table containing the load envelope * descriptions. There are 16 possible load envelope slots in the * table. The slots are on 16 word boundaries and are numbered 0-15. * Each load envelope needs to start at the beginning of a slot but
@@ -655,7 +708,8 @@ struct jr3_channel {struct le_struct load_envelopes[0x10 ];/* offset 0x0100 */ -/* Transforms is a table containing the transform descriptions. +/* +* Transforms is a table containing the transform descriptions. * There are 16 possible transform slots in the table. The slots are * on 16 word boundaries and are numbered 0-15. Each transform needs * to start at the beginning of a slot but need not be fully
Signature · 1 line
2.7.4
PATCH v3 4/8 staging: comedi: ni_atmio.c: Fix checkpatch warning
In reply to Anson JacobFix checkpatch.pl warning for 'Statements should start on a tabstop' Convert single line block comment to single line comment Align single line comment
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/ni_atmio.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-)
drivers/staging/comedi/drivers/ni_atmio.c +4 -7
@@ -89,10 +89,7 @@#include "ni_stc.h" #include "8255.h" -/* -* AT specific setup -*/ - +/* AT specific setup */ static const struct ni_board_struct ni_boards[] = { { .name ="at-mio-16e-1" ,
@@ -206,7 +203,7 @@ static const struct ni_board_struct ni_boards[] = { .n_adchan = 16, .ai_maxdata = 0xffff, .ai_fifo_depth = 512, - .alwaysdither = 1, /* unknown */ + .alwaysdither = 1, /* unknown */ .gainlkup = ai_gain_14, .ai_speed = 10000, .caldac = { dac8800, dac8043, ad8522 },
@@ -278,10 +275,10 @@ static const struct ni_board_struct *ni_atmio_probe(struct comedi_device *dev) }if (device_id ==255 )dev_err (dev->class_dev,"can't find board\n" ); -else if (device_id ==0 ) +else if (device_id ==0 )dev_err (dev->class_dev,"EEPROM read error (?) or device not found\n" ); -else +else dev_err (dev->class_dev,"unknown device ID %d -- contact author\n" , device_id);
Signature · 1 line
2.7.4
PATCH v3 5/8 staging: comedi: s626.h: Fix checkpatch warning
In reply to Anson JacobFix checkpatch.pl warning for
Comparisons should place the constant on the right side of the test Remove extra space after /*
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/s626.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/staging/comedi/drivers/s626.h +2 -2
@@ -79,7 +79,7 @@/* Address offsets, in DWORDS, from base of DMA buffer. */ #define S626_DAC_WDMABUF_OS S626_ADC_DMABUF_DWORDS -/* Interrupt enable bit in ISR and IER. */ +/* Interrupt enable bit in ISR and IER. */ #define S626_IRQ_GPIO3 0x00000040/* IRQ enable for GPIO3. */ #define S626_IRQ_RPS1 0x10000000#define S626_ISR_AFOU 0x00000800
@@ -329,7 +329,7 @@* WS1-WS4 = CS* outputs. */ -#if S626_PLATFORM ==S626_INTEL /* +#if (S626_PLATFORM ==S626_INTEL )/* * Base ACON1 config: always run * A1 based on TSL1. */
Signature · 1 line
2.7.4
PATCH v3 6/8 staging: comedi: jr3_pci.c: Fix checkpatch warning
In reply to Anson JacobFix checkpatch.pl warning 'line over 80 characters' Remove extra space after /*
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/jr3_pci.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)
drivers/staging/comedi/drivers/jr3_pci.c +7 -6
@@ -141,7 +141,7 @@ static void set_transforms(struct jr3_channel __iomem *channel, {int i; - num &=0x000f ;/* Make sure that 0 <= num <= 15 */ + num &=0x000f ;/* Make sure that 0 <= num <= 15 */ for (i =0 ; i <8 ; i++) {set_u16 (&channel->transforms[num].link[i].link_type, transf.link[i].link_type);
@@ -323,10 +323,10 @@ static int read_idm_word(const u8 *data, size_t size, int *pos,int value;if (pos && val) { -/* Skip over non hex */ +/* Skip over non hex */ for (; *pos < size && !isxdigit (data[*pos]); (*pos)++) ; -/* Collect value */ +/* Collect value */ *val =0 ;for (; *pos < size; (*pos)++) { value =hex_to_bin (data[*pos]);
@@ -448,7 +448,8 @@ static int jr3_download_firmware(struct comedi_device *dev,return 0 ; } -static struct jr3_pci_poll_delay jr3_pci_poll_subdevice (struct comedi_subdevice *s) +static struct jr3_pci_poll_delay +jr3_pci_poll_subdevice (struct comedi_subdevice *s) {struct jr3_pci_subdev_private *spriv = s->private;struct jr3_pci_poll_delay result =poll_delay_min_max (1000 ,2000 );
@@ -733,7 +734,7 @@ static int jr3_pci_auto_attach(struct comedi_device *dev, } } -/* Reset DSP card */ +/* Reset DSP card */ writel (0 , &devpriv->iobase->channel[0 ].reset); ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
@@ -763,7 +764,7 @@ static int jr3_pci_auto_attach(struct comedi_device *dev, data.copyright[i]) >> 8); } -/* Start card timer */ +/* Start card timer */ for (i =0 ; i < dev->n_subdevices; i++) { s = &dev->subdevices[i]; spriv = s->private;
Signature · 1 line
2.7.4
PATCH v3 7/8 staging: comedi: ni_at_a2150: Fix checkpatch warning
In reply to Anson JacobFix checkpatch.pl warning 'line over 80 characters' Remove extra space after /*
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/ni_at_a2150.c | 170 ++++++++++++++------------- 1 file changed, 89 insertions(+), 81 deletions(-)
drivers/staging/comedi/drivers/ni_at_a2150.c +89 -81
@@ -58,48 +58,52 @@/* Registers and bits */ #define CONFIG_REG 0x0 -#define CHANNEL_BITS (x) ((x) & 0x7) +#define CHANNEL_BITS (x) ((x) & 0x7)#define CHANNEL_MASK 0x7 -#define CLOCK_SELECT_BITS (x) (((x) & 0x3) << 3) -#define CLOCK_DIVISOR_BITS (x) (((x) & 0x3) << 5) +#define CLOCK_SELECT_BITS (x) (((x) & 0x3) << 3) +#define CLOCK_DIVISOR_BITS (x) (((x) & 0x3) << 5)#define CLOCK_MASK (0xf << 3) -#define ENABLE0_BIT 0x80/* enable (don't internally ground) channels 0 and 1 */ -#define ENABLE1_BIT 0x100/* enable (don't internally ground) channels 2 and 3 */ -#define AC0_BIT 0x200/* ac couple channels 0,1 */ -#define AC1_BIT 0x400/* ac couple channels 2,3 */ -#define APD_BIT 0x800/* analog power down */ -#define DPD_BIT 0x1000/* digital power down */ -#define TRIGGER_REG 0x2/* trigger config register */ -#define POST_TRIGGER_BITS 0x2 -#define DELAY_TRIGGER_BITS 0x3 -#define HW_TRIG_EN 0x10/* enable hardware trigger */ -#define FIFO_START_REG 0x6/* software start aquistion trigger */ -#define FIFO_RESET_REG 0x8/* clears fifo + fifo flags */ -#define FIFO_DATA_REG 0xa/* read data */ -#define DMA_TC_CLEAR_REG 0xe/* clear dma terminal count interrupt */ -#define STATUS_REG 0x12/* read only */ -#define FNE_BIT 0x1/* fifo not empty */ -#define OVFL_BIT 0x8/* fifo overflow */ -#define EDAQ_BIT 0x10/* end of acquisition interrupt */ -#define DCAL_BIT 0x20/* offset calibration in progress */ -#define INTR_BIT 0x40/* interrupt has occurred */ -#define DMA_TC_BIT 0x80/* dma terminal count interrupt has occurred */ -#define ID_BITS (x) (((x) >> 8) & 0x3) -#define IRQ_DMA_CNTRL_REG 0x12/* write only */ -#define DMA_CHAN_BITS (x) ((x) & 0x7)/* sets dma channel */ -#define DMA_EN_BIT 0x8/* enables dma */ -#define IRQ_LVL_BITS (x) (((x) & 0xf) << 4)/* sets irq level */ -#define FIFO_INTR_EN_BIT 0x100/* enable fifo interrupts */ -#define FIFO_INTR_FHF_BIT 0x200/* interrupt fifo half full */ -#define DMA_INTR_EN_BIT 0x800/* enable interrupt on dma terminal count */ -#define DMA_DEM_EN_BIT 0x1000/* enables demand mode dma */ +/* enable (don't internally ground) channels 0 and 1 */ +#define ENABLE0_BIT 0x80 +/* enable (don't internally ground) channels 2 and 3 */ +#define ENABLE1_BIT 0x100 +#define AC0_BIT 0x200/* ac couple channels 0,1 */ +#define AC1_BIT 0x400/* ac couple channels 2,3 */ +#define APD_BIT 0x800/* analog power down */ +#define DPD_BIT 0x1000/* digital power down */ +#define TRIGGER_REG 0x2/* trigger config register */ +#define POST_TRIGGER_BITS 0x2 +#define DELAY_TRIGGER_BITS 0x3 +#define HW_TRIG_EN 0x10/* enable hardware trigger */ +#define FIFO_START_REG 0x6/* software start aquistion trigger */ +#define FIFO_RESET_REG 0x8/* clears fifo + fifo flags */ +#define FIFO_DATA_REG 0xa/* read data */ +#define DMA_TC_CLEAR_REG 0xe/* clear dma terminal count interrupt */ +#define STATUS_REG 0x12/* read only */ +#define FNE_BIT 0x1/* fifo not empty */ +#define OVFL_BIT 0x8/* fifo overflow */ +#define EDAQ_BIT 0x10/* end of acquisition interrupt */ +#define DCAL_BIT 0x20/* offset calibration in progress */ +#define INTR_BIT 0x40/* interrupt has occurred */ +/* dma terminal count interrupt has occurred */ +#define DMA_TC_BIT 0x80 +#define ID_BITS (x) (((x) >> 8) & 0x3) +#define IRQ_DMA_CNTRL_REG 0x12/* write only */ +#define DMA_CHAN_BITS (x) ((x) & 0x7)/* sets dma channel */ +#define DMA_EN_BIT 0x8/* enables dma */ +#define IRQ_LVL_BITS (x) (((x) & 0xf) << 4)/* sets irq level */ +#define FIFO_INTR_EN_BIT 0x100/* enable fifo interrupts */ +#define FIFO_INTR_FHF_BIT 0x200/* interrupt fifo half full */ +/* enable interrupt on dma terminal count */ +#define DMA_INTR_EN_BIT 0x800 +#define DMA_DEM_EN_BIT 0x1000/* enables demand mode dma */ #define I8253_BASE_REG 0x14struct a2150_board {const char *name; -int clock[4 ];/* master clock periods, in nanoseconds */ -int num_clocks;/* number of available master clock speeds */ -int ai_speed;/* maximum conversion rate in nanoseconds */ +int clock[4 ];/* master clock periods, in nanoseconds */ +int num_clocks;/* number of available master clock speeds */ +int ai_speed;/* maximum conversion rate in nanoseconds */ };/* analog input range */
@@ -129,8 +133,8 @@ static const struct a2150_board a2150_boards[] = {struct a2150_private {struct comedi_isadma *dma;unsigned int count;/* number of data points left to be taken */ -int irq_dma_bits;/* irq/dma register bits */ -int config_bits;/* config register bits */ +int irq_dma_bits;/* irq/dma register bits */ +int config_bits;/* config register bits */ };/* interrupt service routine */
@@ -174,13 +178,13 @@ static irqreturn_t a2150_interrupt(int irq, void *d)*/ residue =comedi_isadma_disable (desc->chan); -/* figure out how many points to read */ +/* figure out how many points to read */ max_points =comedi_bytes_to_samples (s, desc->size); num_points = max_points -comedi_bytes_to_samples (s, residue);if (devpriv->count < num_points && cmd->stop_src ==TRIG_COUNT ) num_points = devpriv->count; -/* figure out how many points will be stored next time */ +/* figure out how many points will be stored next time */ leftover =0 ;if (cmd->stop_src ==TRIG_NONE ) { leftover =comedi_bytes_to_samples (s, desc->size);
@@ -189,7 +193,8 @@ static irqreturn_t a2150_interrupt(int irq, void *d)if (leftover > max_points) leftover = max_points; } -/* there should only be a residue if collection was stopped by having +/* +* There should only be a residue if collection was stopped by having * the stop_src set to an external trigger, in which case there * will be no more data */
@@ -199,7 +204,7 @@ static irqreturn_t a2150_interrupt(int irq, void *d)for (i =0 ; i < num_points; i++) {/* write data point to comedi buffer */ dpnt = buf[i]; -/* convert from 2's complement to unsigned coding */ +/* convert from 2's complement to unsigned coding */ dpnt ^=0x8000 ;comedi_buf_write_samples (s, &dpnt,1 );if (cmd->stop_src ==TRIG_COUNT ) {
@@ -229,14 +234,14 @@ static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s)struct comedi_isadma *dma = devpriv->dma;struct comedi_isadma_desc *desc = &dma->desc[0 ]; -/* disable dma on card */ +/* disable dma on card */ devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT ;outw (devpriv->irq_dma_bits, dev->iobase +IRQ_DMA_CNTRL_REG ); -/* disable computer's dma */ +/* disable computer's dma */ comedi_isadma_disable (desc->chan); -/* clear fifo and reset triggering circuitry */ +/* clear fifo and reset triggering circuitry */ outw (0 , dev->iobase +FIFO_RESET_REG );return 0 ;
@@ -255,7 +260,7 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index;int i, j; -/* initialize greatest lower and least upper bounds */ +/* initialize greatest lower and least upper bounds */ lub_divisor_shift =3 ; lub_index =0 ; lub = board->clock[lub_index] * (1 << lub_divisor_shift);
@@ -263,19 +268,19 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period, glb_index = board->num_clocks -1 ; glb = board->clock[glb_index] * (1 << glb_divisor_shift); -/* make sure period is in available range */ +/* make sure period is in available range */ if (*period < glb) *period = glb;if (*period > lub) *period = lub; -/* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ +/* we can multiply period by 1, 2, 4, or 8, using (1 << i) */ for (i =0 ; i <4 ; i++) { -/* there are a maximum of 4 master clocks */ +/* there are a maximum of 4 master clocks */ for (j =0 ; j < board->num_clocks; j++) { -/* temp is the period in nanosec we are evaluating */ +/* temp is the period in nanosec we are evaluating */ temp = board->clock[j] * (1 << i); -/* if it is the best match yet */ +/* if it is the best match yet */ if (temp < lub && temp >= *period) { lub_divisor_shift = i; lub_index = j;
@@ -291,7 +296,7 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,switch (flags &CMDF_ROUND_MASK ) {case CMDF_ROUND_NEAREST :default : -/* if least upper bound is better approximation */ +/* if least upper bound is better approximation */ if (lub - *period < *period - glb) *period = lub;else
@@ -305,7 +310,7 @@ static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,break ; } -/* set clock bits for config register appropriately */ +/* set clock bits for config register appropriately */ devpriv->config_bits &= ~CLOCK_MASK ;if (*period == lub) { devpriv->config_bits |=
@@ -480,7 +485,7 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) "dma incompatible with hard real-time interrupt (CMDF_PRIORITY), aborting\n");return -1 ; } -/* clear fifo and reset triggering circuitry */ +/* clear fifo and reset triggering circuitry */ outw (0 , dev->iobase +FIFO_RESET_REG );/* setup chanlist */
@@ -488,7 +493,7 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) cmd->chanlist_len) < 0)return -1 ; -/* setup ac/dc coupling */ +/* setup ac/dc coupling */ if (CR_AREF (cmd->chanlist[0 ]) ==AREF_OTHER ) devpriv->config_bits |=AC0_BIT ;else
@@ -498,18 +503,18 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)else devpriv->config_bits &= ~AC1_BIT ; -/* setup timing */ +/* setup timing */ a2150_get_timing (dev, &cmd->scan_begin_arg, cmd->flags); -/* send timing, channel, config bits */ +/* send timing, channel, config bits */ outw (devpriv->config_bits, dev->iobase +CONFIG_REG ); -/* initialize number of samples remaining */ +/* initialize number of samples remaining */ devpriv->count = cmd->stop_arg * cmd->chanlist_len;comedi_isadma_disable (desc->chan); -/* set size of transfer to fill in 1/3 second */ +/* set size of transfer to fill in 1/3 second */ #define ONE_THIRD_SECOND 333333333 desc->size =comedi_bytes_per_sample (s) * cmd->chanlist_len *ONE_THIRD_SECOND / cmd->scan_begin_arg;
@@ -527,36 +532,39 @@ static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)*/ outw (0x00 , dev->iobase +DMA_TC_CLEAR_REG ); -/* enable dma on card */ +/* enable dma on card */ devpriv->irq_dma_bits |=DMA_INTR_EN_BIT |DMA_EN_BIT ;outw (devpriv->irq_dma_bits, dev->iobase +IRQ_DMA_CNTRL_REG ); -/* may need to wait 72 sampling periods if timing was changed */ +/* may need to wait 72 sampling periods if timing was changed */ comedi_8254_load (dev->pacer,2 ,72 ,I8254_MODE0 |I8254_BINARY ); -/* setup start triggering */ +/* setup start triggering */ trigger_bits =0 ; -/* decide if we need to wait 72 periods for valid data */ +/* decide if we need to wait 72 periods for valid data */ if (cmd->start_src ==TRIG_NOW && (old_config_bits &CLOCK_MASK ) != (devpriv->config_bits &CLOCK_MASK )) { -/* set trigger source to delay trigger */ +/* set trigger source to delay trigger */ trigger_bits |=DELAY_TRIGGER_BITS ; }else { -/* otherwise no delay */ +/* otherwise no delay */ trigger_bits |=POST_TRIGGER_BITS ; } -/* enable external hardware trigger */ +/* enable external hardware trigger */ if (cmd->start_src ==TRIG_EXT ) { trigger_bits |=HW_TRIG_EN ; }else if (cmd->start_src ==TRIG_OTHER ) { -/* XXX add support for level/slope start trigger using TRIG_OTHER */ +/* +* XXX add support for level/slope start trigger +* using TRIG_OTHER +*/ dev_err (dev->class_dev,"you shouldn't see this?\n" ); } -/* send trigger config bits */ +/* send trigger config bits */ outw (trigger_bits, dev->iobase +TRIGGER_REG ); -/* start acquisition for soft trigger */ +/* start acquisition for soft trigger */ if (cmd->start_src ==TRIG_NOW )outw (0 , dev->iobase +FIFO_START_REG );
@@ -583,28 +591,28 @@ static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,unsigned int n;int ret; -/* clear fifo and reset triggering circuitry */ +/* clear fifo and reset triggering circuitry */ outw (0 , dev->iobase +FIFO_RESET_REG );/* setup chanlist */ if (a2150_set_chanlist (dev,CR_CHAN (insn->chanspec),1 ) <0 )return -1 ; -/* set dc coupling */ +/* set dc coupling */ devpriv->config_bits &= ~AC0_BIT ; devpriv->config_bits &= ~AC1_BIT ; -/* send timing, channel, config bits */ +/* send timing, channel, config bits */ outw (devpriv->config_bits, dev->iobase +CONFIG_REG ); -/* disable dma on card */ +/* disable dma on card */ devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT ;outw (devpriv->irq_dma_bits, dev->iobase +IRQ_DMA_CNTRL_REG ); -/* setup start triggering */ +/* setup start triggering */ outw (0 , dev->iobase +TRIGGER_REG ); -/* start acquisition for soft trigger */ +/* start acquisition for soft trigger */ outw (0 , dev->iobase +FIFO_START_REG );/*
@@ -619,7 +627,7 @@ static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,inw (dev->iobase +FIFO_DATA_REG ); } -/* read data */ +/* read data */ for (n =0 ; n < insn->n; n++) { ret =comedi_timeout (dev, s, insn, a2150_ai_eoc,0 );if (ret)
@@ -629,7 +637,7 @@ static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, data[n] ^=0x8000 ; } -/* clear fifo and reset triggering circuitry */ +/* clear fifo and reset triggering circuitry */ outw (0 , dev->iobase +FIFO_RESET_REG );return n;
@@ -736,16 +744,16 @@ static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->cancel = a2150_cancel; } -/* set card's irq and dma levels */ +/* set card's irq and dma levels */ outw (devpriv->irq_dma_bits, dev->iobase +IRQ_DMA_CNTRL_REG ); -/* reset and sync adc clock circuitry */ +/* reset and sync adc clock circuitry */ outw_p (DPD_BIT |APD_BIT , dev->iobase +CONFIG_REG );outw_p (DPD_BIT , dev->iobase +CONFIG_REG ); -/* initialize configuration register */ +/* initialize configuration register */ devpriv->config_bits =0 ;outw (devpriv->config_bits, dev->iobase +CONFIG_REG ); -/* wait until offset calibration is done, then enable analog inputs */ +/* wait until offset calibration is done, then enable analog inputs */ for (i =0 ; i < timeout; i++) {if ((DCAL_BIT &inw (dev->iobase +STATUS_REG )) ==0 )break ;
Signature · 1 line
2.7.4
PATCH v3 8/8 staging: comedi: cb_pcidas64: Fix checkpath warning
In reply to Anson JacobFix checkpatch.pl warning:
Please use a blank line after function/struct/union/enum declarations
Move macro definition to the top of the file
Aligne macro definitions
Signed-off-by Anson Jacob <[email protected]>
--- drivers/staging/comedi/drivers/cb_pcidas64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/staging/comedi/drivers/cb_pcidas64.c +2 -2
@@ -94,7 +94,8 @@* maybe I'll support this someday */ #define PRESCALED_TIMER_BASE 10000 -#define DMA_BUFFER_SIZE 0x1000 +#define DMA_BUFFER_SIZE 0x1000 +#define DAC_FIFO_SIZE 0x2000/* maximum value that can be loaded into board's 24-bit counters */ static const int max_counter_value =0xffffff ;
@@ -227,7 +228,6 @@ enum hw_config_contents {DAC_FIFO_SIZE_MASK =0xff00 ,/* bits that set dac fifo size */ DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */ }; -#define DAC_FIFO_SIZE 0x2000 enum daq_atrig_low_4020_contents {/* use trig/ext clk bnc input for analog gate signal */
Signature · 1 line
2.7.4