Altera Cyclone Passive Serial SPI FPGA Manager
Subsystems (5)
v2 cover Altera Cyclone Passive Serial SPI FPGA Manager
This series adds an FPGA manager for Altera cyclone FPGAs that can program them using an spi port and a couple of gpios, using Alteras passive serial protocol.
Changes from v1:
- Changed the name from cyclone-spi-fpga-mgr to cyclone-ps-spi-fpga-mgr This name change was requested by Alan Tull, to be specific about which programming method is being employed on the fpga.
- Changed the name of the reset-gpio to config-gpio to closer match the way the pins are described in the Altera manual
- Moved MODULE_LICENCE, _AUTHOR, and _DESCRIPTION to the bottom
- Added a bitrev8x4() function to the bitrev headers and implemented ARM const, runtime, and ARM specific faster versions (This may end up needing to be a standalone patch)
- Moved the bitswapping into cyclonespi_write(), as requested. This falls short of my desired generic lsb first spi support, but is a step in that direction.
- Fixed whitespace problems introduced during refactoring
- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
Joshua Clayton (5):
lib: add bitrev8x4()
doc: dt: add cyclone-spi binding document
fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
ARM: dts: imx6q-evi: support cyclonespi
fpga manager: cyclone-ps-spi: make delay variable
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 23 +++ arch/arm/boot/dts/imx6q-evi.dts | 16 ++ arch/arm/include/asm/bitrev.h | 5 + drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/cyclone-ps-spi.c | 175 +++++++++++++++++++++ include/linux/bitrev.h | 26 +++ 7 files changed, 253 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt create mode 100644 drivers/fpga/cyclone-ps-spi.c
Signature · 1 line
2.7.4
PATCH v2 1/5 lib: add bitrev8x4()
Add a function to reverse bytes within a 32 bit word. This function is more efficient than using the 8 bit version when iterating over an array
--- arch/arm/include/asm/bitrev.h | 5 +++++ include/linux/bitrev.h | 26 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+)
arch/arm/include/asm/bitrev.h +5 -0
@@ -17,4 +17,9 @@ static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x)return __arch_bitrev32 ((u32 )x) >>24 ; } +static __always_inline __attribute_const__ u32 __arch_bitrev8x4(u32 x) +{ + __asm__ ("rbit %0, %1; rev %0, %0" :"=r" (x) :"r" (x)); +} +#endif
include/linux/bitrev.h +26 -0
@@ -9,6 +9,7 @@#define __bitrev32 __arch_bitrev32#define __bitrev16 __arch_bitrev16#define __bitrev8 __arch_bitrev8 +#define __bitrev8x4 __arch_bitrev8x4#else extern u8 const byte_rev_table[256 ];
@@ -27,6 +28,14 @@ static inline u32 __bitrev32(u32 x) return (__bitrev16(x & 0xffff) << 16) | __bitrev16(x >> 16); } +static inline u32 __bitrev8x4 (u32 x) +{ +return (__bitrev8 (x &0xff ) | + (__bitrev8 ((x >>8 ) &0xff ) <<8 ) | + (__bitrev8 ((x >>16 ) &0xff ) <<16 ) | + (__bitrev8 ((x >>24 ) &0xff ) <<24 )); +} +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #define __constant_bitrev32 (x) \
@@ -50,6 +59,15 @@ static inline u32 __bitrev32(u32 x) __x; \ }) +#define __constant_bitrev8x4 (x) \ +({ \ + u32 __x = x; \ + __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4); \ + __x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2); \ + __x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1); \ + __x; \ +}) +#define __constant_bitrev8 (x) \ ({ \ u8 __x = x; \
@@ -75,6 +93,14 @@ static inline u32 __bitrev32(u32 x)__bitrev16 (__x); \ }) +#define bitrev8x4 (x) \ +({ \ + u32 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev8x4(__x) : \ + __bitrev8x4(__x); \ +}) +#define bitrev8 (x) \ ({ \ u8 __x = x; \
Signature · 1 line
2.7.4
kbuild test robot
build botRe: [PATCH v2 1/5] lib: add bitrev8x4()
url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535 config: arm-s5pv210_defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9)…
Hi Joshua,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.9-rc2 next-20161028]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on] [Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535
config: arm-s5pv210_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All warnings (new ones prefixed by >>):
In file included from include/linux/bitrev.h:7:0,
from include/linux/crc32.h:9,
from lib/crc32.c:29:
arch/arm/include/asm/bitrev.h: In function '__arch_bitrev8x4':
>> arch/arm/include/asm/bitrev.h:23:1: warning: no return statement in function returning non-void [-Wreturn-type]
}
^vim +23 arch/arm/include/asm/bitrev.h
7 return x;
8 }
9
10 static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x)
11 {
12 return __arch_bitrev32((u32)x) >> 16;
13 }
14
15 static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x)
16 {
17 return __arch_bitrev32((u32)x) >> 24;
18 }
19
20 static __always_inline __attribute_const__ u32 __arch_bitrev8x4(u32 x)
21 {
22 __asm__ ("rbit %0, %1; rev %0, %0" : "=r" (x) : "r" (x));
> 23 }
24
25 #endif---
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PATCH v2 2/5 doc: dt: add cyclone-spi binding document
In reply to Joshua ClaytonDescribe a cyclonei-ps-spi devicetree entry, required features
--- .../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt new file +23 -0
@@ -0,0 +1,23 @@ +Altera Cyclone Passive Serial SPI FPGA Manager + +Altera Cyclone FPGAs support a method of loading the bitstream over what is +referred to as "passive serial". +The passive serial link is not technically spi, and might require extra +circuits in order to play nicely with other spi slaves on the same bus. + +See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf + +Required properties: +- compatible : should contain "altr,cyclone-ps-spi-fpga-mgr" +- reg : spi slave id of the fpga +- config-gpio : config pin (referred to as nCONFIG in the cyclone manual) +- status-gpio : status pin (referred to as nSTATUS in the cyclone manual) + +Example: + fpga_spi: evi-fpga-spi at 0 { + compatible = "altr,cyclone-ps-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + config-gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status-gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + };
Signature · 1 line
2.7.4
Rob Herring
maintainerRe: [PATCH v2 2/5] doc: dt: add cyclone-spi binding document
Quoted 18 lines · Joshua Clayton
Describe a cyclonei-ps-spi devicetree entry, required features
Signed-off-by Joshua Clayton <[email protected]>--- .../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txtDocumentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt new file +4
-0@@ -0,0 +1,23 @@ +Altera Cyclone Passive Serial SPI FPGA Manager + +Altera Cyclone FPGAs support a method of loading the bitstream over what is +referred to as "passive serial".
Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt line 14
Quoted 10 lines
Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt new file +10
-0+The passive serial link is not technically spi, and might require extra +circuits in order to play nicely with other spi slaves on the same bus. + +See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf + +Required properties: +- compatible : should contain "altr,cyclone-ps-spi-fpga-mgr" +- reg : spi slave id of the fpga +- config-gpio : config pin (referred to as nCONFIG in the cyclone manual) +- status-gpio : status pin (referred to as nSTATUS in the cyclone manual)
'-gpios' is the preferred form.
Looks like active low to me with nXXXX, but the example says active high. Please be specific here.
Quoted 12 lines
Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt new file +9
-0+ +Example: + fpga_spi: evi-fpga-spi at 0 { + compatible = "altr,cyclone-ps-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + config-gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status-gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + };Signature · 1 line
2.7.4
PATCH v2 3/5 fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
In reply to Joshua Claytoncyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first.
--- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/cyclone-ps-spi.c | 172 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 180 insertions(+) create mode 100644 drivers/fpga/cyclone-ps-spi.c
drivers/fpga/Kconfig +7 -0
@@ -13,6 +13,13 @@ config FPGA if FPGA +config FPGA_MGR_CYCLONE_PS_SPI + tristate "Altera Cyclone FPGA Passive Serial over SPI" + depends on SPI + help + FPGA manager driver support for Altera Cyclone using the + passive serial interface over SPI + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA
drivers/fpga/Makefile +1 -0
@@ -6,5 +6,6 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers +obj-$(CONFIG_FPGA_MGR_CYCLONE_PS_SPI) += cyclone-ps-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
drivers/fpga/cyclone-ps-spi.c new file +172 -0
172 lines not on this page · raw message
Signature · 1 line
2.7.4
kbuild test robot
build botRe: [PATCH v2 3/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535 config: i386-allmodconfig (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901…
Hi Joshua,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.9-rc2 next-20161028]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on] [Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 All error/warnings (new ones prefixed by >>):
In file included from include/linux/delay.h:10:0,
from drivers/fpga/cyclone-ps-spi.c:14:
drivers/fpga/cyclone-ps-spi.c: In function 'cyclonespi_write':
>> drivers/fpga/cyclone-ps-spi.c:89:46: error: 'SZ_4K' undeclared (first use in this function)
size_t stride = min(fw_data_end - fw_data, SZ_4K);
^
include/linux/kernel.h:738:2: note: in definition of macro '__min'
t2 min2 = (y); \
^~
>> drivers/fpga/cyclone-ps-spi.c:89:19: note: in expansion of macro 'min'
size_t stride = min(fw_data_end - fw_data, SZ_4K);
^~~
drivers/fpga/cyclone-ps-spi.c:89:46: note: each undeclared identifier is reported only once for each function it appears in
size_t stride = min(fw_data_end - fw_data, SZ_4K);
^
include/linux/kernel.h:738:2: note: in definition of macro '__min'
t2 min2 = (y); \
^~
>> drivers/fpga/cyclone-ps-spi.c:89:19: note: in expansion of macro 'min'
size_t stride = min(fw_data_end - fw_data, SZ_4K);
^~~vim +/SZ_4K +89 drivers/fpga/cyclone-ps-spi.c
8 * Works on Cyclone V. Should work on cyclone series.
9 * May work on other Altera fpgas.
10 *
11 */
12
13 #include <linux/bitrev.h>
> 14 #include <linux/delay.h>
15 #include <linux/fpga/fpga-mgr.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/module.h>
18 #include <linux/of_gpio.h>
19 #include <linux/spi/spi.h>
20
21 #define FPGA_RESET_TIME 50 /* time in usecs to trigger FPGA config */
22 #define FPGA_MIN_DELAY 250 /* min usecs to wait for config status */
23
24 struct cyclonespi_conf {
25 struct gpio_desc *config;
26 struct gpio_desc *status;
27 struct spi_device *spi;
28 };
29
30 static const struct of_device_id of_ef_match[] = {
31 { .compatible = "altr,cyclone-ps-spi-fpga-mgr", },
32 {}
33 };
34 MODULE_DEVICE_TABLE(of, of_ef_match);
35
36 static enum fpga_mgr_states cyclonespi_state(struct fpga_manager *mgr)
37 {
38 return mgr->state;
39 }
40
41 static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags,
42 const char *buf, size_t count)
43 {
44 struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
45
46 if (flags & FPGA_MGR_PARTIAL_RECONFIG) {
47 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
48 return -EINVAL;
49 }
50
51 gpiod_set_value(conf->config, 0);
52 usleep_range(FPGA_RESET_TIME, FPGA_RESET_TIME + 20);
53 if (gpiod_get_value(conf->status) == 1) {
54 dev_err(&mgr->dev, "Status pin should be low.\n");
55 return -EIO;
56 }
57
58 gpiod_set_value(conf->config, 1);
59 usleep_range(FPGA_MIN_DELAY, FPGA_MIN_DELAY + 20);
60 if (gpiod_get_value(conf->status) == 0) {
61 dev_err(&mgr->dev, "Status pin not ready.\n");
62 return -EIO;
63 }
64
65 return 0;
66 }
67
68 static void rev_buf(void *buf, size_t len)
69 {
70 u32 *fw32 = (u32 *)buf;
71 const u32 *fw_end = (u32 *)(buf + len);
72
73 /* set buffer to lsb first */
74 while (fw32 < fw_end) {
75 *fw32 = bitrev8x4(*fw32);
76 fw32++;
77 }
78 }
79
80 static int cyclonespi_write(struct fpga_manager *mgr, const char *buf,
81 size_t count)
82 {
83 struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
84 const char *fw_data = buf;
85 const char *fw_data_end = fw_data + count;
86
87 while (fw_data < fw_data_end) {
88 int ret;
> 89 size_t stride = min(fw_data_end - fw_data, SZ_4K);
90
91 rev_buf((void *)fw_data, stride);
92 ret = spi_write(conf->spi, fw_data, stride);---
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kbuild test robot
build botRe: [PATCH v2 3/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
In reply to Joshua Claytonurl: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535 config: arm64-allmodconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1…
Hi Joshua,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.9-rc2 next-20161028]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on] [Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All error/warnings (new ones prefixed by >>):
In file included from drivers/fpga/cyclone-ps-spi.c:13:0:
drivers/fpga/cyclone-ps-spi.c: In function 'rev_buf':
>> include/linux/bitrev.h:12:21: error: implicit declaration of function '__arch_bitrev8x4' [-Werror=implicit-function-declaration]
#define __bitrev8x4 __arch_bitrev8x4
^
>> include/linux/bitrev.h:101:2: note: in expansion of macro '__bitrev8x4'
__bitrev8x4(__x); \
^~~~~~~~~~~
>> drivers/fpga/cyclone-ps-spi.c:75:11: note: in expansion of macro 'bitrev8x4'
*fw32 = bitrev8x4(*fw32);
^~~~~~~~~
In file included from include/linux/delay.h:10:0,
from drivers/fpga/cyclone-ps-spi.c:14:
drivers/fpga/cyclone-ps-spi.c: In function 'cyclonespi_write':
include/linux/kernel.h:739:16: warning: comparison of distinct pointer types lacks a cast
(void) (&min1 == &min2); \
^
include/linux/kernel.h:742:2: note: in expansion of macro '__min'
__min(typeof(x), typeof(y), \
^~~~~
drivers/fpga/cyclone-ps-spi.c:89:19: note: in expansion of macro 'min'
size_t stride = min(fw_data_end - fw_data, SZ_4K);
^~~cc1: some warnings being treated as errors
vim +/__arch_bitrev8x4 +12 include/linux/bitrev.h
556d2f05 Yalin Wang 2014-11-03 6 #ifdef CONFIG_HAVE_ARCH_BITREVERSE
556d2f05 Yalin Wang 2014-11-03 7 #include <asm/bitrev.h>
556d2f05 Yalin Wang 2014-11-03 8
556d2f05 Yalin Wang 2014-11-03 9 #define __bitrev32 __arch_bitrev32
556d2f05 Yalin Wang 2014-11-03 10 #define __bitrev16 __arch_bitrev16
556d2f05 Yalin Wang 2014-11-03 11 #define __bitrev8 __arch_bitrev8
69ff2a81 Joshua Clayton 2016-10-28 @12 #define __bitrev8x4 __arch_bitrev8x4
a5cfc1ec Akinobu Mita 2006-12-08 13
556d2f05 Yalin Wang 2014-11-03 14 #else
556d2f05 Yalin Wang 2014-11-03 15 extern u8 const byte_rev_table[256];
556d2f05 Yalin Wang 2014-11-03 16 static inline u8 __bitrev8(u8 byte)
a5cfc1ec Akinobu Mita 2006-12-08 17 {
a5cfc1ec Akinobu Mita 2006-12-08 18 return byte_rev_table[byte];
a5cfc1ec Akinobu Mita 2006-12-08 19 }
a5cfc1ec Akinobu Mita 2006-12-08 20
556d2f05 Yalin Wang 2014-11-03 21 static inline u16 __bitrev16(u16 x)
556d2f05 Yalin Wang 2014-11-03 22 {
556d2f05 Yalin Wang 2014-11-03 23 return (__bitrev8(x & 0xff) << 8) | __bitrev8(x >> 8);
556d2f05 Yalin Wang 2014-11-03 24 }
556d2f05 Yalin Wang 2014-11-03 25
556d2f05 Yalin Wang 2014-11-03 26 static inline u32 __bitrev32(u32 x)
556d2f05 Yalin Wang 2014-11-03 27 {
556d2f05 Yalin Wang 2014-11-03 28 return (__bitrev16(x & 0xffff) << 16) | __bitrev16(x >> 16);
556d2f05 Yalin Wang 2014-11-03 29 }
556d2f05 Yalin Wang 2014-11-03 30
69ff2a81 Joshua Clayton 2016-10-28 31 static inline u32 __bitrev8x4(u32 x)
69ff2a81 Joshua Clayton 2016-10-28 32 {
69ff2a81 Joshua Clayton 2016-10-28 33 return(__bitrev8(x & 0xff) |
69ff2a81 Joshua Clayton 2016-10-28 34 (__bitrev8((x >> 8) & 0xff) << 8) |
69ff2a81 Joshua Clayton 2016-10-28 35 (__bitrev8((x >> 16) & 0xff) << 16) |
69ff2a81 Joshua Clayton 2016-10-28 36 (__bitrev8((x >> 24) & 0xff) << 24));
69ff2a81 Joshua Clayton 2016-10-28 37 }
69ff2a81 Joshua Clayton 2016-10-28 38
556d2f05 Yalin Wang 2014-11-03 39 #endif /* CONFIG_HAVE_ARCH_BITREVERSE */
556d2f05 Yalin Wang 2014-11-03 40
556d2f05 Yalin Wang 2014-11-03 41 #define __constant_bitrev32(x) \
556d2f05 Yalin Wang 2014-11-03 42 ({ \
556d2f05 Yalin Wang 2014-11-03 43 u32 __x = x; \
556d2f05 Yalin Wang 2014-11-03 44 __x = (__x >> 16) | (__x << 16); \
556d2f05 Yalin Wang 2014-11-03 45 __x = ((__x & (u32)0xFF00FF00UL) >> 8) | ((__x & (u32)0x00FF00FFUL) << 8); \
556d2f05 Yalin Wang 2014-11-03 46 __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4); \
556d2f05 Yalin Wang 2014-11-03 47 __x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2); \
556d2f05 Yalin Wang 2014-11-03 48 __x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1); \
556d2f05 Yalin Wang 2014-11-03 49 __x; \
556d2f05 Yalin Wang 2014-11-03 50 })
556d2f05 Yalin Wang 2014-11-03 51
556d2f05 Yalin Wang 2014-11-03 52 #define __constant_bitrev16(x) \
556d2f05 Yalin Wang 2014-11-03 53 ({ \
556d2f05 Yalin Wang 2014-11-03 54 u16 __x = x; \
556d2f05 Yalin Wang 2014-11-03 55 __x = (__x >> 8) | (__x << 8); \
556d2f05 Yalin Wang 2014-11-03 56 __x = ((__x & (u16)0xF0F0U) >> 4) | ((__x & (u16)0x0F0FU) << 4); \
556d2f05 Yalin Wang 2014-11-03 57 __x = ((__x & (u16)0xCCCCU) >> 2) | ((__x & (u16)0x3333U) << 2); \
556d2f05 Yalin Wang 2014-11-03 58 __x = ((__x & (u16)0xAAAAU) >> 1) | ((__x & (u16)0x5555U) << 1); \
556d2f05 Yalin Wang 2014-11-03 59 __x; \
556d2f05 Yalin Wang 2014-11-03 60 })
556d2f05 Yalin Wang 2014-11-03 61
69ff2a81 Joshua Clayton 2016-10-28 62 #define __constant_bitrev8x4(x) \
69ff2a81 Joshua Clayton 2016-10-28 63 ({ \
69ff2a81 Joshua Clayton 2016-10-28 64 u32 __x = x; \
69ff2a81 Joshua Clayton 2016-10-28 65 __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4); \
69ff2a81 Joshua Clayton 2016-10-28 66 __x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2); \
69ff2a81 Joshua Clayton 2016-10-28 67 __x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1); \
69ff2a81 Joshua Clayton 2016-10-28 68 __x; \
69ff2a81 Joshua Clayton 2016-10-28 69 })
69ff2a81 Joshua Clayton 2016-10-28 70
556d2f05 Yalin Wang 2014-11-03 71 #define __constant_bitrev8(x) \
556d2f05 Yalin Wang 2014-11-03 72 ({ \
556d2f05 Yalin Wang 2014-11-03 73 u8 __x = x; \
556d2f05 Yalin Wang 2014-11-03 74 __x = (__x >> 4) | (__x << 4); \
556d2f05 Yalin Wang 2014-11-03 75 __x = ((__x & (u8)0xCCU) >> 2) | ((__x & (u8)0x33U) << 2); \
556d2f05 Yalin Wang 2014-11-03 76 __x = ((__x & (u8)0xAAU) >> 1) | ((__x & (u8)0x55U) << 1); \
556d2f05 Yalin Wang 2014-11-03 77 __x; \
556d2f05 Yalin Wang 2014-11-03 78 })
556d2f05 Yalin Wang 2014-11-03 79
556d2f05 Yalin Wang 2014-11-03 80 #define bitrev32(x) \
556d2f05 Yalin Wang 2014-11-03 81 ({ \
556d2f05 Yalin Wang 2014-11-03 82 u32 __x = x; \
556d2f05 Yalin Wang 2014-11-03 83 __builtin_constant_p(__x) ? \
556d2f05 Yalin Wang 2014-11-03 84 __constant_bitrev32(__x) : \
556d2f05 Yalin Wang 2014-11-03 85 __bitrev32(__x); \
556d2f05 Yalin Wang 2014-11-03 86 })
556d2f05 Yalin Wang 2014-11-03 87
556d2f05 Yalin Wang 2014-11-03 88 #define bitrev16(x) \
556d2f05 Yalin Wang 2014-11-03 89 ({ \
556d2f05 Yalin Wang 2014-11-03 90 u16 __x = x; \
556d2f05 Yalin Wang 2014-11-03 91 __builtin_constant_p(__x) ? \
556d2f05 Yalin Wang 2014-11-03 92 __constant_bitrev16(__x) : \
556d2f05 Yalin Wang 2014-11-03 93 __bitrev16(__x); \
556d2f05 Yalin Wang 2014-11-03 94 })
a5cfc1ec Akinobu Mita 2006-12-08 95
69ff2a81 Joshua Clayton 2016-10-28 96 #define bitrev8x4(x) \
69ff2a81 Joshua Clayton 2016-10-28 97 ({ \
69ff2a81 Joshua Clayton 2016-10-28 98 u32 __x = x; \
69ff2a81 Joshua Clayton 2016-10-28 99 __builtin_constant_p(__x) ? \
69ff2a81 Joshua Clayton 2016-10-28 100 __constant_bitrev8x4(__x) : \
69ff2a81 Joshua Clayton 2016-10-28 @101 __bitrev8x4(__x); \
69ff2a81 Joshua Clayton 2016-10-28 102 })69ff2a81 Joshua Clayton 2016-10-28 103556d2f05 Yalin Wang 2014-11-03 104 #define bitrev8(x) \
:::::: The code at line 12 was first introduced by commit :::::: 69ff2a81709e0969b2d1a0efaa9a010e0093917c lib: add bitrev8x4()
:::::: TO: Joshua Clayton <[email protected]> :::::: CC: 0day robot <[email protected]>
---
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kbuild test robot
build botRe: [PATCH v2 3/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
In reply to Joshua Claytonurl: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535 config: openrisc-allmodconfig (attached as .config) compiler: or32-linux-gcc (GCC) 4.5.1-or32-1.0rc1…
Hi Joshua,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.9-rc2 next-20161028]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on] [Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535
config: openrisc-allmodconfig (attached as .config)
compiler: or32-linux-gcc (GCC) 4.5.1-or32-1.0rc1
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=openrisc
All errors (new ones prefixed by >>):
drivers/fpga/cyclone-ps-spi.c: In function 'cyclonespi_write':
drivers/fpga/cyclone-ps-spi.c:89:19: error: 'SZ_4K' undeclared (first use in this function) drivers/fpga/cyclone-ps-spi.c:89:19: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/fpga/cyclone-ps-spi.c:89:19: error: type defaults to 'int' in declaration of '__UNIQUE_ID_min2_15'
vim +89 drivers/fpga/cyclone-ps-spi.c
83 struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv;
84 const char *fw_data = buf;
85 const char *fw_data_end = fw_data + count;
86
87 while (fw_data < fw_data_end) {
88 int ret;
> 89 size_t stride = min(fw_data_end - fw_data, SZ_4K);
90
91 rev_buf((void *)fw_data, stride);
92 ret = spi_write(conf->spi, fw_data, stride);---
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Re: [PATCH v2 3/5] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
Dang it!
This was flagged last time around and I forgot to fix it.
Quoted 31 lines · kbuild test robot
Hi Joshua,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.9-rc2 next-20161028]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on] [Check https://git-scm.com/docs/git-format-patch for more information]url: https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535
config: openrisc-allmodconfig (attached as .config)
compiler: or32-linux-gcc (GCC) 4.5.1-or32-1.0rc1
reproduce:Dang it!
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=openriscAll errors (new ones prefixed by >>):
drivers/fpga/cyclone-ps-spi.c: In function 'cyclonespi_write':
drivers/fpga/cyclone-ps-spi.c:89:19: error: 'SZ_4K' undeclared (first use in this function)drivers/fpga/cyclone-ps-spi.c:89:19: note: each undeclared identifier is reported only once for each function it appears inQuoted 1 line
Quoted 1 line
drivers/fpga/cyclone-ps-spi.c:89:19: error: type defaults to 'int' in declaration of '__UNIQUE_ID_min2_15'vim +89
drivers/fpga/cyclone-ps-spi.c83 struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; 84 const char *fw_data = buf; 85 const char *fw_data_end = fw_data + count; 86 87 while (fw_data < fw_data_end) { 88 int ret;
Quoted 8 lines
Quoted 1 line
89
size_tstride =min(fw_data_end - fw_data, SZ_4K);90 91 rev_buf((void *)fw_data, stride); 92 ret = spi_write(conf->spi, fw_data, stride);---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Thanks, kbuild test robot.
Will fix this time.
PATCH v2 4/5 ARM: dts: imx6q-evi: support cyclonespi
In reply to Joshua ClaytonAdd support for Altera cyclone V FPGA connected to an spi port
--- arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm/boot/dts/imx6q-evi.dts +16 -0
@@ -95,6 +95,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; status = "okay"; + + fpga_spi: cyclonespi at 0 { + compatible = "altr,cyclone-ps-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + pinctrl-0 = <&pinctrl_fpgaspi>; + config-gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status-gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + }; }; &ecspi3 {
@@ -325,6 +334,13 @@ >; }; + pinctrl_fpgaspi: fpgaspigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + pinctrl_gpminand: gpminandgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
Signature · 1 line
2.7.4
PATCH v2 5/5 fpga manager: cyclone-ps-spi: make delay variable
In reply to Joshua ClaytonThe status pin may not show ready in the time described in the Altetera manual. check the value several times before giving up For the hardware I am working on, the status pin takes 250 us, 5 times as long as described by Altera.
--- drivers/fpga/cyclone-ps-spi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)
drivers/fpga/cyclone-ps-spi.c +9 -6
@@ -20,6 +20,7 @@#define FPGA_RESET_TIME 50/* time in usecs to trigger FPGA config */ -#define FPGA_MIN_DELAY 250/* min usecs to wait for config status */ +#define FPGA_MIN_DELAY 50/* min usecs to wait for config status */ +#define FPGA_MAX_DELAY 1000/* max usecs to wait for config status */ struct cyclonespi_conf {struct gpio_desc *config;
@@ -42,6 +43,7 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, const char *buf, size_t count) {struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; +int i;if (flags &FPGA_MGR_PARTIAL_RECONFIG ) {dev_err (&mgr->dev,"Partial reconfiguration not supported.\n" );
@@ -56,13 +58,14 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, }gpiod_set_value (conf->config,1 ); -usleep_range (FPGA_MIN_DELAY ,FPGA_MIN_DELAY +20 ); -if (gpiod_get_value (conf->status) ==0 ) { -dev_err (&mgr->dev,"Status pin not ready.\n" ); -return -EIO ; +for (i =0 ; i < (FPGA_MAX_DELAY /FPGA_MIN_DELAY ); i++) { +usleep_range (FPGA_MIN_DELAY ,FPGA_MIN_DELAY +20 ); +if (gpiod_get_value (conf->status)) +return 0 ; } -return 0 ; +dev_err (&mgr->dev,"Status pin not ready.\n" ); +return -EIO ; }static void rev_buf (void *buf,size_t len)
Signature · 1 line
2.7.4
Re: [PATCH v2 5/5] fpga manager: cyclone-ps-spi: make delay variable
Hi Joshua,
looks good to me; however, I think since you're adding initial support, I'd squash this together with [3/5].
Quoted 2 lines · Joshua Clayton
The status pin may not show ready in the time described in the Altetera manual. check the value several times before giving up
s/Altetera/Altera
Quoted 52 lines
For the hardware I am working on, the status pin takes 250 us, 5 times as long as described by Altera.
Signed-off-by Joshua Clayton <[email protected]>--- drivers/fpga/cyclone-ps-spi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)drivers/fpga/cyclone-ps-spi.c +9
-6@@ -20,6 +20,7 @@#define FPGA_RESET_TIME 50/* time in usecs to trigger FPGA config */ -#define FPGA_MIN_DELAY 250/* min usecs to wait for config status */ +#define FPGA_MIN_DELAY 50/* min usecs to wait for config status */ +#define FPGA_MAX_DELAY 1000/* max usecs to wait for config status */ struct cyclonespi_conf {struct gpio_desc *config;@@ -42,6 +43,7 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, const char *buf, size_t count) {struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; +int i;if (flags &FPGA_MGR_PARTIAL_RECONFIG ) {dev_err (&mgr->dev,"Partial reconfiguration not supported.\n" );@@ -56,13 +58,14 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, }gpiod_set_value (conf->config,1 ); -usleep_range (FPGA_MIN_DELAY ,FPGA_MIN_DELAY +20 ); -if (gpiod_get_value (conf->status) ==0 ) { -dev_err (&mgr->dev,"Status pin not ready.\n" ); -return -EIO ; +for (i =0 ; i < (FPGA_MAX_DELAY /FPGA_MIN_DELAY ); i++) { +usleep_range (FPGA_MIN_DELAY ,FPGA_MIN_DELAY +20 ); +if (gpiod_get_value (conf->status)) +return 0 ; } -return 0 ; +dev_err (&mgr->dev,"Status pin not ready.\n" ); +return -EIO ; }static void rev_buf (void *buf,size_t len)Signature · 1 line
2.7.4
Cheers,
Moritz
Re: [PATCH v2 5/5] fpga manager: cyclone-ps-spi: make delay variable
Hi Moritz,
Thanks for the review.
Quoted 4 lines · Moritz Fischer
Hi Joshua,
looks good to me; however, I think since you're adding initial support, I'd squash this together with [3/5].
I agree. I didn't want to squash it in before putting it up for review, though.
Quoted 5 lines · Joshua Clayton
Quoted 2 lines
The status pin may not show ready in the time described in the Altetera manual. check the value several times before giving up
s/Altetera/Altera
Thanks. I'll fix this. And it will go away when it gets squashed.
Quoted 48 lines
Quoted 48 lines
For the hardware I am working on, the status pin takes 250 us, 5 times as long as described by Altera.
Signed-off-by Joshua Clayton <[email protected]>--- drivers/fpga/cyclone-ps-spi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)drivers/fpga/cyclone-ps-spi.c +9
-6@@ -20,6 +20,7 @@#define FPGA_RESET_TIME 50/* time in usecs to trigger FPGA config */ -#define FPGA_MIN_DELAY 250/* min usecs to wait for config status */ +#define FPGA_MIN_DELAY 50/* min usecs to wait for config status */ +#define FPGA_MAX_DELAY 1000/* max usecs to wait for config status */ struct cyclonespi_conf {struct gpio_desc *config;@@ -42,6 +43,7 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, const char *buf, size_t count) {struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; +int i;if (flags &FPGA_MGR_PARTIAL_RECONFIG ) {dev_err (&mgr->dev,"Partial reconfiguration not supported.\n" );@@ -56,13 +58,14 @@ static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags, }gpiod_set_value (conf->config,1 ); -usleep_range (FPGA_MIN_DELAY ,FPGA_MIN_DELAY +20 ); -if (gpiod_get_value (conf->status) ==0 ) { -dev_err (&mgr->dev,"Status pin not ready.\n" ); -return -EIO ; +for (i =0 ; i < (FPGA_MAX_DELAY /FPGA_MIN_DELAY ); i++) { +usleep_range (FPGA_MIN_DELAY ,FPGA_MIN_DELAY +20 ); +if (gpiod_get_value (conf->status)) +return 0 ; } -return 0 ; +dev_err (&mgr->dev,"Status pin not ready.\n" ); +return -EIO ; }
Quoted 7 lines
Quoted 4 lines
drivers/fpga/cyclone-ps-spi.c +0
-0static void rev_buf (void *buf,size_t len)Signature · 1 line
2.7.4Cheers,
Moritz
Joshua