PCI bus support
Subsystems (2)
v11 cover PCI bus support
This is 11th version of PCI support.
Changes since v9:
- all PCI configuration space accessors added;
- data size in PCI configuration space accessors fixed;
- PCI bus parity checking enabled;
- coding style errors fixed;
Sources are avalable at:
https://github.com/a-gordeev/kvm-unit-tests.git pci-testdev-v11
Cc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Alexander Gordeev (12):
pci: Fix coding style in generic PCI files
pci: x86: Rename pci_config_read() to pci_config_readl()
pci: Add 'extern' to public function declarations
pci: x86: Add remaining PCI configuration space accessors
pci: Factor out pci_bar_get()
pci: Rework pci_bar_addr()
pci: Add pci_bar_set_addr()
pci: Add pci_dev_exists()
pci: Add pci_print()
pci: Add generic ECAM host support
pci: Add pci-testdev PCI bus test device arm/arm64: pci: Add pci-testdev PCI device operation test
arm/Makefile.common | 6 +- arm/pci-test.c | 27 ++++ arm/run | 7 +- arm/unittests.cfg | 4 + lib/arm/asm/pci.h | 1 + lib/arm64/asm/pci.h | 1 + lib/asm-generic/pci-host-bridge.h | 28 ++++ lib/pci-host-generic.c | 318 ++++++++++++++++++++++++++++++++++++++ lib/pci-host-generic.h | 46 ++++++ lib/pci-testdev.c | 192 +++++++++++++++++++++++ lib/pci.c | 212 ++++++++++++++++++++++--- lib/pci.h | 43 +++++- lib/x86/asm/pci.h | 46 +++++- x86/vmexit.c | 4 +- 14 files changed, 904 insertions(+), 31 deletions(-) create mode 100644 arm/pci-test.c create mode 100644 lib/arm/asm/pci.h create mode 100644 lib/arm64/asm/pci.h create mode 100644 lib/asm-generic/pci-host-bridge.h create mode 100644 lib/pci-host-generic.c create mode 100644 lib/pci-host-generic.h create mode 100644 lib/pci-testdev.c
Signature · 1 line
1.8.3.1
PATCH v11 1/12 pci: Fix coding style in generic PCI files
Cc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Thomas Huth <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 38 ++++++++++++++++++++------------------ lib/pci.h | 3 ++- 2 files changed, 22 insertions(+), 19 deletions(-)
lib/pci.c +20 -18
@@ -10,34 +10,36 @@/* Scan bus look for a specific device. Only bus 0 scanned for now. */ pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id) { -unsigned dev; -for (dev =0 ; dev <256 ; ++dev) { -uint32_t id =pci_config_read (dev,0 ); -if ((id &0xFFFF ) == vendor_id && (id >>16 ) == device_id) { -return dev; - } - } -return PCIDEVADDR_INVALID ; +pcidevaddr_t dev; + +for (dev =0 ; dev <256 ; ++dev) { +uint32_t id =pci_config_read (dev,0 ); + +if ((id &0xFFFF ) == vendor_id && (id >>16 ) == device_id) +return dev; + } + +return PCIDEVADDR_INVALID ; }unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num) { -uint32_t bar =pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); -if (bar &PCI_BASE_ADDRESS_SPACE_IO ) { -return bar &PCI_BASE_ADDRESS_IO_MASK ; - }else { -return bar &PCI_BASE_ADDRESS_MEM_MASK ; - } +uint32_t bar =pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); + +if (bar &PCI_BASE_ADDRESS_SPACE_IO ) +return bar &PCI_BASE_ADDRESS_IO_MASK ; +else +return bar &PCI_BASE_ADDRESS_MEM_MASK ; }bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num) { -uint32_t bar =pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); -return !(bar &PCI_BASE_ADDRESS_SPACE_IO ); +uint32_t bar =pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); + +return !(bar &PCI_BASE_ADDRESS_SPACE_IO ); }bool pci_bar_is_valid (pcidevaddr_t dev,int bar_num) { -uint32_t bar =pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); -return bar; +return pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); }
lib/pci.h +2 -1
@@ -12,8 +12,9 @@typedef uint16_t pcidevaddr_t ;enum { -PCIDEVADDR_INVALID =0xffff , +PCIDEVADDR_INVALID =0xffff , }; +pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id);unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num);bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num);
Signature · 1 line
1.8.3.1
PATCH v11 2/12 pci: x86: Rename pci_config_read() to pci_config_readl()
In reply to Alexander GordeevCc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Thomas Huth <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 8 ++++---- lib/x86/asm/pci.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-)
lib/pci.c +4 -4
@@ -13,7 +13,7 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)pcidevaddr_t dev;for (dev =0 ; dev <256 ; ++dev) { -uint32_t id =pci_config_read (dev,0 ); +uint32_t id =pci_config_readl (dev,0 );if ((id &0xFFFF ) == vendor_id && (id >>16 ) == device_id)return dev;
@@ -24,7 +24,7 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num) { -uint32_t bar =pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); +uint32_t bar =pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 );if (bar &PCI_BASE_ADDRESS_SPACE_IO )return bar &PCI_BASE_ADDRESS_IO_MASK ;
@@ -34,12 +34,12 @@ unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num) { -uint32_t bar =pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); +uint32_t bar =pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 );return !(bar &PCI_BASE_ADDRESS_SPACE_IO ); }bool pci_bar_is_valid (pcidevaddr_t dev,int bar_num) { -return pci_config_read (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); +return pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); }
lib/x86/asm/pci.h +1 -1
@@ -9,7 +9,7 @@#include "pci.h" #include "x86/asm/io.h" -static inline uint32_t pci_config_read (pcidevaddr_t dev,uint8_t reg) +static inline uint32_t pci_config_readl (pcidevaddr_t dev,uint8_t reg) {uint32_t index = reg | (dev <<8 ) | (0x1 <<31 );outl (index,0xCF8 );
Signature · 1 line
1.8.3.1
PATCH v11 3/12 pci: Add 'extern' to public function declarations
In reply to Alexander GordeevCc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
lib/pci.h +4 -4
@@ -15,10 +15,10 @@ enum { PCIDEVADDR_INVALID = 0xffff, }; -pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id); -unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num); -bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num); -bool pci_bar_is_valid (pcidevaddr_t dev,int bar_num); +extern pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id); +extern unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num); +extern bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num); +extern bool pci_bar_is_valid (pcidevaddr_t dev,int bar_num);/* * pci-testdev is a driver for the pci-testdev qemu pci device. The
Signature · 1 line
1.8.3.1
PATCH v11 4/12 pci: x86: Add remaining PCI configuration space accessors
In reply to Alexander GordeevCc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Thomas Huth <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 5 ++--- lib/x86/asm/pci.h | 38 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 5 deletions(-)
lib/pci.c +2 -3
@@ -13,9 +13,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)pcidevaddr_t dev;for (dev =0 ; dev <256 ; ++dev) { -uint32_t id =pci_config_readl (dev,0 ); - -if ((id &0xFFFF ) == vendor_id && (id >>16 ) == device_id) +if (pci_config_readw (dev,PCI_VENDOR_ID ) == vendor_id && +pci_config_readw (dev,PCI_DEVICE_ID ) == device_id)return dev; }
lib/x86/asm/pci.h +36 -2
@@ -9,11 +9,45 @@#include "pci.h" #include "x86/asm/io.h" +#define PCI_CONF1_ADDRESS (dev, reg) ((0x1 << 31) | (dev << 8) | reg) + +static inline uint8_t pci_config_readb (pcidevaddr_t dev,uint8_t reg) +{ +outl (PCI_CONF1_ADDRESS (dev, reg),0xCF8 ); +return inb (0xCFC ); +} + +static inline uint16_t pci_config_readw (pcidevaddr_t dev,uint8_t reg) +{ +outl (PCI_CONF1_ADDRESS (dev, reg),0xCF8 ); +return inw (0xCFC ); +} +static inline uint32_t pci_config_readl (pcidevaddr_t dev,uint8_t reg) { -uint32_t index = reg | (dev <<8 ) | (0x1 <<31 ); -outl (index,0xCF8 ); +outl (PCI_CONF1_ADDRESS (dev, reg),0xCF8 );return inl (0xCFC ); } +static inline void pci_config_writeb (pcidevaddr_t dev,uint8_t reg, +uint8_t val) +{ +outl (PCI_CONF1_ADDRESS (dev, reg),0xCF8 ); +outb (val,0xCFC ); +} + +static inline void pci_config_writew (pcidevaddr_t dev,uint8_t reg, +uint16_t val) +{ +outl (PCI_CONF1_ADDRESS (dev, reg),0xCF8 ); +outw (val,0xCFC ); +} + +static inline void pci_config_writel (pcidevaddr_t dev,uint8_t reg, +uint32_t val) +{ +outl (PCI_CONF1_ADDRESS (dev, reg),0xCF8 ); +outl (val,0xCFC ); +} +#endif
Signature · 1 line
1.8.3.1
PATCH v11 5/12 pci: Factor out pci_bar_get()
In reply to Alexander GordeevCc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Thomas Huth <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
lib/pci.c +8 -3
@@ -21,9 +21,14 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)return PCIDEVADDR_INVALID ; } +static uint32_t pci_bar_get (pcidevaddr_t dev,int bar_num) +{ +return pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); +} +unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num) { -uint32_t bar =pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); +uint32_t bar =pci_bar_get (dev, bar_num);if (bar &PCI_BASE_ADDRESS_SPACE_IO )return bar &PCI_BASE_ADDRESS_IO_MASK ;
@@ -33,12 +38,12 @@ unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num) { -uint32_t bar =pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); +uint32_t bar =pci_bar_get (dev, bar_num);return !(bar &PCI_BASE_ADDRESS_SPACE_IO ); }bool pci_bar_is_valid (pcidevaddr_t dev,int bar_num) { -return pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); +return pci_bar_get (dev, bar_num); }
Signature · 1 line
1.8.3.1
PATCH v11 6/12 pci: Rework pci_bar_addr()
In reply to Alexander GordeevThis update makes pci_bar_addr() interface 64 bit BARs aware and introduces a concept of PCI address translation.
An architecutre should implement pci_translate_addr() interface in order to provide mapping between PCI bus address and CPU physical address.
Cc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Thomas Huth <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++---- lib/pci.h | 17 ++++++++++++- lib/x86/asm/pci.h | 6 +++++ 3 files changed, 90 insertions(+), 6 deletions(-)
lib/pci.c +68 -5
@@ -21,19 +21,71 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)return PCIDEVADDR_INVALID ; } +static uint32_t pci_bar_mask (uint32_t bar) +{ +return (bar &PCI_BASE_ADDRESS_SPACE_IO ) ? +PCI_BASE_ADDRESS_IO_MASK :PCI_BASE_ADDRESS_MEM_MASK ; +} +static uint32_t pci_bar_get (pcidevaddr_t dev,int bar_num) {return pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); } -unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num) +phys_addr_t pci_bar_addr (pcidevaddr_t dev,int bar_num) {uint32_t bar =pci_bar_get (dev, bar_num); +uint32_t mask =pci_bar_mask (bar); +uint64_t addr = bar & mask; -if (bar &PCI_BASE_ADDRESS_SPACE_IO ) -return bar &PCI_BASE_ADDRESS_IO_MASK ; -else -return bar &PCI_BASE_ADDRESS_MEM_MASK ; +if (pci_bar_is64 (dev, bar_num)) + addr |= (uint64_t )pci_bar_get (dev, bar_num +1 ) <<32 ; + +return pci_translate_addr (dev, addr); +} + +/* +* To determine the amount of address space needed by a PCI device, +* one must save the original value of the BAR, write a value of +* all 1's to the register, and then read it back. The amount of +* memory can be then determined by masking the information bits, +* performing a bitwise NOT, and incrementing the value by 1. +* +* The following pci_bar_size_helper() and pci_bar_size() functions +* implement the algorithm. +*/ +static uint32_t pci_bar_size_helper (pcidevaddr_t dev,int bar_num) +{ +int off =PCI_BASE_ADDRESS_0 + bar_num *4 ; +uint32_t bar, val; + + bar =pci_config_readl (dev, off); +pci_config_writel (dev, off, ~0u ); + val =pci_config_readl (dev, off); +pci_config_writel (dev, off, bar); + +return val; +} + +phys_addr_t pci_bar_size (pcidevaddr_t dev,int bar_num) +{ +uint32_t bar, size; + + size =pci_bar_size_helper (dev, bar_num); +if (!size) +return 0 ; + + bar =pci_bar_get (dev, bar_num); + size &=pci_bar_mask (bar); + +if (pci_bar_is64 (dev, bar_num)) { +phys_addr_t size64 =pci_bar_size_helper (dev, bar_num +1 ); + size64 = (size64 <<32 ) | size; + +return ~size64 +1 ; + }else { +return ~size +1 ; + } }bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num)
@@ -47,3 +99,14 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num) {return pci_bar_get (dev, bar_num); } + +bool pci_bar_is64 (pcidevaddr_t dev,int bar_num) +{ +uint32_t bar =pci_bar_get (dev, bar_num); + +if (bar &PCI_BASE_ADDRESS_SPACE_IO ) +return false; + +return (bar &PCI_BASE_ADDRESS_MEM_TYPE_MASK ) == +PCI_BASE_ADDRESS_MEM_TYPE_64 ; +}
lib/pci.h +16 -1
@@ -16,7 +16,22 @@ enum { };extern pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id); -extern unsigned long pci_bar_addr (pcidevaddr_t dev,int bar_num); + +/* +* @bar_num in all BAR access functions below is the index of the 32-bit +* register starting from the PCI_BASE_ADDRESS_0 offset. +* +* In cases where the BAR size is 64-bit, a caller should still provide +* @bar_num in terms of 32-bit words. For example, if a device has a 64-bit +* BAR#0 and a 32-bit BAR#1, then caller should provide 2 to address BAR#1, +* not 1. +* +* It is expected the caller is aware of the device BAR layout and never +* tries to address the middle of a 64-bit register. +*/ +extern phys_addr_t pci_bar_addr (pcidevaddr_t dev,int bar_num); +extern phys_addr_t pci_bar_size (pcidevaddr_t dev,int bar_num); +extern bool pci_bar_is64 (pcidevaddr_t dev,int bar_num);extern bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num);extern bool pci_bar_is_valid (pcidevaddr_t dev,int bar_num);
lib/x86/asm/pci.h +6 -0
@@ -50,4 +50,10 @@ static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg,outl (val,0xCFC ); } +static inline +phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr) +{ +return addr; +} +#endif
Signature · 1 line
1.8.3.1
PATCH v11 7/12 pci: Add pci_bar_set_addr()
In reply to Alexander GordeevBecause the counterpart to pci_bar_set_addr() setter is pci_bar_addr() getter, these names become inconsistent. Rename pci_bar_addr() to pci_bar_get_addr() also to make the resulting names conform to each other.
Cc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 12 +++++++++++- lib/pci.h | 3 ++- x86/vmexit.c | 4 ++-- 3 files changed, 15 insertions(+), 4 deletions(-)
lib/pci.c +11 -1
@@ -32,7 +32,7 @@ static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)return pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); } -phys_addr_t pci_bar_addr (pcidevaddr_t dev,int bar_num) +phys_addr_t pci_bar_get_addr (pcidevaddr_t dev,int bar_num) {uint32_t bar =pci_bar_get (dev, bar_num);uint32_t mask =pci_bar_mask (bar);
@@ -44,6 +44,16 @@ phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)return pci_translate_addr (dev, addr); } +void pci_bar_set_addr (pcidevaddr_t dev,int bar_num,phys_addr_t addr) +{ +int off =PCI_BASE_ADDRESS_0 + bar_num *4 ; + +pci_config_writel (dev, off, (uint32_t )addr); + +if (pci_bar_is64 (dev, bar_num)) +pci_config_writel (dev, off +4 , (uint32_t )(addr >>32 )); +} +/* * To determine the amount of address space needed by a PCI device, * one must save the original value of the BAR, write a value of
lib/pci.h +2 -1
@@ -29,7 +29,8 @@ extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);* It is expected the caller is aware of the device BAR layout and never * tries to address the middle of a 64-bit register. */ -extern phys_addr_t pci_bar_addr (pcidevaddr_t dev,int bar_num); +extern phys_addr_t pci_bar_get_addr (pcidevaddr_t dev,int bar_num); +extern void pci_bar_set_addr (pcidevaddr_t dev,int bar_num,phys_addr_t addr);extern phys_addr_t pci_bar_size (pcidevaddr_t dev,int bar_num);extern bool pci_bar_is64 (pcidevaddr_t dev,int bar_num);extern bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num);
x86/vmexit.c +2 -2
@@ -392,10 +392,10 @@ int main(int ac, char **av)continue ; }if (pci_bar_is_memory (pcidev, i)) { - membar =pci_bar_addr (pcidev, i); + membar =pci_bar_get_addr (pcidev, i); pci_test.memaddr =ioremap (membar,PAGE_SIZE ); }else { - pci_test.iobar =pci_bar_addr (pcidev, i); + pci_test.iobar =pci_bar_get_addr (pcidev, i); } } printf("pci-testdev at 0x%x membar %lx iobar %x\n",
Signature · 1 line
1.8.3.1
PATCH v11 8/12 pci: Add pci_dev_exists()
In reply to Alexander GordeevCc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 6 ++++++ lib/pci.h | 1 + 2 files changed, 7 insertions(+)
lib/pci.c +6 -0
@@ -7,6 +7,12 @@#include "pci.h" #include "asm/pci.h" +bool pci_dev_exists (pcidevaddr_t dev) +{ +return (pci_config_readw (dev,PCI_VENDOR_ID ) !=0xffff && +pci_config_readw (dev,PCI_DEVICE_ID ) !=0xffff ); +} +/* Scan bus look for a specific device. Only bus 0 scanned for now. */ pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id) {
lib/pci.h +1 -0
@@ -15,6 +15,7 @@ enum { PCIDEVADDR_INVALID = 0xffff, }; +extern bool pci_dev_exists (pcidevaddr_t dev);extern pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id);/*
Signature · 1 line
1.8.3.1
PATCH v11 9/12 pci: Add pci_print()
In reply to Alexander GordeevCc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Suggested-by Andrew Jones <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/pci.h | 3 +++ 2 files changed, 92 insertions(+)
lib/pci.c +89 -0
@@ -126,3 +126,92 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num)return (bar &PCI_BASE_ADDRESS_MEM_TYPE_MASK ) ==PCI_BASE_ADDRESS_MEM_TYPE_64 ; } + +static void pci_bar_print (pcidevaddr_t dev,int bar_num) +{ +phys_addr_t size, start, end; +uint32_t bar; + + size =pci_bar_size (dev, bar_num); +if (!size) +return ; + + bar =pci_bar_get (dev, bar_num); + start =pci_bar_get_addr (dev, bar_num); + end = start + size -1 ; + +if (pci_bar_is64 (dev, bar_num)) { +printf ("BAR#%d,%d [%" PRIx64"-%" PRIx64" " , + bar_num, bar_num +1 , start, end); + }else { +printf ("BAR#%d [%02x-%02x " , + bar_num, (uint32_t )start, (uint32_t )end); + } + +if (bar &PCI_BASE_ADDRESS_SPACE_IO ) { +printf ("PIO" ); + }else { +printf ("MEM" ); +switch (bar &PCI_BASE_ADDRESS_MEM_TYPE_MASK ) { +case PCI_BASE_ADDRESS_MEM_TYPE_32 : +printf ("32" ); +break ; +case PCI_BASE_ADDRESS_MEM_TYPE_1M : +printf ("1M" ); +break ; +case PCI_BASE_ADDRESS_MEM_TYPE_64 : +printf ("64" ); +break ; +default : +assert (0 ); + } + } + +if (bar &PCI_BASE_ADDRESS_MEM_PREFETCH ) +printf ("/p" ); + +printf ("]" ); +} + +static void pci_dev_print_id (pcidevaddr_t dev) +{ +printf ("00.%02x.%1x %04x:%04x" , dev /8 , dev %8 , +pci_config_readw (dev,PCI_VENDOR_ID ), +pci_config_readw (dev,PCI_DEVICE_ID )); +} + +static void pci_dev_print (pcidevaddr_t dev) +{ +uint8_t header =pci_config_readb (dev,PCI_HEADER_TYPE ); +uint8_t progif =pci_config_readb (dev,PCI_CLASS_PROG ); +uint8_t subclass =pci_config_readb (dev,PCI_CLASS_DEVICE ); +uint8_t class =pci_config_readb (dev,PCI_CLASS_DEVICE +1 ); +int i; + +pci_dev_print_id (dev); +printf (" type %02x progif %02x class %02x subclass %02x\n" , + header, progif, class, subclass); + +if ((header &PCI_HEADER_TYPE_MASK ) !=PCI_HEADER_TYPE_NORMAL ) +return ; + +for (i =0 ; i <6 ; i++) { +if (pci_bar_size (dev, i)) { +printf ("\t" ); +pci_bar_print (dev, i); +printf ("\n" ); + } +if (pci_bar_is64 (dev, i)) + i++; + } +} + +void pci_print (void ) +{ +pcidevaddr_t dev; + +for (dev =0 ; dev <256 ; ++dev) { +if (pci_dev_exists (dev)) +pci_dev_print (dev); + } +}
lib/pci.h +3 -0
@@ -15,6 +15,7 @@ enum { PCIDEVADDR_INVALID = 0xffff, }; +extern void pci_print (void );extern bool pci_dev_exists (pcidevaddr_t dev);extern pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id);
@@ -57,4 +58,6 @@ struct pci_test_dev_hdr { uint8_t name[]; }; +#define PCI_HEADER_TYPE_MASK 0x7f +#endif /* PCI_H */
Signature · 1 line
1.8.3.1
PATCH v11 10/12 pci: Add generic ECAM host support
In reply to Alexander GordeevUnlike x86, other architectures using generic ECAM PCI host do not have a luxury of PCI bus initialized by a BIOS and ready to use at start. Thus, we need allocate and assign resources to all devices, much like an architecture's firmware would do.
There is no any sort of resource management for memory and io spaces, since only ones-per-BAR allocations are expected and no deallocations at all.
Cc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Suggested-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/asm-generic/pci-host-bridge.h | 28 ++++ lib/pci-host-generic.c | 318 ++++++++++++++++++++++++++++++++++++++ lib/pci-host-generic.h | 46 ++++++ lib/pci.c | 8 +- lib/pci.h | 5 + 5 files changed, 401 insertions(+), 4 deletions(-) create mode 100644 lib/asm-generic/pci-host-bridge.h create mode 100644 lib/pci-host-generic.c create mode 100644 lib/pci-host-generic.h
lib/asm-generic/pci-host-bridge.h new file +28 -0
@@ -0,0 +1,28 @@ +#ifndef _ASM_PCI_HOST_BRIDGE_H_ +#define _ASM_PCI_HOST_BRIDGE_H_ +/* +* Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <[email protected]> +* +* This work is licensed under the terms of the GNU LGPL, version 2. +*/ +#include "libcflat.h" + +phys_addr_t pci_host_bridge_get_paddr (uint64_t addr); + +static inline +phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr) +{ +/* +* Assume we only have single PCI host bridge in a system. +*/ +return pci_host_bridge_get_paddr (addr); +} + +uint8_t pci_config_readb (pcidevaddr_t dev,uint8_t reg); +uint16_t pci_config_readw (pcidevaddr_t dev,uint8_t reg); +uint32_t pci_config_readl (pcidevaddr_t dev,uint8_t reg); +void pci_config_writeb (pcidevaddr_t dev,uint8_t reg,uint8_t val); +void pci_config_writew (pcidevaddr_t dev,uint8_t reg,uint16_t val); +void pci_config_writel (pcidevaddr_t dev,uint8_t reg,uint32_t val); + +#endif
lib/pci-host-generic.c new file +318 -0
318 lines not on this page · raw message
lib/pci-host-generic.h new file +46 -0
46 lines not on this page · raw message
lib/pci.c +4 -4
@@ -27,13 +27,13 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)return PCIDEVADDR_INVALID ; } -static uint32_t pci_bar_mask (uint32_t bar) +uint32_t pci_bar_mask (uint32_t bar) {return (bar &PCI_BASE_ADDRESS_SPACE_IO ) ?PCI_BASE_ADDRESS_IO_MASK :PCI_BASE_ADDRESS_MEM_MASK ; } -static uint32_t pci_bar_get (pcidevaddr_t dev,int bar_num) +uint32_t pci_bar_get (pcidevaddr_t dev,int bar_num) {return pci_config_readl (dev,PCI_BASE_ADDRESS_0 + bar_num *4 ); }
@@ -127,7 +127,7 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num)PCI_BASE_ADDRESS_MEM_TYPE_64 ; } -static void pci_bar_print (pcidevaddr_t dev,int bar_num) +void pci_bar_print (pcidevaddr_t dev,int bar_num) {phys_addr_t size, start, end;uint32_t bar;
@@ -173,7 +173,7 @@ static void pci_bar_print(pcidevaddr_t dev, int bar_num)printf ("]" ); } -static void pci_dev_print_id (pcidevaddr_t dev) +void pci_dev_print_id (pcidevaddr_t dev) { printf("00.%02x.%1x %04x:%04x", dev / 8, dev % 8, pci_config_readw(dev, PCI_VENDOR_ID),
lib/pci.h +5 -0
@@ -15,6 +15,7 @@ enum { PCIDEVADDR_INVALID = 0xffff, }; +extern bool pci_probe (void );extern void pci_print (void );extern bool pci_dev_exists (pcidevaddr_t dev);extern pcidevaddr_t pci_find_dev (uint16_t vendor_id,uint16_t device_id);
@@ -34,9 +35,13 @@ extern pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);extern phys_addr_t pci_bar_get_addr (pcidevaddr_t dev,int bar_num);extern void pci_bar_set_addr (pcidevaddr_t dev,int bar_num,phys_addr_t addr);extern phys_addr_t pci_bar_size (pcidevaddr_t dev,int bar_num); +extern uint32_t pci_bar_get (pcidevaddr_t dev,int bar_num); +extern uint32_t pci_bar_mask (uint32_t bar);extern bool pci_bar_is64 (pcidevaddr_t dev,int bar_num);extern bool pci_bar_is_memory (pcidevaddr_t dev,int bar_num);extern bool pci_bar_is_valid (pcidevaddr_t dev,int bar_num); +extern void pci_bar_print (pcidevaddr_t dev,int bar_num); +extern void pci_dev_print_id (pcidevaddr_t dev);/* * pci-testdev is a driver for the pci-testdev qemu pci device. The
Signature · 1 line
1.8.3.1
Re: [kvm-unit-tests PATCH v11 10/12] pci: Add generic ECAM host support
Quoted 15 lines · Alexander Gordeev
Unlike x86, other architectures using generic ECAM PCI host do not have a luxury of PCI bus initialized by a BIOS and ready to use at start. Thus, we need allocate and assign resources to all devices, much like an architecture's firmware would do.
There is no any sort of resource management for memory and io spaces, since only ones-per-BAR allocations are expected and no deallocations at all.
Cc Thomas Huth <[email protected]>Cc Andrew Jones <[email protected]>Cc Peter Xu <[email protected]>Suggested-by Andrew Jones <[email protected]>Signed-off-by Alexander Gordeev <[email protected]>
Quoted 11 lines
--- lib/asm-generic/pci-host-bridge.h | 28 ++++ lib/pci-host-generic.c | 318 ++++++++++++++++++++++++++++++++++++++ lib/pci-host-generic.h | 46 ++++++ lib/pci.c | 8 +- lib/pci.h | 5 + 5 files changed, 401 insertions(+), 4 deletions(-) create mode 100644 lib/asm-generic/pci-host-bridge.h create mode 100644 lib/pci-host-generic.c create mode 100644 lib/pci-host-generic.h
Reviewed-by Andrew Jones <[email protected]>
PATCH v11 11/12 pci: Add pci-testdev PCI bus test device
In reply to Alexander GordeevCc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- lib/pci-testdev.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/pci.h | 7 ++ 2 files changed, 199 insertions(+) create mode 100644 lib/pci-testdev.c
lib/pci-testdev.c new file +192 -0
@@ -0,0 +1,192 @@ +/* +* QEMU "pci-testdev" PCI test device +* +* Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <[email protected]> +* +* This work is licensed under the terms of the GNU LGPL, version 2. +*/ +#include "pci.h" +#include "asm/io.h" + +struct pci_testdev_ops { +u8 (*io_readb)(const volatile void *addr); +u16 (*io_readw)(const volatile void *addr); +u32 (*io_readl)(const volatile void *addr); +void (*io_writeb)(u8 value,volatile void *addr); +void (*io_writew)(u16 value,volatile void *addr); +void (*io_writel)(u32 value,volatile void *addr); +}; + +static u8 pio_readb (const volatile void *addr) +{ +return inb ((unsigned long )addr); +} + +static u16 pio_readw (const volatile void *addr) +{ +return inw ((unsigned long )addr); +} + +static u32 pio_readl (const volatile void *addr) +{ +return inl ((unsigned long )addr); +} + +static void pio_writeb (u8 value,volatile void *addr) +{ +outb (value, (unsigned long )addr); +} + +static void pio_writew (u16 value,volatile void *addr) +{ +outw (value, (unsigned long )addr); +} + +static void pio_writel (u32 value,volatile void *addr) +{ +outl (value, (unsigned long )addr); +} + +static struct pci_testdev_ops pci_testdev_io_ops = { + .io_readb = pio_readb, + .io_readw = pio_readw, + .io_readl = pio_readl, + .io_writeb = pio_writeb, + .io_writew = pio_writew, + .io_writel = pio_writel +}; + +static u8 mmio_readb (const volatile void *addr) +{ +return *(const volatile u8 __force *)addr; +} + +static u16 mmio_readw (const volatile void *addr) +{ +return *(const volatile u16 __force *)addr; +} + +static u32 mmio_readl (const volatile void *addr) +{ +return *(const volatile u32 __force *)addr; +} + +static void mmio_writeb (u8 value,volatile void *addr) +{ + *(volatile u8 __force *)addr = value; +} + +static void mmio_writew (u16 value,volatile void *addr) +{ + *(volatile u16 __force *)addr = value; +} + +static void mmio_writel (u32 value,volatile void *addr) +{ + *(volatile u32 __force *)addr = value; +} + +static struct pci_testdev_ops pci_testdev_mem_ops = { + .io_readb = mmio_readb, + .io_readw = mmio_readw, + .io_readl = mmio_readl, + .io_writeb = mmio_writeb, + .io_writew = mmio_writew, + .io_writel = mmio_writel +}; + +static bool pci_testdev_one (struct pci_test_dev_hdr *test, +int test_nr, +struct pci_testdev_ops *ops) +{ +u8 width; +u32 count, sig, off; +const int nr_writes =16 ; +int i; + + ops->io_writeb (test_nr, &test->test); + count = ops->io_readl (&test->count); +if (count !=0 ) +return false; + + width = ops->io_readb (&test->width); +if (width !=1 && width !=2 && width !=4 ) +return false; + + sig = ops->io_readl (&test->data); + off = ops->io_readl (&test->offset); + +for (i =0 ; i < nr_writes; i++) { +switch (width) { +case 1 : ops->io_writeb (sig, (void *)test + off);break ; +case 2 : ops->io_writew (sig, (void *)test + off);break ; +case 4 : ops->io_writel (sig, (void *)test + off);break ; + } + } + + count = ops->io_readl (&test->count); +if (!count) +return true; + +return (int )count == nr_writes; +} + +void pci_testdev_print (struct pci_test_dev_hdr *test, +struct pci_testdev_ops *ops) +{ +bool io = (ops == &pci_testdev_io_ops); +int i; + +printf ("pci-testdev %3s: " , io ?"io" :"mem" ); +for (i =0 ;; ++i) { +char c = ops->io_readb (&test->name[i]); +if (!c) +break ; +printf ("%c" , c); + } +printf ("\n" ); +} + +static int pci_testdev_all (struct pci_test_dev_hdr *test, +struct pci_testdev_ops *ops) +{ +int i; + +for (i =0 ;; i++) { +if (!pci_testdev_one (test, i, ops)) +break ; +pci_testdev_print (test, ops); + } + +return i; +} + +int pci_testdev (void ) +{ +phys_addr_t addr; +void __iomem *mem, *io; +pcidevaddr_t dev; +int nr_tests =0 ; +bool ret; + + dev =pci_find_dev (PCI_VENDOR_ID_REDHAT ,PCI_DEVICE_ID_REDHAT_TEST ); +if (dev ==PCIDEVADDR_INVALID ) { +printf ("'pci-testdev' device is not found, " +"check QEMU '-device pci-testdev' parameter\n" ); +return -1 ; + } + + ret =pci_bar_is_valid (dev,0 ) &&pci_bar_is_valid (dev,1 ); +assert (ret); + + addr =pci_bar_get_addr (dev,0 ); + mem =ioremap (addr,PAGE_SIZE ); + + addr =pci_bar_get_addr (dev,1 ); + io = (void *)(unsigned long )addr; + + nr_tests +=pci_testdev_all (mem, &pci_testdev_mem_ops); + nr_tests +=pci_testdev_all (io, &pci_testdev_io_ops); + +return nr_tests; +}
lib/pci.h +7 -0
@@ -43,6 +43,8 @@ extern bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);extern void pci_bar_print (pcidevaddr_t dev,int bar_num);extern void pci_dev_print_id (pcidevaddr_t dev); +int pci_testdev (void ); +/* * pci-testdev is a driver for the pci-testdev qemu pci device. The * device enables testing mmio and portio exits, and measuring their
@@ -51,7 +53,12 @@ extern void pci_dev_print_id(pcidevaddr_t dev);#define PCI_VENDOR_ID_REDHAT 0x1b36#define PCI_DEVICE_ID_REDHAT_TEST 0x0005 +/* +* pci-testdev supports at least three types of tests (via mmio and +* portio BARs): no-eventfd, wildcard-eventfd and datamatch-eventfd +*/ #define PCI_TESTDEV_NUM_BARS 2 +#define PCI_TESTDEV_NUM_TESTS 3struct pci_test_dev_hdr {uint8_t test;
Signature · 1 line
1.8.3.1
PATCH v11 12/12 arm/arm64: pci: Add pci-testdev PCI device operation test
In reply to Alexander GordeevSuggested-by Andrew Jones <[email protected]>
Cc Thomas Huth <[email protected]>
Cc Andrew Jones <[email protected]>
Cc Peter Xu <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Signed-off-by Alexander Gordeev <[email protected]>
--- arm/Makefile.common | 6 +++++- arm/pci-test.c | 27 +++++++++++++++++++++++++++ arm/run | 7 ++++++- arm/unittests.cfg | 4 ++++ lib/arm/asm/pci.h | 1 + lib/arm64/asm/pci.h | 1 + 6 files changed, 44 insertions(+), 2 deletions(-) create mode 100644 arm/pci-test.c create mode 100644 lib/arm/asm/pci.h create mode 100644 lib/arm64/asm/pci.h
arm/Makefile.common +5 -1
@@ -11,7 +11,8 @@ endif tests-common = \ $(TEST_DIR)/selftest.flat \ - $(TEST_DIR)/spinlock-test.flat + $(TEST_DIR)/spinlock-test.flat \ + $(TEST_DIR)/pci-test.flat all: test_cases
@@ -33,6 +34,9 @@ include scripts/asm-offsets.mak cflatobjs += lib/util.o cflatobjs += lib/alloc.o cflatobjs += lib/devicetree.o +cflatobjs += lib/pci.o +cflatobjs += lib/pci-host-generic.o +cflatobjs += lib/pci-testdev.o cflatobjs += lib/virtio.o cflatobjs += lib/virtio-mmio.o cflatobjs += lib/chr-testdev.o
arm/pci-test.c new file +27 -0
@@ -0,0 +1,27 @@ +/* +* PCI bus operation test +* +* Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <[email protected]> +* +* This work is licensed under the terms of the GNU LGPL, version 2. +*/ +#include <libcflat.h> +#include <pci.h> + +#define NR_TESTS (PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS) + +int main (void ) +{ +int ret; + +if (!pci_probe ()) +report_abort ("PCI bus probing failed\n" ); + +pci_print (); + + ret =pci_testdev (); +report ("PCI test device passed %d/%d tests" , + ret >=NR_TESTS , ret >0 ? ret :0 ,NR_TESTS ); + +return report_summary (); +}
arm/run +6 -1
@@ -67,8 +67,13 @@ fi chr_testdev='-device virtio-serial-device' chr_testdev+=' -device virtconsole,chardev=ctd -chardev testdev,id=ctd' +pci_testdev= +if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then + pci_testdev="-device pci-testdev" +fi + M+=",accel=$ACCEL" -command="$qemu $M -cpu $processor $chr_testdev" +command="$qemu $M -cpu $processor $chr_testdev $pci_testdev" command+=" -display none -serial stdio -kernel" command="$(timeout_cmd) $command" echo $command "$@"
arm/unittests.cfg +4 -0
@@ -54,3 +54,7 @@ file = selftest.flat smp = $MAX_SMP extra_params = -append 'smp' groups = selftest + +[pci-test] +file = pci-test.flat +groups = pci
lib/arm/asm/pci.h new file +1 -0
@@ -0,0 +1 @@ +#include <asm-generic/pci-host-bridge.h>
lib/arm64/asm/pci.h new file +1 -0
@@ -0,0 +1 @@ +#include "../../arm/asm/pci.h"
Signature · 1 line
1.8.3.1
Quoted 15 lines · Alexander Gordeev
This is 11th version of PCI support.
Changes since v9:
- all PCI configuration space accessors added;
- data size in PCI configuration space accessors fixed;
- PCI bus parity checking enabled;
- coding style errors fixed;Sources are avalable at:
https://github.com/a-gordeev/kvm-unit-tests.git pci-testdev-v11Cc Thomas Huth <[email protected]>Cc Andrew Jones <[email protected]>Cc Peter Xu <[email protected]>
Quoted 14 lines
Alexander Gordeev (12):
pci: Fix coding style in generic PCI files
pci: x86: Renamepci_config_read()topci_config_readl()
pci: Add 'extern' to public function declarations
pci: x86: Add remaining PCI configuration space accessors
pci: Factor outpci_bar_get()
pci: Reworkpci_bar_addr()
pci: Addpci_bar_set_addr()
pci: Addpci_dev_exists()
pci: Addpci_print()
pci: Add generic ECAM host support
pci: Add pci-testdev PCI bus test device arm/arm64: pci: Add pci-testdev PCI device operation test
All patches look good to me!
Paolo, please merge this version (v11).
Thanks,
drew
Paolo Bonzini
maintainerQuoted 31 lines · Andrew Jones
Quoted 15 lines · Alexander Gordeev
This is 11th version of PCI support.
Changes since v9:
- all PCI configuration space accessors added;
- data size in PCI configuration space accessors fixed;
- PCI bus parity checking enabled;
- coding style errors fixed;Sources are avalable at:
https://github.com/a-gordeev/kvm-unit-tests.git pci-testdev-v11Cc Thomas Huth <[email protected]>Cc Andrew Jones <[email protected]>Cc Peter Xu <[email protected]>Quoted 14 lines
Alexander Gordeev (12):
pci: Fix coding style in generic PCI files
pci: x86: Renamepci_config_read()topci_config_readl()
pci: Add 'extern' to public function declarations
pci: x86: Add remaining PCI configuration space accessors
pci: Factor outpci_bar_get()
pci: Reworkpci_bar_addr()
pci: Addpci_bar_set_addr()
pci: Addpci_dev_exists()
pci: Addpci_print()
pci: Add generic ECAM host support
pci: Add pci-testdev PCI bus test device arm/arm64: pci: Add pci-testdev PCI device operation test
Quoted 3 lines
All patches look good to me!
Paolo, please merge this version (v11).
I haven't pushed yet, but I've applied it.
Paolo