OpenRISC patches for 4.11

From: Stefan Kristiansson <[email protected]>

This brings it inline with the other setup oprations done like the cache enables _ic_enable and _dc_enable. Also, this is going to make it easier to initialize additional cpu's when smp is introduced.

Signed-off-by Stefan Kristiansson <[email protected]>

[[email protected]: Added commit body]

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/head.S | 38 ++++++++++++++++++++++----------------
  1 file changed, 22 insertions(+), 16 deletions(-)

arch/openrisc/kernel/head.S +22 -16

index 63ba2d9..a22f1fc 100644
@@ -522,22 +522,8 @@ enable_dc:
  	 l.nop
 
  flush_tlb:
-	/*
-	 *  I N V A L I D A T E   T L B   e n t r i e s
-	 */
-	LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
-	LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
-	l.addi	r7,r0,128 /* Maximum number of sets */
-1:
-	l.mtspr	r5,r0,0x0
-	l.mtspr	r6,r0,0x0
-
-	l.addi	r5,r5,1
-	l.addi	r6,r6,1
-	l.sfeq	r7,r0
-	l.bnf	1b
-	 l.addi	r7,r7,-1
-
+	l.jal	_flush_tlb
+	 l.nop
 
  /* The MMU needs to be enabled before or32_early_setup is called */
 

@@ -629,6 +615,26 @@ jump_start_kernel:
  	l.jr    r30
  	 l.nop
 
+_flush_tlb:
+	/*
+	 *  I N V A L I D A T E   T L B   e n t r i e s
+	 */
+	LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
+	LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
+	l.addi	r7,r0,128 /* Maximum number of sets */
+1:
+	l.mtspr	r5,r0,0x0
+	l.mtspr	r6,r0,0x0
+
+	l.addi	r5,r5,1
+	l.addi	r6,r6,1
+	l.sfeq	r7,r0
+	l.bnf	1b
+	 l.addi	r7,r7,-1
+
+	l.jr	r9
+	 l.nop
+
  /* ========================================[ cache ]=== */
 
  	/* aligment here so we don't change memory offsets with

Quoted 5 lines · Stafford Horne

From: Stefan Kristiansson <[email protected]>

This brings it inline with the other setup oprations done like the cache enables _ic_enable and _dc_enable. Also, this is going to make it easier to initialize additional cpu's when smp is introduced.

This patch confuses me. The TLB flush is moved to a point after MMU's are enabled. The TLB flush should happen before enabling the MMU, shouldn't it?

Quoted 6 lines · Jonas Bonn

Quoted 5 lines · Stafford Horne

From: Stefan Kristiansson <[email protected]>

This brings it inline with the other setup oprations done like the cache enables _ic_enable and _dc_enable. Also, this is going to make it easier to initialize additional cpu's when smp is introduced.

Quoted 3 lines

This patch confuses me. The TLB flush is moved to a point after MMU's are enabled. The TLB flush should happen before enabling the MMU, shouldn't it?

It still happens before the MMUs are enabled, the patch only refactors the code out into a function that is called from the place where it was open coded before.

Stefan

Quoted 7 lines · Stefan Kristiansson

Quoted 6 lines · Jonas Bonn

Quoted 5 lines · Stafford Horne

From: Stefan Kristiansson <[email protected]>

This brings it inline with the other setup oprations done like the cache enables _ic_enable and _dc_enable. Also, this is going to make it easier to initialize additional cpu's when smp is introduced.

Quoted 6 lines

Quoted 3 lines

This patch confuses me. The TLB flush is moved to a point after MMU's are enabled. The TLB flush should happen before enabling the MMU, shouldn't it?

It still happens before the MMUs are enabled, the patch only refactors the code out into a function that is called from the place where it was open coded before.

Right. What's the point of moving it then?

Quoted 15 lines · Jonas Bonn

Quoted 13 lines · Stefan Kristiansson

Quoted 9 lines · Jonas Bonn

Quoted 5 lines · Stafford Horne

From: Stefan Kristiansson <[email protected]>

This brings it inline with the other setup oprations done like the cache enables _ic_enable and _dc_enable. Also, this is going to make it easier to initialize additional cpu's when smp is introduced.

This patch confuses me. The TLB flush is moved to a point after MMU's are enabled. The TLB flush should happen before enabling the MMU, shouldn't it?

It still happens before the MMUs are enabled, the patch only refactors the code out into a function that is called from the place where it was open coded before.

Quoted 2 lines

Right. What's the point of moving it then?

As the commit message mentions, it's a preparation patch for initialisation of secondary cpus, which also will call this function.

Perhaps this patch should be bundled with those patches.

From: Stefan Kristiansson <[email protected]>

This adds an emulation layer for implementations that lack the l.lwa and l.swa instructions. It handles these instructions both in kernel space and user space.

Signed-off-by Stefan Kristiansson <[email protected]>

[shorne at gmail.com: Added delay slot pc adjust logic]

Signed-off-by Stafford Horne <[email protected]>

Quoted 7 lines · Stafford Horne

From: Stefan Kristiansson <[email protected]>

This adds an emulation layer for implementations that lack the l.lwa and l.swa instructions. It handles these instructions both in kernel space and user space.

Quoted 3 lines

Signed-off-by Stefan Kristiansson <[email protected]>

[shorne at gmail.com: Added delay slot pc adjust logic]

Signed-off-by Stafford Horne <[email protected]>

What happened here? A bit of junk has slunk in among your Sign-offs!

These 4 patches (7,8,9,10) look good to me.

Thanks!

Acked-by Peter Zijlstra (Intel) <[email protected]>

Openrisc stack pointer is managed by decrementing r1. Add regexes to recognize this.

Signed-off-by Stafford Horne <[email protected]>

---
 scripts/checkstack.pl | 3 +++
 1 file changed, 3 insertions(+)

scripts/checkstack.pl +0 -0

index dd83978..eea5b78 100755

Quoted 8 lines · Stafford Horne

Openrisc stack pointer is managed by decrementing r1. Add regexes to recognize this.

Signed-off-by Stafford Horne <[email protected]>

---
 scripts/checkstack.pl | 3 +++
 1 file changed, 3 insertions(+)

scripts/checkstack.pl my (@stack, $re, $dre, $x, $xs, $funcre); · line 111

Quoted 11 lines

scripts/checkstack.pl +3 -0

index dd83978..eea5b78 100755
@@ -106,6 +106,9 @@ my (@stack, $re, $dre, $x, $xs, $funcre);
 	} elsif ($arch eq 'sparc' || $arch eq 'sparc64') {
 		# f0019d10:       9d e3 bf 90     save  %sp, -112, %sp
 		$re = qr/.*save.*%sp, -(([0-9]{2}|[3-9])[0-9]{2}), %sp/o;
+	} elsif ($arch eq 'openrisc') {
+		# c000043c:       9c 21 fe f0     l.addi r1,r1,-272
+		$re = qr/.*l\.addi.*r1,r1,-(([0-9]{2}|[3-9])[0-9]{2})/o;

The if/elsif clauses are currently ordered alphabetically (except for blackfin :-/), so this should rather be inserted above after nios2.

Cleanups to whitespace and add some comments. Reading through the delay slot logic I noticed some things:
- Delay slot instructions were not indented
- Some comments are not lined up
- Use tabs and spaces consistent with other code

No functional change

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/entry.S | 38 ++++++++++++++++++--------------------
  1 file changed, 18 insertions(+), 20 deletions(-)

arch/openrisc/kernel/entry.S +18 -20

index ba1a361..daae2a4 100644
@@ -228,7 +228,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
  	 * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
  	 */
  #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
-	l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+	l.lwz   r6,PT_PC(r3)               // address of an offending insn
  	l.lwz   r6,0(r6)                   // instruction that caused pf
 
  	l.srli  r6,r6,26                   // check opcode for jump insn

@@ -244,49 +244,47 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
  	l.bf    8f
  	l.sfeqi r6,0x12                    // l.jalr
  	l.bf    8f
-
-	l.nop
+	 l.nop
 
  	l.j     9f
-	l.nop
-8:
+	 l.nop
 
-	l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+8: // offending insn is in delay slot
+	l.lwz   r6,PT_PC(r3)               // address of an offending insn
  	l.addi  r6,r6,4
  	l.lwz   r6,0(r6)                   // instruction that caused pf
  	l.srli  r6,r6,26                   // get opcode
-9:
+9: // offending instruction opcode loaded in r6
 
  #else
 
-	l.mfspr r6,r0,SPR_SR		   // SR
-//	l.lwz	r6,PT_SR(r3)		   // ESR
-	l.andi	r6,r6,SPR_SR_DSX	   // check for delay slot exception
-	l.sfeqi	r6,0x1			   // exception happened in delay slot
-	l.bnf	7f
-	l.lwz	r6,PT_PC(r3)		   // address of an offending insn
+	l.mfspr r6,r0,SPR_SR               // SR
+	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
+	l.sfeqi r6,0x1                     // exception happened in delay slot
+	l.bnf   7f
+	 l.lwz  r6,PT_PC(r3)               // address of an offending insn
 
-	l.addi	r6,r6,4			   // offending insn is in delay slot
+	l.addi	r6,r6,4                    // offending insn is in delay slot
  7:
  	l.lwz   r6,0(r6)                   // instruction that caused pf
  	l.srli  r6,r6,26                   // check opcode for write access
  #endif
 
-	l.sfgeui r6,0x33		   // check opcode for write access
+	l.sfgeui r6,0x33                   // check opcode for write access
  	l.bnf   1f
  	l.sfleui r6,0x37
  	l.bnf   1f
  	l.ori   r6,r0,0x1                  // write access
  	l.j     2f
-	l.nop
+	 l.nop
  1:	l.ori   r6,r0,0x0                  // !write access
  2:
 
  	/* call fault.c handler in or32/mm/fault.c */
  	l.jal   do_page_fault
-	l.nop
+	 l.nop
  	l.j     _ret_from_exception
-	l.nop
+	 l.nop
 
  /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
  EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)

@@ -306,9 +304,9 @@ EXCEPTION_ENTRY(_insn_page_fault_handler)
 
  	/* call fault.c handler in or32/mm/fault.c */
  	l.jal   do_page_fault
-	l.nop
+	 l.nop
  	l.j     _ret_from_exception
-	l.nop
+	 l.nop
 
 
  /* ---[ 0x500: Timer exception ]----------------------------------------- */

Quoted 7 lines · Stafford Horne

Cleanups to whitespace and add some comments. Reading through the delay slot logic I noticed some things:
- Delay slot instructions were not indented
- Some comments are not lined up
- Use tabs and spaces consistent with other code

No functional change

No, don't do this. Whitespace cleanups like this make life difficult for people rebasing on your tree, as well as blunting useful tools like git blame.

I'm not against the indentation of the delay slot instructions; that seems sane and should be pretty transparent in a merge conflict.

The whitespace cleanup and tab-space toggling needs to go, though. These sorts of things are better fixed up when the code lines they apply to are changed for other, functional reasons.

I suggest you pull out the delay slot fixups into a separate patch and then just sit on the rest until you've discovered the pain of whitespace cleanup-inflicted merge conflicts and decide to just ditch them altogether.

Quoted 84 lines

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/entry.S | 38 ++++++++++++++++++--------------------
  1 file changed, 18 insertions(+), 20 deletions(-)

arch/openrisc/kernel/entry.S +18 -20

index ba1a361..daae2a4 100644
@@ -228,7 +228,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
  	 * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
  	 */
  #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
-	l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+	l.lwz   r6,PT_PC(r3)               // address of an offending insn
  	l.lwz   r6,0(r6)                   // instruction that caused pf
  	l.srli  r6,r6,26                   // check opcode for jump insn

@@ -244,49 +244,47 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
  	l.bf    8f
  	l.sfeqi r6,0x12                    // l.jalr
  	l.bf    8f
-
-	l.nop
+	 l.nop
  	l.j     9f
-	l.nop
-8:
+	 l.nop
-	l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+8: // offending insn is in delay slot
+	l.lwz   r6,PT_PC(r3)               // address of an offending insn
  	l.addi  r6,r6,4
  	l.lwz   r6,0(r6)                   // instruction that caused pf
  	l.srli  r6,r6,26                   // get opcode
-9:
+9: // offending instruction opcode loaded in r6
  #else
-	l.mfspr r6,r0,SPR_SR		   // SR
-//	l.lwz	r6,PT_SR(r3)		   // ESR
-	l.andi	r6,r6,SPR_SR_DSX	   // check for delay slot exception
-	l.sfeqi	r6,0x1			   // exception happened in delay slot
-	l.bnf	7f
-	l.lwz	r6,PT_PC(r3)		   // address of an offending insn
+	l.mfspr r6,r0,SPR_SR               // SR
+	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
+	l.sfeqi r6,0x1                     // exception happened in delay slot
+	l.bnf   7f
+	 l.lwz  r6,PT_PC(r3)               // address of an offending insn
-	l.addi	r6,r6,4			   // offending insn is in delay slot
+	l.addi	r6,r6,4                    // offending insn is in delay slot
  7:
  	l.lwz   r6,0(r6)                   // instruction that caused pf
  	l.srli  r6,r6,26                   // check opcode for write access
  #endif
-	l.sfgeui r6,0x33		   // check opcode for write access
+	l.sfgeui r6,0x33                   // check opcode for write access
  	l.bnf   1f
  	l.sfleui r6,0x37
  	l.bnf   1f
  	l.ori   r6,r0,0x1                  // write access
  	l.j     2f
-	l.nop
+	 l.nop
  1:	l.ori   r6,r0,0x0                  // !write access
  2:
  	/* call fault.c handler in or32/mm/fault.c */
  	l.jal   do_page_fault
-	l.nop
+	 l.nop
  	l.j     _ret_from_exception
-	l.nop
+	 l.nop
  /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
  EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)

@@ -306,9 +304,9 @@ EXCEPTION_ENTRY(_insn_page_fault_handler)
  	/* call fault.c handler in or32/mm/fault.c */
  	l.jal   do_page_fault
-	l.nop
+	 l.nop
  	l.j     _ret_from_exception
-	l.nop
+	 l.nop
  /* ---[ 0x500: Timer exception ]----------------------------------------- */

Use execption SR stored in pt_regs for detection, the current SR is not correct as the handler is running after return from exception.

Also, The code that checks for a delay slot uses a flag bitmask and then wants to check if the result is not zero. The test it implemented was wrong.

Correct it by changing the test to check result against non zero.

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/entry.S | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

arch/openrisc/kernel/entry.S +2 -2

index daae2a4..bc65008 100644
@@ -258,9 +258,9 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
 
  #else
 
-	l.mfspr r6,r0,SPR_SR               // SR
+	l.lwz   r6,PT_SR(r3)               // SR
  	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
-	l.sfeqi r6,0x1                     // exception happened in delay slot
+	l.sfne  r6,r0                      // exception happened in delay slot
  	l.bnf   7f
  	 l.lwz  r6,PT_PC(r3)               // address of an offending insn
 

Quoted 8 lines · Stafford Horne

Use execption SR stored in pt_regs for detection, the current SR is not correct as the handler is running after return from exception.

Also, The code that checks for a delay slot uses a flag bitmask and then wants to check if the result is not zero. The test it implemented was wrong.

Correct it by changing the test to check result against non zero.

This wants to be two patches as you are changing two different things.

Quoted 19 lines

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/entry.S | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

arch/openrisc/kernel/entry.S +2 -2

index daae2a4..bc65008 100644
@@ -258,9 +258,9 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
  #else
-	l.mfspr r6,r0,SPR_SR               // SR
+	l.lwz   r6,PT_SR(r3)               // SR
  	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
-	l.sfeqi r6,0x1                     // exception happened in delay slot
+	l.sfne  r6,r0                      // exception happened in delay slot
  	l.bnf   7f
  	 l.lwz  r6,PT_PC(r3)               // address of an offending insn

The strings used during the head/init phase of openrisc bootup were stored in the executable section of the binary.

This causes compilation to fail when using CONFIG_DEBUG_INFO with error:
Error: unaligned opcodes detected in executable segment

Also, this patch removes unused strings.

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/head.S | 12 +-----------
  1 file changed, 1 insertion(+), 11 deletions(-)

arch/openrisc/kernel/head.S +1 -11

index a22f1fc..573e131 100644
@@ -1530,11 +1530,7 @@ ENTRY(_early_uart_init)
  	l.jr	r9
  	l.nop
 
-_string_copying_linux:
-	.string "\n\n\n\n\n\rCopying Linux... \0"
-
-_string_ok_booting:
-	.string "Ok, booting the kernel.\n\r\0"
+	.section .rodata
 
  _string_unhandled_exception:
  	.string "\n\rRunarunaround: Unhandled exception 0x\0"

@@ -1545,12 +1541,6 @@ _string_epc_prefix:
  _string_nl:
  	.string "\n\r\0"
 
-	.global	_string_esr_irq_bug
-_string_esr_irq_bug:
-	.string "\n\rESR external interrupt bug, for details look into entry.S\n\r\0"
-
-
-
  /* ========================================[ page aligned structures ]=== */
 
  /*

Quoted 7 lines · Stafford Horne

The strings used during the head/init phase of openrisc bootup were stored in the executable section of the binary.

This causes compilation to fail when using CONFIG_DEBUG_INFO with error:
Error: unaligned opcodes detected in executable segment

Quoted 1 line

Also, this patch removes unused strings.

This should be two patches: one that removes unused strings and one that switches the data section.

Works like "Also" usually indicate that you are doing too much in your patch and you need to split it up.

Quoted 32 lines

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/head.S | 12 +-----------
  1 file changed, 1 insertion(+), 11 deletions(-)

arch/openrisc/kernel/head.S +1 -11

index a22f1fc..573e131 100644
@@ -1530,11 +1530,7 @@ ENTRY(_early_uart_init)
  	l.jr	r9
  	l.nop
-_string_copying_linux:
-	.string "\n\n\n\n\n\rCopying Linux... \0"
-
-_string_ok_booting:
-	.string "Ok, booting the kernel.\n\r\0"
+	.section .rodata
  _string_unhandled_exception:
  	.string "\n\rRunarunaround: Unhandled exception 0x\0"

@@ -1545,12 +1541,6 @@ _string_epc_prefix:
  _string_nl:
  	.string "\n\r\0"
-	.global	_string_esr_irq_bug
-_string_esr_irq_bug:
-	.string "\n\rESR external interrupt bug, for details look into entry.S\n\r\0"
-
-
-
  /* ========================================[ page aligned structures ]=== */
  /*

From: Valentin Rothberg <[email protected]>

The Kconfig option for OR12000 is OR1K_1200.

Signed-off-by Valentin Rothberg <[email protected]>

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/lib/memcpy.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

arch/openrisc/lib/memcpy.c +1 -1

index 4706f01..669887a 100644
@@ -17,7 +17,7 @@
 
  #include <linux/string.h>
 
-#ifdef CONFIG_OR1200
+#ifdef CONFIG_OR1K_1200
  /*
   * Do memcpy with word copies and loop unrolling. This gives the
   * best performance on the OR1200 and MOR1KX archirectures

Hi Stafford,

Squash this patch into the memcpy patch in order to prevent surprises for anyone doing a git bisection through here.

/Jonas

Quoted 21 lines · Stafford Horne

From: Valentin Rothberg <[email protected]>

The Kconfig option for OR12000 is OR1K_1200.

Signed-off-by Valentin Rothberg <[email protected]>

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/lib/memcpy.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

arch/openrisc/lib/memcpy.c +1 -1

index 4706f01..669887a 100644
@@ -17,7 +17,7 @@
  #include <linux/string.h>
-#ifdef CONFIG_OR1200
+#ifdef CONFIG_OR1K_1200
  /*
   * Do memcpy with word copies and loop unrolling. This gives the
   * best performance on the OR1200 and MOR1KX archirectures

Originally openrisc spec 0 specified that r0 would be wired to ground. This is no longer the case. r0 is not guaranteed to be 0 at init, so we need to initialize it to 0 before using it.

Also, if we are clearing r0 we cant use r0 to clear itself. Change the the CLEAR_GPR macro to use movhi for clearing.

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/head.S | 5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)

arch/openrisc/kernel/head.S +4 -1

index 573e131..e8a1784 100644
@@ -35,7 +35,7 @@
  	l.add	rd,rd,rs
 
  #define CLEAR_GPR(gpr)				\
-	l.or    gpr,r0,r0
+	l.movhi	gpr,0x0
 
  #define LOAD_SYMBOL_2_GPR(gpr,symbol)		\
  	l.movhi gpr,hi(symbol)			;\

@@ -443,6 +443,9 @@ _dispatch_do_ipage_fault:
  	__HEAD
  	.global _start
  _start:
+	/* Init r0 to zero as per spec */
+	CLEAR_GPR(r0)
+
  	/* save kernel parameters */
  	l.or	r25,r0,r3	/* pointer to fdt */
 

Quoted 6 lines · Stafford Horne

Originally openrisc spec 0 specified that r0 would be wired to ground. This is no longer the case. r0 is not guaranteed to be 0 at init, so we need to initialize it to 0 before using it.

Also, if we are clearing r0 we cant use r0 to clear itself. Change the the CLEAR_GPR macro to use movhi for clearing.

Use the Reported-by: tag here since you are taking the time to mention him in the summary mail.

Reported-by Jakob...

Quoted 25 lines

Signed-off-by Stafford Horne <[email protected]>

---
  arch/openrisc/kernel/head.S | 5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)

arch/openrisc/kernel/head.S +4 -1

index 573e131..e8a1784 100644
@@ -35,7 +35,7 @@
  	l.add	rd,rd,rs
  #define CLEAR_GPR(gpr)				\
-	l.or    gpr,r0,r0
+	l.movhi	gpr,0x0
  #define LOAD_SYMBOL_2_GPR(gpr,symbol)		\
  	l.movhi gpr,hi(symbol)			;\

@@ -443,6 +443,9 @@ _dispatch_do_ipage_fault:
  	__HEAD
  	.global _start
  _start:
+	/* Init r0 to zero as per spec */
+	CLEAR_GPR(r0)
+
  	/* save kernel parameters */
  	l.or	r25,r0,r3	/* pointer to fdt */