ARM: dts: omap: workarounds for Ethernet PHY strap on DRA71 and DRA72 EVMs

Hi Tony,

Here are some patches to overcome incorrect Ethernet PHY strap settings on DRA72x EVM Rev C and DRA71 EVM. Both of these boards use TI's DP83867 PHY.

The incorrect PHY strap settings cause a voilation of PHY specification and need to be worked around in software as documented in the commit messages. But there is no known issue that these patches fix.

I did verify that there are no regressions with NFS boot on these boards after the patches are applied on v4.12-rc4.

The series itself has been rebased on your omap-for-v4.13/dt branch since it has some conflicts with patches you have queued.

Sekhar Nori (3):
ARM: dts: dra71-evm: workaround incorrect DP83867 RX_CTRL pin strap
ARM: dts: dra72-evm-revc: workaround incorrect DP83867 RX_CTRL pin
strap
ARM: omap2plus_defconfig: enable DP83867 phy driver

 arch/arm/boot/dts/dra71-evm.dts      | 2 ++
 arch/arm/boot/dts/dra72-evm-revc.dts | 2 ++
 arch/arm/configs/omap2plus_defconfig | 1 +
 3 files changed, 5 insertions(+)

2.9.0

The DRA71 EVM straps the DP83867 GigaBit Ethernet phy's RX_DV/RX_CTRL pin in mode 1. Unfortunately, the phy data manual disallows this.

Add "ti,dp83867-rxctrl-strap-quirk" property to the phy's device-tree node to allow kernel to enable software workaround for this incorrect strap setting. This is as suggested by the phy's datamanual and ensures proper operation of this PHY.

This needs to be done for both instances of this PHY present on the board.

---
 arch/arm/boot/dts/dra71-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

index 570f06e4f71f..c1a7ee09218f 100644
@@ -205,6 +205,7 @@
 		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 		ti,min-output-impedance;
+		ti,dp83867-rxctrl-strap-quirk;
 	};
 
 	dp83867_1: ethernet-phy at 3 {

@@ -213,6 +214,7 @@
 		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 		ti,min-output-impedance;
+		ti,dp83867-rxctrl-strap-quirk;
 	};
 };
 

2.9.0

The DRA72 EVM Rev C straps the DP83867 GigaBit Ethernet phy's RX_DV/RX_CTRL pin in mode 1. Unfortunately, the phy data manual disallows this.

Add "ti,dp83867-rxctrl-strap-quirk" property to the phy's device-tree node to allow kernel to enable software workaround for this incorrect strap setting. This is as suggested by the phy's datamanual and ensures proper operation of this PHY.

This needs to be done for both instances of this PHY present on the board.

---
 arch/arm/boot/dts/dra72-evm-revc.dts | 2 ++
 1 file changed, 2 insertions(+)

index 5532309971ae..9b439851ff79 100644
@@ -80,6 +80,7 @@
 		ti,min-output-impedance;
 		interrupt-parent = <&gpio6>;
 		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+		ti,dp83867-rxctrl-strap-quirk;
 	};
 
 	dp83867_1: ethernet-phy at 3 {

@@ -90,6 +91,7 @@
 		ti,min-output-impedance;
 		interrupt-parent = <&gpio6>;
 		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+		ti,dp83867-rxctrl-strap-quirk;
 	};
 };
 

2.9.0

TI's DP83867 phy is used on DRA72x EVM rev C and DRA71x EVMs. Enable support for it in omap2plus_defconfig.

The driver is built into the kernel to help NFS booting.

---
 arch/arm/configs/omap2plus_defconfig | 1 +
 1 file changed, 1 insertion(+)

index a120ae816260..d4afa2ca2537 100644
@@ -170,6 +170,7 @@ CONFIG_TI_CPTS=y
 # CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_AT803X_PHY=y
 CONFIG_DP83848_PHY=y
+CONFIG_DP83867_PHY=y
 CONFIG_MICREL_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_PPP=m

2.9.0

this can go alone I think.

regards,
-grygorii

Hi Tony,

Please ignore this series. It is prematurely posted. The DT property I use is not upstream yet. I relied on some recollection of it being upstream. I should have grepped instead. Since there was no regression and no change in behavior could also be explained, I did not catch it in my testing. Thanks Grygorii for pointing out.

Regards,
Sekhar