Skip to content Skip to conversation

drm/i915: push more stuff down to encoders on crtc enable/disable

RFC PATCH In review Jani Nikula 3 participants 10 messages Jul 12, 2017 – Jul 18, 2017

Subsystems (2)

DRM drivers Intel i915

Share & tools

Jani Nikula

author

2017-07-12 14:03 UTC #0 lore raw

cover drm/i915: push more stuff down to encoders on crtc enable/disable

Some initial patches for comments and CI. The idea is to move more of the encoder specific stuff from crtc enable/disable paths down to the encoder hooks. Because they're encoder specific. This is the easy start, let's see how it flies.

The commit messages are, uh, a little bit on the terse side. I know. Don't tell me.

BR,
Jani.

Jani Nikula (4):
drm/i915: push DDI CRT underrun reporting on enable to encoder drm/i915: push DDI CRT underrun reporting on disable to encoder drm/i915: push DDI underrun reporting on enable to encoder drm/i915: push DDI FDI link training on enable to CRT encoder

 drivers/gpu/drm/i915/intel_crt.c     | 60 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c     |  8 +++++
 drivers/gpu/drm/i915/intel_display.c | 30 +-----------------
 3 files changed, 69 insertions(+), 29 deletions(-)

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2017-07-12 14:03 UTC #1 lore raw

RFC PATCH 1/4 drm/i915: push DDI CRT underrun reporting on enable to encoder

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_crt.c     | 44 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 16 +------------
 2 files changed, 45 insertions(+), 15 deletions(-)

drivers/gpu/drm/i915/intel_crt.c +44 -0

index 84a1f5e85153..82bd149889ee 100644
@@ -227,11 +227,53 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder,
 	intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 }
 
+static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
+				   struct intel_crtc_state *pipe_config,
+				   struct drm_connector_state *conn_state)
+{
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, false);
+}
+
+static void hsw_pre_enable_crt(struct intel_encoder *encoder,
+			       struct intel_crtc_state *pipe_config,
+			       struct drm_connector_state *conn_state)
+{
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+
+	WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+}
+
 static void intel_enable_crt(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config,
 			     struct drm_connector_state *conn_state)
 {
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+
 	intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
+
+	if (HAS_DDI(dev_priv)) {
+		WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+		intel_wait_for_vblank(dev_priv, pipe);
+		intel_wait_for_vblank(dev_priv, pipe);
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
+						      true);
+	}
 }
 
 static enum drm_mode_status

@@ -907,6 +949,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
 		crt->base.port = PORT_E;
 		crt->base.get_config = hsw_crt_get_config;
 		crt->base.get_hw_state = intel_ddi_get_hw_state;
+		crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
+		crt->base.pre_enable = hsw_pre_enable_crt;
 		crt->base.post_disable = hsw_post_disable_crt;
 	} else {
 		crt->base.port = PORT_NONE;

drivers/gpu/drm/i915/intel_display.c +1 ~~-15~~

index 2144adc5b1d5..02448a86edeb 100644
@@ -5346,10 +5346,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (WARN_ON(intel_crtc->active))
 		return;
 
-	if (intel_crtc->config->has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      false);
-
 	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
 
 	if (intel_crtc->config->shared_dpll)

@@ -5383,9 +5379,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_crtc->active = true;
 
-	if (intel_crtc->config->has_pch_encoder)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-	else
+	if (!intel_crtc->config->has_pch_encoder)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);

@@ -5429,14 +5423,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_encoders_enable(crtc, pipe_config, old_state);
 
-	if (intel_crtc->config->has_pch_encoder) {
-		intel_wait_for_vblank(dev_priv, pipe);
-		intel_wait_for_vblank(dev_priv, pipe);
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      true);
-	}
-
 	/* If we change the relative order between pipe/planes enabling, we need
 	 * to change the workaround. */
 	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Daniel Vetter

Reviewed-by on v1 1/4

2017-07-18 07:59 UTC #2 lore raw

Re: [RFC PATCH 1/4] drm/i915: push DDI CRT underrun reporting on enable to encoder

Quoted 52 lines · Jani Nikula

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_crt.c     | 44 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 16 +------------
 2 files changed, 45 insertions(+), 15 deletions(-)

drivers/gpu/drm/i915/intel_crt.c +33 -0

index 84a1f5e85153..82bd149889ee 100644
@@ -227,11 +227,53 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder,
 	intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 }
 
+static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
+				   struct intel_crtc_state *pipe_config,
+				   struct drm_connector_state *conn_state)
+{
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, false);
+}
+
+static void hsw_pre_enable_crt(struct intel_encoder *encoder,
+			       struct intel_crtc_state *pipe_config,
+			       struct drm_connector_state *conn_state)
+{
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+
+	WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+}
+
 static void intel_enable_crt(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config,
 			     struct drm_connector_state *conn_state)
 {
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+
 	intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
+

drivers/gpu/drm/i915/intel_crt.c static void hsw_post_disable_crt(struct intel_encoder *encoder, · line 277

Quoted 10 lines

drivers/gpu/drm/i915/intel_crt.c +9 -0

+	if (HAS_DDI(dev_priv)) {
+		WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+		intel_wait_for_vblank(dev_priv, pipe);
+		intel_wait_for_vblank(dev_priv, pipe);
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
+						      true);
+	}
 }

Bikeshed, but since we have so many hsw_ special cases already, I'd do one for enable too. Mixing up vfuncs and if conditions are confusing. With that (and a bit more commit message perhaps):

Reviewed-by Daniel Vetter <[email protected]>

Quoted 59 lines

drivers/gpu/drm/i915/intel_crt.c +2 -0

 static enum drm_mode_status

@@ -907,6 +949,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
 		crt->base.port = PORT_E;
 		crt->base.get_config = hsw_crt_get_config;
 		crt->base.get_hw_state = intel_ddi_get_hw_state;
+		crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
+		crt->base.pre_enable = hsw_pre_enable_crt;
 		crt->base.post_disable = hsw_post_disable_crt;
 	} else {
 		crt->base.port = PORT_NONE;

drivers/gpu/drm/i915/intel_display.c +1 ~~-15~~

index 2144adc5b1d5..02448a86edeb 100644
@@ -5346,10 +5346,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (WARN_ON(intel_crtc->active))
 		return;
 
-	if (intel_crtc->config->has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      false);
-
 	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
 
 	if (intel_crtc->config->shared_dpll)

@@ -5383,9 +5379,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_crtc->active = true;
 
-	if (intel_crtc->config->has_pch_encoder)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-	else
+	if (!intel_crtc->config->has_pch_encoder)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);

@@ -5429,14 +5423,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_encoders_enable(crtc, pipe_config, old_state);
 
-	if (intel_crtc->config->has_pch_encoder) {
-		intel_wait_for_vblank(dev_priv, pipe);
-		intel_wait_for_vblank(dev_priv, pipe);
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      true);
-	}
-
 	/* If we change the relative order between pipe/planes enabling, we need
 	 * to change the workaround. */
 	hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 7 lines

Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2017-07-12 14:03 UTC #3 lore raw

RFC PATCH 2/4 drm/i915: push DDI CRT underrun reporting on disable to encoder

In reply to Jani Nikula

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_crt.c     | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  8 --------
 2 files changed, 14 insertions(+), 8 deletions(-)

drivers/gpu/drm/i915/intel_crt.c +14 -0

index 82bd149889ee..c5e5fda91412 100644
@@ -204,6 +204,16 @@ static void pch_disable_crt(struct intel_encoder *encoder,
 			    struct intel_crtc_state *old_crtc_state,
 			    struct drm_connector_state *old_conn_state)
 {
+	struct drm_crtc *crtc = old_crtc_state->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	if (HAS_DDI(dev_priv)) {
+		WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
+						      false);
+	}
 }
 
 static void pch_post_disable_crt(struct intel_encoder *encoder,

@@ -225,6 +235,10 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder,
 	lpt_disable_iclkip(dev_priv);
 
 	intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
+
+	WARN_ON(!old_crtc_state->has_pch_encoder);
+
+	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, true);
 }
 
 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_display.c +0 -8

index 02448a86edeb..ec6391bdd308 100644
@@ -5516,10 +5516,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 
-	if (intel_crtc->config->has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      false);
-
 	intel_encoders_disable(crtc, old_crtc_state, old_state);
 
 	drm_crtc_vblank_off(crtc);

@@ -5544,10 +5540,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 		intel_ddi_disable_pipe_clock(intel_crtc->config);
 
 	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
-
-	if (old_crtc_state->has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      true);
 }
 
 static void i9xx_pfit_enable(struct intel_crtc *crtc)

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Daniel Vetter

Reviewed-by on v1 2/4

2017-07-18 08:00 UTC #4 lore raw

Re: [RFC PATCH 2/4] drm/i915: push DDI CRT underrun reporting on disable to encoder

Quoted 15 lines · Jani Nikula

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_crt.c     | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  8 --------
 2 files changed, 14 insertions(+), 8 deletions(-)

drivers/gpu/drm/i915/intel_crt.c +1 -0

index 82bd149889ee..c5e5fda91412 100644
@@ -204,6 +204,16 @@ static void pch_disable_crt(struct intel_encoder *encoder,
 			    struct intel_crtc_state *old_crtc_state,
 			    struct drm_connector_state *old_conn_state)
 {
+	struct drm_crtc *crtc = old_crtc_state->base.crtc;

drivers/gpu/drm/i915/intel_crt.c static void pch_disable_crt(struct intel_encoder *encoder, · line 217

Quoted 10 lines

drivers/gpu/drm/i915/intel_crt.c +9 -0

+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	if (HAS_DDI(dev_priv)) {
+		WARN_ON(!intel_crtc->config->has_pch_encoder);
+
+		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
+						      false);
+	}
 }

Same comments about just going with hsw_ variants for these, especially when the pch one is empty (nuke that one maybe?). With that:

Reviewed-by Daniel Vetter <[email protected]>

Quoted 46 lines

drivers/gpu/drm/i915/intel_crt.c +4 -0

 static void pch_post_disable_crt(struct intel_encoder *encoder,

@@ -225,6 +235,10 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder,
 	lpt_disable_iclkip(dev_priv);
 
 	intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
+
+	WARN_ON(!old_crtc_state->has_pch_encoder);
+
+	intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, true);
 }
 
 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_display.c +0 -8

index 02448a86edeb..ec6391bdd308 100644
@@ -5516,10 +5516,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 
-	if (intel_crtc->config->has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      false);
-
 	intel_encoders_disable(crtc, old_crtc_state, old_state);
 
 	drm_crtc_vblank_off(crtc);

@@ -5544,10 +5540,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 		intel_ddi_disable_pipe_clock(intel_crtc->config);
 
 	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
-
-	if (old_crtc_state->has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
-						      true);
 }
 
 static void i9xx_pfit_enable(struct intel_crtc *crtc)

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 7 lines

Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2017-07-12 14:04 UTC #5 lore raw

RFC PATCH 3/4 drm/i915: push DDI underrun reporting on enable to encoder

In reply to Jani Nikula

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_ddi.c     | 8 ++++++++
 drivers/gpu/drm/i915/intel_display.c | 5 +----
 2 files changed, 9 insertions(+), 4 deletions(-)

drivers/gpu/drm/i915/intel_ddi.c +8 -0

index efb13582dc73..7c083fe0b622 100644
@@ -2182,8 +2182,16 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config,
 				 struct drm_connector_state *conn_state)
 {
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
 	int type = encoder->type;
 
+	WARN_ON(intel_crtc->config->has_pch_encoder);
+
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+
 	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
 		intel_ddi_pre_enable_dp(encoder,
 					pipe_config->port_clock,

drivers/gpu/drm/i915/intel_display.c +1 -4

index ec6391bdd308..9e074310f161 100644
@@ -5338,7 +5338,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	struct drm_crtc *crtc = pipe_config->base.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
+	int hsw_workaround_pipe;
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 	struct intel_atomic_state *old_intel_state =
 		to_intel_atomic_state(old_state);

@@ -5379,9 +5379,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_crtc->active = true;
 
-	if (!intel_crtc->config->has_pch_encoder)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
 	if (intel_crtc->config->has_pch_encoder)

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Daniel Vetter

2017-07-18 08:02 UTC #6 lore raw

Re: [RFC PATCH 3/4] drm/i915: push DDI underrun reporting on enable to encoder

Quoted 13 lines · Jani Nikula

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_ddi.c     | 8 ++++++++
 drivers/gpu/drm/i915/intel_display.c | 5 +----
 2 files changed, 9 insertions(+), 4 deletions(-)

drivers/gpu/drm/i915/intel_ddi.c +0 -0

index efb13582dc73..7c083fe0b622 100644
@@ -2182,8 +2182,16 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config,
 				 struct drm_connector_state *conn_state)

drivers/gpu/drm/i915/intel_ddi.c static void intel_ddi_pre_enable(struct intel_encoder *encoder, · line 2193

Quoted 10 lines

drivers/gpu/drm/i915/intel_ddi.c +7 -0

 {
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
 	int type = encoder->type;
 
+	WARN_ON(intel_crtc->config->has_pch_encoder);
+
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

Doesn't this miss dsi ports?

Also I'd half expect that once you've pushed all the fdi stuff into the encoder you can again have a unified place where we enable cpu underrun reporting. At least that's my intuition since the fdi stuff is all behind the port, and as soon as the port is up we should be able to enable fifo underruns.
-Daniel

Quoted 34 lines

drivers/gpu/drm/i915/intel_ddi.c +1 -0

+
 	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
 		intel_ddi_pre_enable_dp(encoder,
 					pipe_config->port_clock,

drivers/gpu/drm/i915/intel_display.c +1 -4

index ec6391bdd308..9e074310f161 100644
@@ -5338,7 +5338,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	struct drm_crtc *crtc = pipe_config->base.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
+	int hsw_workaround_pipe;
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 	struct intel_atomic_state *old_intel_state =
 		to_intel_atomic_state(old_state);

@@ -5379,9 +5379,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_crtc->active = true;
 
-	if (!intel_crtc->config->has_pch_encoder)
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
 	if (intel_crtc->config->has_pch_encoder)

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 7 lines

Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2017-07-12 14:04 UTC #7 lore raw

RFC PATCH 4/4 drm/i915: push DDI FDI link training on enable to CRT encoder

In reply to Jani Nikula

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_crt.c     | 2 ++
 drivers/gpu/drm/i915/intel_display.c | 3 ---
 2 files changed, 2 insertions(+), 3 deletions(-)

drivers/gpu/drm/i915/intel_crt.c +2 -0

index c5e5fda91412..5d76fb5c9885 100644
@@ -266,6 +266,8 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 	WARN_ON(!intel_crtc->config->has_pch_encoder);
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+
+	dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
 }
 
 static void intel_enable_crt(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_display.c +0 -3

index 9e074310f161..449a956c779f 100644
@@ -5381,9 +5381,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
-	if (intel_crtc->config->has_pch_encoder)
-		dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
-
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_enable_pipe_clock(pipe_config);

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Daniel Vetter

Reviewed-by on v1 4/4

2017-07-18 08:04 UTC #8 lore raw

Re: [RFC PATCH 4/4] drm/i915: push DDI FDI link training on enable to CRT encoder

Quoted 1 line · Jani Nikula

Signed-off-by Jani Nikula <[email protected]>

Reviewed-by Daniel Vetter <[email protected]>

Quoted 39 lines

---
 drivers/gpu/drm/i915/intel_crt.c     | 2 ++
 drivers/gpu/drm/i915/intel_display.c | 3 ---
 2 files changed, 2 insertions(+), 3 deletions(-)

drivers/gpu/drm/i915/intel_crt.c +2 -0

index c5e5fda91412..5d76fb5c9885 100644
@@ -266,6 +266,8 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 	WARN_ON(!intel_crtc->config->has_pch_encoder);
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+
+	dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
 }
 
 static void intel_enable_crt(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_display.c +0 -3

index 9e074310f161..449a956c779f 100644
@@ -5381,9 +5381,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
-	if (intel_crtc->config->has_pch_encoder)
-		dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
-
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_enable_pipe_clock(pipe_config);

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 7 lines

Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patchwork

CI

2017-07-12 14:22 UTC #9 lore raw

✓ Fi.CI.BAT: success for drm/i915: push more stuff down to encoders on crtc enable/disable

In reply to Jani Nikula

== Series Details ==

== Series Details ==

Series: drm/i915: push more stuff down to encoders on crtc enable/disable
URL : https://patchwork.freedesktop.org/series/27186/
State : success

== Summary ==

Series 27186v1 drm/i915: push more stuff down to encoders on crtc enable/disable
https://patchwork.freedesktop.org/api/1.0/series/27186/revisions/1/mbox/

Test gem_exec_flush:

        Subgroup basic-batch-kernel-default-uc:
                pass       -> FAIL       (fi-snb-2600) fdo#100007
Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-pnv-d510) fdo#101597

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:443s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:429s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:355s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:527s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:508s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:489s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:492s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:600s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:440s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:409s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:419s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:491s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:474s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:450s
fi-kbl-7560u     total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  time:572s
fi-kbl-r         total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  time:582s
fi-pnv-d510      total:279  pass:221  dwarn:3   dfail:0   fail:0   skip:55  time:557s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:452s
fi-skl-6700hq    total:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  time:596s
fi-skl-6700k     total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  time:468s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:481s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:435s
fi-skl-x1585l    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:490s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:547s
fi-snb-2600      total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  time:410s

8ad9e19aafea47c272163c2cbf554e06ff7f9857 drm-tip: 2017y-07m-11d-19h-08m-20s UTC integration manifest 1393ecb drm/i915: push DDI FDI link training on enable to CRT encoder
f111e4b drm/i915: push DDI underrun reporting on enable to encoder
88002e1 drm/i915: push DDI CRT underrun reporting on disable to encoder
354aa71 drm/i915: push DDI CRT underrun reporting on enable to encoder

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5173/
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx