add support for rk3066 platform.

new file mode 100644
index 0000000..be40884
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 2017 Paweł Jarosz <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3066_H
+#define _ASM_ARCH_GRF_RK3066_H
+
+struct rk3066_grf_gpio_lh {
+	u32 l;
+	u32 h;
+};
+
+struct rk3066_grf {
+	struct rk3066_grf_gpio_lh gpio_dir[7];
+	struct rk3066_grf_gpio_lh gpio_do[7];
+	struct rk3066_grf_gpio_lh gpio_en[7];
+
+	u32 gpio0a_iomux;
+	u32 gpio0b_iomux;
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+
+	u32 gpio4a_iomux;
+	u32 gpio4b_iomux;
+	u32 gpio4c_iomux;
+	u32 gpio4d_iomux;
+
+	u32 reserved0[5];
+
+	u32 gpio6b_iomux;
+
+	u32 reserved1[2];
+
+	struct rk3066_grf_gpio_lh gpio_pull[7];
+
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+
+	u32 soc_status0;
+
+	u32 dmac1_con[3];
+	u32 dmac2_con[4];
+
+	u32 uoc0_con[3];
+	u32 uoc1_con[4];
+	u32 ddrc_con;
+	u32 ddrc_stat;
+
+	u32 reserved2[10];
+
+	u32 os_reg[4];
+};
+check_member(rk3066_grf, os_reg[3], 0x01d4);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+	GPIO0A6_SHIFT		= 12,
+	GPIO0A6_MASK		= 1 << GPIO0A6_SHIFT,
+	GPIO0A6_GPIO		= 0,
+	GPIO0A6_HOST_DRV_VBUS,
+
+	GPIO0A5_SHIFT		= 10,
+	GPIO0A5_MASK		= 1 << GPIO0A5_SHIFT,
+	GPIO0A5_GPIO		= 0,
+	GPIO0A5_OTG_DRV_VBUS,
+
+	GPIO0A4_SHIFT		= 8,
+	GPIO0A4_MASK		= 1 << GPIO0A4_SHIFT,
+	GPIO0A4_GPIO		= 0,
+	GPIO0A4_PWM1,
+
+	GPIO0A3_SHIFT		= 6,
+	GPIO0A3_MASK		= 1 << GPIO0A3_SHIFT,
+	GPIO0A3_GPIO		= 0,
+	GPIO0A3_PWM0
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+	GPIO0D7_SHIFT		= 14,
+	GPIO0D7_MASK		= 1 << GPIO0D7_SHIFT,
+	GPIO0D7_GPIO		= 0,
+	GPIO0D7_PWM3,
+
+	GPIO0D6_SHIFT		= 12,
+	GPIO0D6_MASK		= 1 << GPIO0D6_SHIFT,
+	GPIO0D6_GPIO		= 0,
+	GPIO0D6_PWM2
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+	GPIO1A7_SHIFT		= 14,
+	GPIO1A7_MASK		= 3 << GPIO1A7_SHIFT,
+	GPIO1A7_GPIO		= 0,
+	GPIO1A7_UART1_RTS_N,
+	GPIO1A7_SPI0_TXD,
+
+	GPIO1A6_SHIFT		= 12,
+	GPIO1A6_MASK		= 3 << GPIO1A6_SHIFT,
+	GPIO1A6_GPIO		= 0,
+	GPIO1A6_UART1_CTS_N,
+	GPIO1A6_SPI0_RXD,
+
+	GPIO1A5_SHIFT		= 10,
+	GPIO1A5_MASK		= 3 << GPIO1A5_SHIFT,
+	GPIO1A5_GPIO		= 0,
+	GPIO1A5_UART1_SOUT,
+	GPIO1A5_SPI0_CLK,
+
+	GPIO1A4_SHIFT		= 8,
+	GPIO1A4_MASK		= 3 << GPIO1A4_SHIFT,
+	GPIO1A4_GPIO		= 0,
+	GPIO1A4_UART1_SIN,
+	GPIO1A4_SPI0_CSN0,
+
+	GPIO1A3_SHIFT		= 6,
+	GPIO1A3_MASK		= 1 << GPIO1A3_SHIFT,
+	GPIO1A3_GPIO		= 0,
+	GPIO1A3_UART0_RTS_N,
+
+	GPIO1A2_SHIFT		= 4,
+	GPIO1A2_MASK		= 1 << GPIO1A2_SHIFT,
+	GPIO1A2_GPIO		= 0,
+	GPIO1A2_UART0_CTS_N,
+
+	GPIO1A1_SHIFT		= 2,
+	GPIO1A1_MASK		= 1 << GPIO1A1_SHIFT,
+	GPIO1A1_GPIO		= 0,
+	GPIO1A1_UART0_SOUT,
+
+	GPIO1A0_SHIFT		= 0,
+	GPIO1A0_MASK		= 1 << GPIO1A0_SHIFT,
+	GPIO1A0_GPIO		= 0,
+	GPIO1A0_UART0_SIN
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+	GPIO1B1_SHIFT		= 2,
+	GPIO1B1_MASK		= 1 << GPIO1B1_SHIFT,
+	GPIO1B1_GPIO		= 0,
+	GPIO1B1_UART2_SOUT,
+
+	GPIO1B0_SHIFT		= 0,
+	GPIO1B0_MASK		= 1 << GPIO1B0_SHIFT,
+	GPIO1B0_GPIO		= 0,
+	GPIO1B0_UART2_SIN
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+	GPIO2C7_SHIFT		= 14,
+	GPIO2C7_MASK		= 3 << GPIO2C7_SHIFT,
+	GPIO2C7_GPIO		= 0,
+	GPIO2C7_LCDC1_DATA23,
+	GPIO2C7_SPI1_CSN1,
+	GPIO2C7_HSADC_DATA4,
+
+	GPIO2C6_SHIFT		= 12,
+	GPIO2C6_MASK		= 3 << GPIO2C6_SHIFT,
+	GPIO2C6_GPIO		= 0,
+	GPIO2C6_LCDC1_DATA22,
+	GPIO2C6_SPI1_RXD,
+	GPIO2C6_HSADC_DATA3,
+
+	GPIO2C5_SHIFT		= 10,
+	GPIO2C5_MASK		= 3 << GPIO2C5_SHIFT,
+	GPIO2C5_GPIO		= 0,
+	GPIO2C5_LCDC1_DATA21,
+	GPIO2C5_SPI1_TXD,
+	GPIO2C5_HSADC_DATA2,
+
+	GPIO2C4_SHIFT		= 8,
+	GPIO2C4_MASK		= 3 << GPIO2C4_SHIFT,
+	GPIO2C4_GPIO		= 0,
+	GPIO2C4_LCDC1_DATA20,
+	GPIO2C4_SPI1_CSN0,
+	GPIO2C4_HSADC_DATA1,
+
+	GPIO2C3_SHIFT		= 6,
+	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
+	GPIO2C3_GPIO		= 0,
+	GPIO2C3_LCDC1_DATA19,
+	GPIO2C3_SPI1_CLK,
+	GPIO2C3_HSADC_DATA0
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2D7_SHIFT		= 14,
+	GPIO2D7_MASK		= 1 << GPIO2D7_SHIFT,
+	GPIO2D7_GPIO		= 0,
+	GPIO2D7_I2C1_SCL,
+
+	GPIO2D6_SHIFT		= 12,
+	GPIO2D6_MASK		= 1 << GPIO2D6_SHIFT,
+	GPIO2D6_GPIO		= 0,
+	GPIO2D6_I2C1_SDA,
+
+	GPIO2D5_SHIFT		= 10,
+	GPIO2D5_MASK		= 1 << GPIO2D5_SHIFT,
+	GPIO2D5_GPIO		= 0,
+	GPIO2D5_I2C0_SCL,
+
+	GPIO2D4_SHIFT		= 8,
+	GPIO2D4_MASK		= 1 << GPIO2D4_SHIFT,
+	GPIO2D4_GPIO		= 0,
+	GPIO2D4_I2C0_SDA
+
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+	GPIO3A7_SHIFT		= 14,
+	GPIO3A7_MASK		= 1 << GPIO3A7_SHIFT,
+	GPIO3A7_GPIO		= 0,
+	GPIO3A7_SDMMC0_WRITE_PRT,
+
+	GPIO3A6_SHIFT		= 12,
+	GPIO3A6_MASK		= 1 << GPIO3A6_SHIFT,
+	GPIO3A6_GPIO		= 0,
+	GPIO3A6_SDMMC0_RSTN_OUT,
+
+	GPIO3A5_SHIFT		= 10,
+	GPIO3A5_MASK		= 1 << GPIO3A5_SHIFT,
+	GPIO3A5_GPIO		= 0,
+	GPIO3A5_I2C4_SCL,
+
+	GPIO3A4_SHIFT		= 8,
+	GPIO3A4_MASK		= 1 << GPIO3A4_SHIFT,
+	GPIO3A4_GPIO		= 0,
+	GPIO3A4_I2C4_SDA,
+
+	GPIO3A3_SHIFT		= 6,
+	GPIO3A3_MASK		= 1 << GPIO3A3_SHIFT,
+	GPIO3A3_GPIO		= 0,
+	GPIO3A3_I2C3_SCL,
+
+	GPIO3A2_SHIFT		= 4,
+	GPIO3A2_MASK		= 1 << GPIO3A2_SHIFT,
+	GPIO3A2_GPIO		= 0,
+	GPIO3A2_I2C3_SDA,
+
+	GPIO3A1_SHIFT		= 2,
+	GPIO3A1_MASK		= 1 << GPIO3A1_SHIFT,
+	GPIO3A1_GPIO		= 0,
+	GPIO3A1_I2C2_SCL,
+
+	GPIO3A0_SHIFT		= 0,
+	GPIO3A0_MASK		= 1 << GPIO3A0_SHIFT,
+	GPIO3A0_GPIO		= 0,
+	GPIO3A0_I2C2_SDA,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+	GPIO3B7_SHIFT		= 14,
+	GPIO3B7_MASK		= 1 << GPIO3B7_SHIFT,
+	GPIO3B7_GPIO		= 0,
+	GPIO3B7_SDMMC0_WRITE_PRT,
+
+	GPIO3B6_SHIFT		= 12,
+	GPIO3B6_MASK		= 1 << GPIO3B6_SHIFT,
+	GPIO3B6_GPIO		= 0,
+	GPIO3B6_SDMMC0_DETECT_N,
+
+	GPIO3B5_SHIFT		= 10,
+	GPIO3B5_MASK		= 1 << GPIO3B5_SHIFT,
+	GPIO3B5_GPIO		= 0,
+	GPIO3B5_SDMMC0_DATA3,
+
+	GPIO3B4_SHIFT		= 8,
+	GPIO3B4_MASK		= 1 << GPIO3B4_SHIFT,
+	GPIO3B4_GPIO		= 0,
+	GPIO3B4_SDMMC0_DATA2,
+
+	GPIO3B3_SHIFT		= 6,
+	GPIO3B3_MASK		= 1 << GPIO3B3_SHIFT,
+	GPIO3B3_GPIO		= 0,
+	GPIO3B3_SDMMC0_DATA1,
+
+	GPIO3B2_SHIFT		= 4,
+	GPIO3B2_MASK		= 1 << GPIO3B2_SHIFT,
+	GPIO3B2_GPIO		= 0,
+	GPIO3B2_SDMMC0_DATA0,
+
+	GPIO3B1_SHIFT		= 2,
+	GPIO3B1_MASK		= 1 << GPIO3B1_SHIFT,
+	GPIO3B1_GPIO		= 0,
+	GPIO3B1_SDMMC0_CMD,
+
+	GPIO3B0_SHIFT		= 0,
+	GPIO3B0_MASK		= 1 << GPIO3B0_SHIFT,
+	GPIO3B0_GPIO		= 0,
+	GPIO3B0_SDMMC0_CLKOUT
+
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+	GPIO3C7_SHIFT		= 14,
+	GPIO3C7_MASK		= 1 << GPIO3C7_SHIFT,
+	GPIO3C7_GPIO		= 0,
+	GPIO3C7_SDMMC1_WRITE_PRT,
+
+	GPIO3C6_SHIFT		= 12,
+	GPIO3C6_MASK		= 1 << GPIO3C6_SHIFT,
+	GPIO3C6_GPIO		= 0,
+	GPIO3C6_SDMMC1_DETECT_N,
+
+	GPIO3C5_SHIFT		= 10,
+	GPIO3C5_MASK		= 1 << GPIO3C5_SHIFT,
+	GPIO3C5_GPIO		= 0,
+	GPIO3C5_SDMMC1_CLKOUT,
+
+	GPIO3C4_SHIFT		= 8,
+	GPIO3C4_MASK		= 1 << GPIO3C4_SHIFT,
+	GPIO3C4_GPIO		= 0,
+	GPIO3C4_SDMMC1_DATA3,
+
+	GPIO3C3_SHIFT		= 6,
+	GPIO3C3_MASK		= 1 << GPIO3C3_SHIFT,
+	GPIO3C3_GPIO		= 0,
+	GPIO3C3_SDMMC1_DATA2,
+
+	GPIO3C2_SHIFT		= 4,
+	GPIO3C2_MASK		= 1 << GPIO3C2_SHIFT,
+	GPIO3C2_GPIO		= 0,
+	GPIO3C2_SDMMC1_DATA1,
+
+	GPIO3C1_SHIFT		= 2,
+	GPIO3C1_MASK		= 1 << GPIO3C1_SHIFT,
+	GPIO3C1_GPIO		= 0,
+	GPIO3C1_SDMMC1_DATA0,
+
+	GPIO3C0_SHIFT		= 0,
+	GPIO3C0_MASK		= 1 << GPIO3C0_SHIFT,
+	GPIO3C0_GPIO		= 0,
+	GPIO3C0_SMMC1_CMD
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+	GPIO3D7_SHIFT		= 14,
+	GPIO3D7_MASK		= 3 << GPIO3D7_SHIFT,
+	GPIO3D7_GPIO		= 0,
+	GPIO3D7_FLASH_DQS,
+	GPIO3D7_EMMC_CLKOUT,
+
+	GPIO3D6_SHIFT		= 12,
+	GPIO3D6_MASK		= 1 << GPIO3D6_SHIFT,
+	GPIO3D6_GPIO		= 0,
+	GPIO3D6_UART3_RTS_N,
+
+	GPIO3D5_SHIFT		= 10,
+	GPIO3D5_MASK		= 1 << GPIO3D5_SHIFT,
+	GPIO3D5_GPIO		= 0,
+	GPIO3D5_UART3_CTS_N,
+
+	GPIO3D4_SHIFT		= 8,
+	GPIO3D4_MASK		= 1 << GPIO3D4_SHIFT,
+	GPIO3D4_GPIO		= 0,
+	GPIO3D4_UART3_SOUT,
+
+	GPIO3D3_SHIFT		= 6,
+	GPIO3D3_MASK		= 1 << GPIO3D3_SHIFT,
+	GPIO3D3_GPIO		= 0,
+	GPIO3D3_UART3_SIN,
+
+	GPIO3D2_SHIFT		= 4,
+	GPIO3D2_MASK		= 1 << GPIO3D2_SHIFT,
+	GPIO3D2_GPIO		= 0,
+	GPIO3D2_SDMMC1_INT_N,
+
+	GPIO3D1_SHIFT		= 2,
+	GPIO3D1_MASK		= 1 << GPIO3D1_SHIFT,
+	GPIO3D1_GPIO		= 0,
+	GPIO3D1_SDMMC1_BACKEND_PWR,
+
+	GPIO3D0_SHIFT		= 0,
+	GPIO3D0_MASK		= 1 << GPIO3D0_SHIFT,
+	GPIO3D0_GPIO		= 0,
+	GPIO3D0_SDMMC1_PWR_EN
+
+};
+
+/* GRF_GPIO4A_IOMUX */
+enum {
+	GPIO4A7_SHIFT		= 14,
+	GPIO4A7_MASK		= 1 << GPIO4A7_SHIFT,
+	GPIO4A7_GPIO		= 0,
+	GPIO4A7_FLASH_DATA15,
+
+	GPIO4A6_SHIFT		= 12,
+	GPIO4A6_MASK		= 1 << GPIO4A6_SHIFT,
+	GPIO4A6_GPIO		= 0,
+	GPIO4A6_FLASH_DATA14,
+
+	GPIO4A5_SHIFT		= 10,
+	GPIO4A5_MASK		= 1 << GPIO4A5_SHIFT,
+	GPIO4A5_GPIO		= 0,
+	GPIO4A5_FLASH_DATA13,
+
+	GPIO4A4_SHIFT		= 8,
+	GPIO4A4_MASK		= 1 << GPIO4A4_SHIFT,
+	GPIO4A4_GPIO		= 0,
+	GPIO4A4_FLASH_DATA12,
+
+	GPIO4A3_SHIFT		= 6,
+	GPIO4A3_MASK		= 1 << GPIO4A3_SHIFT,
+	GPIO4A3_GPIO		= 0,
+	GPIO4A3_FLASH_DATA11,
+
+	GPIO4A2_SHIFT		= 4,
+	GPIO4A2_MASK		= 1 << GPIO4A2_SHIFT,
+	GPIO4A2_GPIO		= 0,
+	GPIO4A2_FLASH_DATA10,
+
+	GPIO4A1_SHIFT		= 2,
+	GPIO4A1_MASK		= 1 << GPIO4A1_SHIFT,
+	GPIO4A1_GPIO		= 0,
+	GPIO4A1_FLASH_DATA9,
+
+	GPIO4A0_SHIFT		= 0,
+	GPIO4A0_MASK		= 1 << GPIO4A0_SHIFT,
+	GPIO4A0_GPIO		= 0,
+	GPIO4A0_FLASH_DATA8
+
+};
+
+/* GRF_GPIO4B_IOMUX */
+enum {
+	GPIO4B7_SHIFT		= 14,
+	GPIO4B7_MASK		= 1 << GPIO4B7_SHIFT,
+	GPIO4B7_GPIO		= 0,
+	GPIO4B7_SPI0_CSN1,
+
+	GPIO4B6_SHIFT		= 12,
+	GPIO4B6_MASK		= 1 << GPIO4B6_SHIFT,
+	GPIO4B6_GPIO		= 0,
+	GPIO4B6_FLASH_CSN7,
+
+	GPIO4B5_SHIFT		= 10,
+	GPIO4B5_MASK		= 1 << GPIO4B5_SHIFT,
+	GPIO4B5_GPIO		= 0,
+	GPIO4B5_FLASH_CSN6,
+
+	GPIO4B4_SHIFT		= 8,
+	GPIO4B4_MASK		= 1 << GPIO4B4_SHIFT,
+	GPIO4B4_GPIO		= 0,
+	GPIO4B4_FLASH_CSN5,
+
+	GPIO4B3_SHIFT		= 6,
+	GPIO4B3_MASK		= 1 << GPIO4B3_SHIFT,
+	GPIO4B3_GPIO		= 0,
+	GPIO4B3_FLASH_CSN4,
+
+	GPIO4B2_SHIFT		= 4,
+	GPIO4B2_MASK		= 3 << GPIO4B2_SHIFT,
+	GPIO4B2_GPIO		= 0,
+	GPIO4B2_FLASH_CSN3,
+	GPIO4B2_EMMC_RSTN_OUT,
+
+	GPIO4B1_SHIFT		= 2,
+	GPIO4B1_MASK		= 3 << GPIO4B1_SHIFT,
+	GPIO4B1_GPIO		= 0,
+	GPIO4B1_FLASH_CSN2,
+	GPIO4B1_EMMC_CMD,
+
+	GPIO4B0_SHIFT		= 0,
+	GPIO4B0_MASK		= 1 << GPIO4B0_SHIFT,
+	GPIO4B0_GPIO		= 0,
+	GPIO4B0_FLASH_CSN1
+};
+
+/* GRF_SOC_CON0 */
+enum {
+	SMC_MUX_CON_SHIFT	= 13,
+	SMC_MUX_CON_MASK	= 1 << SMC_MUX_CON_SHIFT,
+
+	NOC_REMAP_SHIFT		= 12,
+	NOC_REMAP_MASK		= 1 << NOC_REMAP_SHIFT,
+
+	EMMC_FLASH_SEL_SHIFT	= 11,
+	EMMC_FLASH_SEL_MASK	= 1 << EMMC_FLASH_SEL_SHIFT,
+
+	TZPC_REVISION_SHIFT	= 7,
+	TZPC_REVISION_MASK	= 0xf << TZPC_REVISION_SHIFT,
+
+	L2CACHE_ACC_SHIFT	= 5,
+	L2CACHE_ACC_MASK	= 3 << L2CACHE_ACC_SHIFT,
+
+	L2RD_WAIT_SHIFT		= 3,
+	L2RD_WAIT_MASK		= 3 << L2RD_WAIT_SHIFT,
+
+	IMEMRD_WAIT_SHIFT	= 1,
+	IMEMRD_WAIT_MASK	= 3 << IMEMRD_WAIT_SHIFT,
+	
+	SOC_REMAP_SHIFT		= 0,
+	SOC_REMAP_MASK		= 1 << SOC_REMAP_SHIFT,
+};
+
+/* GRF_SOC_CON1 */
+enum {
+	RKI2C4_SEL_SHIFT	= 15,
+	RKI2C4_SEL_MASK		= 1 << RKI2C4_SEL_SHIFT,
+
+	RKI2C3_SEL_SHIFT	= 14,
+	RKI2C3_SEL_MASK		= 1 << RKI2C3_SEL_SHIFT,
+
+	RKI2C2_SEL_SHIFT	= 13,
+	RKI2C2_SEL_MASK		= 1 << RKI2C2_SEL_SHIFT,
+
+	RKI2C1_SEL_SHIFT	= 12,
+	RKI2C1_SEL_MASK		= 1 << RKI2C1_SEL_SHIFT,
+
+	RKI2C0_SEL_SHIFT	= 11,
+	RKI2C0_SEL_MASK		= 1 << RKI2C0_SEL_SHIFT,
+
+	VCODEC_SEL_SHIFT	= 10,
+	VCODEC_SEL_MASK		= 1 << VCODEC_SEL_SHIFT,
+
+	PERI_EMEM_PAUSE_SHIFT	= 9,
+	PERI_EMEM_PAUSE_MASK	= 1 << PERI_EMEM_PAUSE_SHIFT,
+
+	PERI_USB_PAUSE_SHIFT	= 8,
+	PERI_USB_PAUSE_MASK	= 1 << PERI_USB_PAUSE_SHIFT,
+
+	SMC_MUX_MODE_0_SHIFT	= 6,
+	SMC_MUX_MODE_0_MASK	= 1 << SMC_MUX_MODE_0_SHIFT,
+
+	SMC_SRAM_MW_0_SHIFT	= 4,
+	SMC_SRAM_MW_0_MASK	= 3 << SMC_SRAM_MW_0_SHIFT,
+
+	SMC_REMAP_0_SHIFT	= 3,
+	SMC_REMAP_0_MASK	= 1 << SMC_REMAP_0_SHIFT,
+
+	SMC_A_GT_M0_SYNC_SHIFT	= 2,
+	SMC_A_GT_M0_SYNC_MASK	= 1 << SMC_A_GT_M0_SYNC_SHIFT,
+
+	EMAC_SPEED_SHIFT	= 1,
+	EMAC_SPEEC_MASK		= 1 << EMAC_SPEED_SHIFT,
+
+	EMAC_MODE_SHIFT		= 0,
+	EMAC_MODE_MASK		= 1 << EMAC_MODE_SHIFT,
+};
+
+/* GRF_SOC_CON2 */
+enum {
+
+	MSCH4_MAINDDR3_SHIFT	= 7,
+	MSCH4_MAINDDR3_MASK	= 1 << MSCH4_MAINDDR3_SHIFT,
+	MSCH4_MAINDDR3_DDR3	= 1,
+
+	EMAC_NEWRCV_EN_SHIFT	= 6,
+	EMAC_NEWRCV_EN_MASK	= 1 << EMAC_NEWRCV_EN_SHIFT,
+
+	SW_ADDR15_EN_SHIFT	= 5,
+	SW_ADDR15_EN_MASK	= 1 << SW_ADDR15_EN_SHIFT,
+
+	SW_ADDR16_EN_SHIFT	= 4,
+	SW_ADDR16_EN_MASK	= 1 << SW_ADDR16_EN_SHIFT,
+
+	SW_ADDR17_EN_SHIFT	= 3,
+	SW_ADDR17_EN_MASK	= 1 << SW_ADDR17_EN_SHIFT,
+
+	BANK2_TO_RANK_EN_SHIFT	= 2,
+	BANK2_TO_RANK_EN_MASK	= 1 << BANK2_TO_RANK_EN_SHIFT,
+
+	RANK_TO_ROW15_EN_SHIFT	= 1,
+	RANK_TO_ROW15_EN_MASK	= 1 << RANK_TO_ROW15_EN_SHIFT,
+
+	UPCTL_C_ACTIVE_IN_SHIFT = 0,
+	UPCTL_C_ACTIVE_IN_MASK	= 1 << UPCTL_C_ACTIVE_IN_SHIFT,
+	UPCTL_C_ACTIVE_IN_MAY	= 0,
+	UPCTL_C_ACTIVE_IN_WILL,
+};
+
+/* GRF_DDRC_CON0 */
+enum {
+	DTO_LB_SHIFT		= 11,
+	DTO_LB_MASK		= 3 << DTO_LB_SHIFT,
+
+	DTO_TE_SHIFT		= 9,
+	DTO_TE_MASK		= 3 << DTO_TE_SHIFT,
+
+	DTO_PDR_SHIFT		= 7,
+	DTO_PDR_MASK		= 3 << DTO_PDR_SHIFT,
+
+	DTO_PDD_SHIFT		= 5,
+	DTO_PDD_MASK		= 3 << DTO_PDD_SHIFT,
+
+	DTO_IOM_SHIFT		= 3,
+	DTO_IOM_MASK		= 3 << DTO_IOM_SHIFT,
+
+	DTO_OE_SHIFT		= 1,
+	DTO_OE_MASK		= 3 << DTO_OE_SHIFT,
+
+	ATO_AE_SHIFT		= 0,
+	ATO_AE_MASK		= 1 << ATO_AE_SHIFT,
+};
+#endif

index 9f4bc2e..6c8c77d 100644
@@ -43,6 +43,7 @@ enum periph_id {
 	PERIPH_ID_HDMI,
 	PERIPH_ID_GMAC,
 	PERIPH_ID_SFC,
+	PERIPH_ID_NAND,
 
 	PERIPH_ID_COUNT,
 

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new file mode 100644
index 0000000..c4a6951
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2016 Heiko Stuebner <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3066_H
+#define _ASM_ARCH_CRU_RK3066_H
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(1416 * 1000000)
+#define APLL_SAFE_HZ	(600 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+#define CPLL_HZ		(384 * 1000000)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ	297000000
+#define CPU_HCLK_HZ	148500000
+#define CPU_PCLK_HZ	74250000
+#define CPU_H2P_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3066_clk_priv {
+	struct rk3066_grf *grf;
+	struct rk3066_cru *cru;
+	ulong rate;
+	bool has_bwadj;
+};
+
+struct rk3066_cru {
+	struct rk3066_pll {
+		u32 con0;
+		u32 con1;
+		u32 con2;
+		u32 con3;
+	} pll[4];
+	u32 cru_mode_con;
+	u32 cru_clksel_con[35];
+	u32 cru_clkgate_con[10];
+	u32 reserved1[2];
+	u32 cru_glb_srst_fst_value;
+	u32 cru_glb_srst_snd_value;
+	u32 reserved2[2];
+	u32 cru_softrst_con[9];
+	u32 cru_misc_con;
+	u32 reserved3[2];
+	u32 cru_glb_cnt_th;
+};
+check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+	/* a9_core_div: core = core_src / (a9_core_div + 1) */
+	A9_CORE_DIV_SHIFT	= 9,
+	A9_CORE_DIV_MASK	= 0x1f << A9_CORE_DIV_SHIFT,
+	CORE_PLL_SHIFT		= 8,
+	CORE_PLL_MASK		= 1 << CORE_PLL_SHIFT,
+	CORE_PLL_SELECT_APLL	= 0,
+	CORE_PLL_SELECT_GPLL,
+
+	/* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
+	CORE_PERI_DIV_SHIFT	= 6,
+	CORE_PERI_DIV_MASK	= 3 << CORE_PERI_DIV_SHIFT,
+
+	/* aclk_cpu pll selection */
+	CPU_ACLK_PLL_SHIFT	= 5,
+	CPU_ACLK_PLL_MASK	= 1 << CPU_ACLK_PLL_SHIFT,
+	CPU_ACLK_PLL_SELECT_APLL	= 0,
+	CPU_ACLK_PLL_SELECT_GPLL,
+
+	/* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
+	A9_CPU_DIV_SHIFT	= 0,
+	A9_CPU_DIV_MASK		= 0x1f << A9_CPU_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+	/* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
+	AHB2APB_DIV_SHIFT	= 14,
+	AHB2APB_DIV_MASK	= 3 << AHB2APB_DIV_SHIFT,
+
+	/* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
+	CPU_PCLK_DIV_SHIFT	= 12,
+	CPU_PCLK_DIV_MASK	= 3 << CPU_PCLK_DIV_SHIFT,
+
+	/* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
+	CPU_HCLK_DIV_SHIFT	= 8,
+	CPU_HCLK_DIV_MASK	= 3 << CPU_HCLK_DIV_SHIFT,
+
+	/* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
+	CORE_ACLK_DIV_SHIFT	= 3,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+	PERI_SEL_PLL_SHIFT	= 15,
+	PERI_SEL_PLL_MASK	= 1 << PERI_SEL_PLL_SHIFT,
+	PERI_SEL_CPLL		= 0,
+	PERI_SEL_GPLL,
+
+	/* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
+
+	/* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+
+	/* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+};
+/* CRU_CLKSEL11_CON */
+enum {
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+	UART_PLL_SHIFT		= 15,
+	UART_PLL_MASK		= 1 << UART_PLL_SHIFT,
+	UART_PLL_SELECT_GENERAL	= 0,
+	UART_PLL_SELECT_CODEC,
+
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
+
+	SDIO_DIV_SHIFT		= 0,
+	SDIO_DIV_MASK		= 0x3f << SDIO_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+	SPI1_DIV_SHIFT		= 8,
+	SPI1_DIV_MASK		= 0x7f << SPI1_DIV_SHIFT,
+
+	SPI0_DIV_SHIFT		= 0,
+	SPI0_DIV_MASK		= 0x7f << SPI0_DIV_SHIFT,
+};
+
+/* CRU_MODE_CON */
+enum {
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORMAL,
+	GPLL_MODE_DEEP,
+
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 3 << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORMAL,
+	CPLL_MODE_DEEP,
+
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 3 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORMAL,
+	DPLL_MODE_DEEP,
+
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 3 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORMAL,
+	APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+	CLKR_SHIFT		= 8,
+	CLKR_MASK		= 0x3f << CLKR_SHIFT,
+
+	CLKOD_SHIFT		= 0,
+	CLKOD_MASK		= 0x3f << CLKOD_SHIFT,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+	CLKF_SHIFT		= 0,
+	CLKF_MASK		= 0x1fff << CLKF_SHIFT,
+};
+
+#endif

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new file mode 100644
index 0000000..ae52902
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3066_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}

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new file mode 100644
index 0000000..e5d66fe
@@ -0,0 +1,10 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+

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index d36f900..7bd9f7d 100644
@@ -58,6 +58,9 @@ struct nand_flash_dev nand_flash_ids[] = {
 	{"TC58NVG6D2 64G 3.3V 8-bit",
 		{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
 		  SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
+	{"SDTNQGAMA 64G 3.3V 8-bit",
+		{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x57} },
+		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
 	{"SDTNRGAMA 64G 3.3V 8-bit",
 		{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
 		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },

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index 4a0947c..0e68788 100644
@@ -157,6 +157,7 @@ enum fdt_compat_id {
 	COMPAT_ALTERA_SOCFPGA_F2SDR0,           /* SoCFPGA fpga2SDRAM0 bridge */
 	COMPAT_ALTERA_SOCFPGA_F2SDR1,           /* SoCFPGA fpga2SDRAM1 bridge */
 	COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
+	COMPAT_ROCKCHIP_NANDC,			/* Rockchip NAND controller */
 
 	COMPAT_COUNT,
 };

index 107a892..4a8a8d7 100644
@@ -70,6 +70,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
 	COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
 	COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
+	COMPAT(ROCKCHIP_NANDC, "rockchip,nandc"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)

index a058eb8..f5f6cd2 100644
@@ -167,6 +167,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_FPGA,       "fpga",       "FPGA Image" },
 	{       IH_TYPE_TEE,        "tee",        "Trusted Execution Environment Image",},
 	{	IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
+	{	IH_TYPE_RKNAND,     "rknand",     "Rockchip NAND Boot Image" },
 	{	-1,		    "",		  "",			},
 };
 

index 1f4bfda..10ff094 100644
@@ -269,6 +269,7 @@ enum {
 	IH_TYPE_VYBRIDIMAGE,	/* VYBRID .vyb Image */
 	IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
 	IH_TYPE_FIRMWARE_IVT,		/* Firmware Image with HABv4 IVT */
+	IH_TYPE_RKNAND,			/* Rockchip NAND Boot Image	*/
 
 	IH_TYPE_COUNT,			/* Number of image types */
 };

index a8d5054..0b2a707 100644
@@ -77,6 +77,7 @@ struct image_tool_params {
 	bool quiet;		/* Don't output text in normal operation */
 	unsigned int external_offset;	/* Add padding to external data */
 	const char *engine_id;	/* Engine to use for signing */
+	char *extraparams;	/* Extra parameters for img creation (-X) */
 };
 
 /*

index 28ff35e..ffc91d2 100644
@@ -144,7 +144,7 @@ static void process_args(int argc, char **argv)
 	int opt;
 
 	while ((opt = getopt(argc, argv,
-			     "a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:N:p:O:rR:qsT:vVx")) != -1) {
+			     "a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:N:p:O:rR:qsT:vVxX:")) != -1) {
 		switch (opt) {
 		case 'a':
 			params.addr = strtoull(optarg, &ptr, 16);

@@ -279,6 +279,9 @@ static void process_args(int argc, char **argv)
 		case 'x':
 			params.xflag++;
 			break;
+		case 'X':
+			params.extraparams = optarg;
+			break;
 		default:
 			usage("Invalid option");
 		}

@@ -416,7 +419,8 @@ int main(int argc, char **argv)
 		exit (retval);
 	}
 
-	if ((params.type != IH_TYPE_MULTI) && (params.type != IH_TYPE_SCRIPT)) {
+	if ((params.type != IH_TYPE_MULTI) && (params.type != IH_TYPE_SCRIPT) &&
+	    (params.type != IH_TYPE_RKNAND)) {
 		dfd = open(params.datafile, O_RDONLY | O_BINARY);
 		if (dfd < 0) {
 			fprintf(stderr, "%s: Can't open %s: %s\n",

index 04e8272..a2f2160 100644
@@ -73,6 +73,7 @@ struct spl_info {
 
 static struct spl_info spl_infos[] = {
 	{ "rk3036", "RK30", 0x1000, false, false },
+	{ "rk3066", "RK30", 0x8000, true, false },
 	{ "rk3188", "RK31", 0x8000 - 0x800, true, false },
 	{ "rk322x", "RK32", 0x8000 - 0x1000, false, false },
 	{ "rk3288", "RK32", 0x8000, false, false },

@@ -167,7 +168,7 @@ bool rkcommon_spl_is_boot0(struct image_tool_params *params)
 	return info->spl_boot0;
 }
 
-static void rkcommon_set_header0(void *buf, uint file_size,
+static void rkcommon_set_header0(void *buf, uint file_size, uint max_size,
 				 struct image_tool_params *params)
 {
 	struct header0_info *hdr = buf;

@@ -194,12 +195,13 @@ static void rkcommon_set_header0(void *buf, uint file_size,
 	 * see https://lists.denx.de/pipermail/u-boot/2017-May/293267.html
 	 * for a more detailed explanation by Andy Yan
 	 */
-	hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE;
+	hdr->init_boot_size = hdr->init_size + DIV_ROUND_UP(max_size, RK_BLK_SIZE);
+	hdr->init_boot_size = ROUND(hdr->init_boot_size, 4);
 
 	rc4_encode(buf, RK_BLK_SIZE, rc4_key);
 }
 
-int rkcommon_set_header(void *buf, uint file_size,
+int rkcommon_set_header(void *buf, uint file_size, uint max_size,
 			struct image_tool_params *params)
 {
 	struct header1_info *hdr = buf + RK_SPL_HDR_START;

@@ -207,7 +209,7 @@ int rkcommon_set_header(void *buf, uint file_size,
 	if (file_size > rkcommon_get_spl_size(params))
 		return -ENOSPC;
 
-	rkcommon_set_header0(buf, file_size, params);
+	rkcommon_set_header0(buf, file_size, max_size, params);
 
 	/* Set up the SPL name (i.e. copy spl_hdr over) */
 	memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);

index 8790f1c..cd357c7 100644
@@ -45,6 +45,14 @@ const char *rkcommon_get_spl_hdr(struct image_tool_params *params);
 int rkcommon_get_spl_size(struct image_tool_params *params);
 
 /**
+ * rkcommon_spl_is_boot0() - is magic included in spl
+ *
+ * Returns true if magic (for example RK30) is included in spl
+ */
+
+bool rkcommon_spl_is_boot0(struct image_tool_params *params);
+
+/**
  * rkcommon_set_header() - set up the header for a Rockchip boot image
  *
  * This sets up a 2KB header which can be interpreted by the Rockchip boot ROM.

@@ -53,7 +61,7 @@ int rkcommon_get_spl_size(struct image_tool_params *params);
  * @file_size:	Size of the file we want the boot ROM to load, in bytes
  * @return 0 if OK, -ENOSPC if too large
  */
-int rkcommon_set_header(void *buf, uint file_size,
+int rkcommon_set_header(void *buf, uint file_size, uint max_size,
 			struct image_tool_params *params);
 
 /**

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index c56153d..164c1fb 100644
@@ -26,7 +26,7 @@ static void rksd_set_header(void *buf,  struct stat *sbuf,  int ifd,
 	 * header).
 	 */
 	size = params->file_size - RK_SPL_HDR_START;
-	ret = rkcommon_set_header(buf, size, params);
+	ret = rkcommon_set_header(buf, size, RK_MAX_BOOT_SIZE, params);
 	if (ret) {
 		/* TODO(sjg at chromium.org): This method should return an error */
 		printf("Warning: SPL image is too large (size %#x) and will "

index 4332ce1..5005051 100644
@@ -25,7 +25,7 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd,
 	int ret;
 
 	size = params->orig_file_size;
-	ret = rkcommon_set_header(buf, size, params);
+	ret = rkcommon_set_header(buf, size, RK_MAX_BOOT_SIZE, params);
 	debug("size %x\n", size);
 	if (ret) {
 		/* TODO(sjg at chromium.org): This method should return an error */

index 8fa06a2..2b96eb2 100644
@@ -90,55 +90,17 @@ static struct dwc2_plat_otg_data rk3066_otg_data = {
 
 int board_usb_init(int index, enum usb_init_type init)
 {
-	int node, phy_node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-	u32 grf_phy_offset;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3066-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3066-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+	ofnode otg_node;
+	u32 reg;
 
-	node = fdtdec_lookup_phandle(blob, node, "phys");
-	if (node <= 0) {
-		debug("Not found usb phy device\n");
+	otg_node = ofnode_path("/usb@10180000");
+	if (!ofnode_valid(otg_node)) {
+		debug("Not found usb otg device\n");
 		return -ENODEV;
 	}
 
-	phy_node = fdt_parent_offset(blob, node);
-	if (phy_node <= 0) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	rk3066_otg_data.phy_of_node = phy_node;
-	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3066-grf");
-	if (node <= 0) {
-		debug("Not found grf device\n");
-		return -ENODEV;
-	}
-	rk3066_otg_data.regs_phy = grf_phy_offset +
-				fdtdec_get_addr(blob, node, "reg");
+	ofnode_read_u32(otg_node, "reg", &reg);
+	rk3066_otg_data.regs_otg = reg;
 
 	return dwc2_udc_probe(&rk3066_otg_data);
 }

index 700f764..2cc4d67 100644
@@ -428,6 +428,7 @@ static int dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
 	struct dwmci_host *host = mmc->priv;
+	uint32_t use_dma;
 
 	if (host->board_init)
 		host->board_init(host);

@@ -439,6 +440,13 @@ static int dwmci_init(struct mmc *mmc)
 		return -EIO;
 	}
 
+	use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON));
+	if (use_dma == DMA_INTERFACE_IDMA) {
+		host->fifo_mode = 0;
+	} else {
+		host->fifo_mode = 1;
+	}
+
 	/* Enumerate at 400KHz */
 	dwmci_setup_bus(host, mmc->cfg->f_min);
 

index 4dda009..269536d 100644
@@ -115,6 +115,10 @@
 #define RX_WMARK_SHIFT		16
 #define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)
 
+/* HCON Register */
+#define DMA_INTERFACE_IDMA		(0x0)
+#define SDMMC_GET_TRANS_MODE(x)		(((x)>>16) & 0x3)
+
 #define DWMCI_IDMAC_OWN		(1 << 31)
 #define DWMCI_IDMAC_CH		(1 << 4)
 #define DWMCI_IDMAC_FS		(1 << 3)

index e7fcf89..a879fcd 100644
@@ -160,6 +160,7 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
 
 static const struct udevice_id rockchip_dwmmc_ids[] = {
 	{ .compatible = "rockchip,rk3288-dw-mshc" },
+	{ .compatible = "rockchip,rk2928-dw-mshc" },
 	{ }
 };
 

index 72d264b..4179448 100644
@@ -5,6 +5,19 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
+	ldr	r3, =0x10080900
+	ldr	r0, [r3]
+	cmp	r0, #1
+	movne	r0, #1
+	strne	r0, [r3]
+	beq	out_of_bootrom
+	bx	lr
+out_of_bootrom:
+	mov	r0, #0
+	str	r0, [r3]
+#endif
+
 /*
  * Execution starts on the instruction following this 4-byte header
  * (containing the magic 'RK33').

@@ -26,6 +39,7 @@
 	 */
 	b reset	 /* may be overwritten --- should be 'nop' or a 'b reset' */
 #endif
+
 	b reset
 
 #if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)

new file mode 100644
index 0000000..c7e1fc0
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_SYSRESET_COMMON_H
+#define _ASM_ARCH_SYSRESET_COMMON_H
+
+struct rockchip_sysreset_data {
+	void *grf_soc_con0;
+	uint32_t noc_remap_mask;
+	void *cru_mode_con;
+	void *cru_glb_srst_snd_value;
+	void *cru_glb_srst_fst_value;
+};
+
+int rockchip_sysreset_request(struct rockchip_sysreset_data *data,
+			      enum sysreset_t type);
+#endif

new file mode 100644
index 0000000..41e76e3
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysreset_common.h>
+#include <linux/err.h>
+
+int rockchip_sysreset_request(struct rockchip_sysreset_data *data,
+			      enum sysreset_t type)
+{
+	switch (type) {
+	case SYSRESET_WARM:
+		/*
+		 * warm-reset keeps the remap value,
+		 * so make sure it's disabled.
+		 */
+		rk_clrsetreg(data->grf_soc_con0,
+			data->noc_remap_mask, 0);
+
+		rk_clrreg(data->cru_mode_con, 0xffff);
+		writel(0xeca8, data->cru_glb_srst_snd_value);
+		break;
+	case SYSRESET_COLD:
+		rk_clrreg(data->cru_mode_con, 0xffff);
+		writel(0xfdb9, data->cru_glb_srst_fst_value);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	return -EINPROGRESS;
+}

index b5dcb9a..f82b3dd 100644
@@ -14,40 +14,28 @@
 #include <asm/arch/cru_rk3066.h>
 #include <asm/arch/grf_rk3066.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sysreset_common.h>
 #include <linux/err.h>
 
 int rk3066_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	struct rk3066_cru *cru = rockchip_get_cru();
-	struct rk3066_grf *grf;
+	struct rk3066_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rockchip_sysreset_data data = {
+			.grf_soc_con0 = &grf->soc_con0,
+			.noc_remap_mask = NOC_REMAP_MASK,
+			.cru_mode_con = &cru->cru_mode_con,
+			.cru_glb_srst_snd_value = &cru->cru_glb_srst_snd_value,
+			.cru_glb_srst_fst_value = &cru->cru_glb_srst_fst_value
+	};
 
 	if (IS_ERR(cru))
 		return PTR_ERR(cru);
 
-	switch (type) {
-	case SYSRESET_WARM:
-		grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-		if (IS_ERR(grf))
-			return -EPROTONOSUPPORT;
-		/*
-		 * warm-reset keeps the remap value,
-		 * so make sure it's disabled.
-		 */
-		rk_clrsetreg(&grf->soc_con0,
-			NOC_REMAP_MASK, 0 << NOC_REMAP_SHIFT);
-
-		rk_clrreg(&cru->cru_mode_con, 0xffff);
-		writel(0xeca8, &cru->cru_glb_srst_snd_value);
-		break;
-	case SYSRESET_COLD:
-		rk_clrreg(&cru->cru_mode_con, 0xffff);
-		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
-		break;
-	default:
+	if (IS_ERR(grf))
 		return -EPROTONOSUPPORT;
-	}
 
-	return -EINPROGRESS;
+	return rockchip_sysreset_request(&data, type);
 }
 
 static struct sysreset_ops rk3066_sysreset = {

index 053a634..e924a02 100644
@@ -14,41 +14,28 @@
 #include <asm/arch/cru_rk3188.h>
 #include <asm/arch/grf_rk3188.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sysreset_common.h>
 #include <linux/err.h>
 
 int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	struct rk3188_cru *cru = rockchip_get_cru();
-	struct rk3188_grf *grf;
+	struct rk3188_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rockchip_sysreset_data data = {
+			.grf_soc_con0 = &grf->soc_con0,
+			.noc_remap_mask = NOC_REMAP_MASK,
+			.cru_mode_con = &cru->cru_mode_con,
+			.cru_glb_srst_snd_value = &cru->cru_glb_srst_snd_value,
+			.cru_glb_srst_fst_value = &cru->cru_glb_srst_fst_value
+	};
 
 	if (IS_ERR(cru))
 		return PTR_ERR(cru);
-	switch (type) {
-	case SYSRESET_WARM:
-		grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-		if (IS_ERR(grf))
-			return -EPROTONOSUPPORT;
 
-		/*
-		 * warm-reset keeps the remap value,
-		 * so make sure it's disabled.
-		 */
-		rk_clrsetreg(&grf->soc_con0,
-			NOC_REMAP_MASK << NOC_REMAP_SHIFT,
-			0 << NOC_REMAP_SHIFT);
-
-		rk_clrreg(&cru->cru_mode_con, 0xffff);
-		writel(0xeca8, &cru->cru_glb_srst_snd_value);
-		break;
-	case SYSRESET_COLD:
-		rk_clrreg(&cru->cru_mode_con, 0xffff);
-		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
-		break;
-	default:
+	if (IS_ERR(grf))
 		return -EPROTONOSUPPORT;
-	}
 
-	return -EINPROGRESS;
+	return rockchip_sysreset_request(&data, type);
 }
 
 static struct sysreset_ops rk3188_sysreset = {

index 6dc9ff7..a196233 100644
@@ -192,8 +192,9 @@ unsigned int dfu_polltimeout_nand(struct dfu_entity *dfu)
 int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s)
 {
 	char *st;
+#ifndef CONFIG_SPL_BUILD
 	int ret, dev, part;
-
+#endif
 	dfu->data.nand.ubi = 0;
 	dfu->dev_type = DFU_DEV_NAND;
 	st = strsep(&s, " ");

@@ -203,6 +204,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s)
 		s++;
 		dfu->data.nand.size = simple_strtoul(s, &s, 16);
 	} else if ((!strcmp(st, "part")) || (!strcmp(st, "partubi"))) {
+#ifndef CONFIG_SPL_BUILD
 		char mtd_id[32];
 		struct mtd_device *mtd_dev;
 		u8 part_num;

@@ -220,6 +222,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s)
 		mtdparts_init();
 
 		ret = find_dev_and_part(mtd_id, &mtd_dev, &part_num, &pi);
+
 		if (ret != 0) {
 			printf("Could not locate '%s'\n", mtd_id);
 			return -1;

@@ -229,6 +232,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s)
 		dfu->data.nand.size = pi->size;
 		if (!strcmp(st, "partubi"))
 			dfu->data.nand.ubi = 1;
+#endif
 	} else {
 		printf("%s: Memory layout (%s) not supported!\n", __func__, st);
 		return -1;