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Add the ZynqMP PMU and IPI

PATCH Superseded Alistair Francis 3 participants 11 messages Sep 1, 2017 – Sep 14, 2017 Arm/Zynq architecture

v2 of 7 Superseded Latest is v7 →

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Alistair Francis

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#0 lore raw

v2 cover Add the ZynqMP PMU and IPI

This series adds the ZynqMP Power Management Unit (PMU) machine with basic functionality.

The machine only has the CPU and memory connected, but that is enough to run some of the ROM code on the machine.

The series also adds the IPI device and connects it to the ZynqMP ARM side and the ZynqMP PMU. These IPI devices don't connect between the ARM and MicroBlaze instances though.

The PMU machine is missing an interrupt controller, which needs to be added later on.

Alistair Francis (6):
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU
xlnx-zynqmp-pmu: Add the CPU and memory aarch64-softmmu.mak: Use an ARM specific config
xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device
xlnx-zynqmp-pmu: Connect the IPI device to the PMU
xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC

 default-configs/aarch64-softmmu.mak    |   1 +
 default-configs/microblaze-softmmu.mak |   1 +
 hw/arm/Makefile.objs                   |   2 +-
 hw/arm/xlnx-zynqmp.c                   |  14 ++
 hw/display/Makefile.objs               |   2 +-
 hw/dma/Makefile.objs                   |   2 +-
 hw/intc/Makefile.objs                  |   1 +
 hw/intc/xlnx-zynqmp-ipi.c              | 377 +++++++++++++++++++++++++++++++++
 hw/microblaze/Makefile.objs            |   1 +
 hw/microblaze/xlnx-zynqmp-pmu.c        | 172 +++++++++++++++
 include/hw/arm/xlnx-zynqmp.h           |   2 +
 include/hw/intc/xlnx-zynqmp-ipi.h      |  57 +++++
 12 files changed, 629 insertions(+), 3 deletions(-)
 create mode 100644 hw/intc/xlnx-zynqmp-ipi.c
 create mode 100644 hw/microblaze/xlnx-zynqmp-pmu.c
 create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h
Signature · 1 line
2.11.0
author
#1 lore raw

PATCH v2 1/6 xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU

The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU.

The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being.

Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/microblaze/Makefile.objs     |  1 +
 hw/microblaze/xlnx-zynqmp-pmu.c | 83 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 84 insertions(+)
 create mode 100644 hw/microblaze/xlnx-zynqmp-pmu.c
hw/microblaze/Makefile.objs +1 -0
index b2517d87fe..ae9fd40de7 100644
@@ -1,3 +1,4 @@
 obj-y += petalogix_s3adsp1800_mmu.o
 obj-y += petalogix_ml605_mmu.o
+obj-y += xlnx-zynqmp-pmu.o
 obj-y += boot.o
hw/microblaze/xlnx-zynqmp-pmu.c new file +83 -0

83 lines not on this page · raw message

Signature · 1 line
2.11.0
author
#2 lore raw

PATCH v2 2/6 xlnx-zynqmp-pmu: Add the CPU and memory

In reply to Alistair Francis

Connect the MicroBlaze CPU and the ROM and RAM memory regions.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/microblaze/xlnx-zynqmp-pmu.c | 65 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 63 insertions(+), 2 deletions(-)
hw/microblaze/xlnx-zynqmp-pmu.c +63 -2
index fc3c8b236f..33584cfa4d 100644
@@ -18,8 +18,11 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
+#include "exec/address-spaces.h"
 #include "hw/boards.h"
+#include "hw/qdev-properties.h"
 #include "cpu.h"
+#include "boot.h"
 
 /* Define the PMU device */
 

@@ -27,21 +30,51 @@
 #define XLNX_ZYNQMP_PMU(obj) OBJECT_CHECK(XlnxZynqMPPMUState, (obj), \
                                           TYPE_XLNX_ZYNQMP_PMU)
 
+#define XLNX_ZYNQMP_PMU_ROM_SIZE    0x8000
+#define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
+#define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000
+
 typedef struct XlnxZynqMPPMUState {
     /*< private >*/
     DeviceState parent_obj;
 
     /*< public >*/
+    MicroBlazeCPU cpu;
 }  XlnxZynqMPPMUState;
 
 static void xlnx_zynqmp_pmu_init(Object *obj)
 {
+    XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);
 
+    object_initialize(&s->cpu, sizeof(s->cpu),
+                      TYPE_MICROBLAZE_CPU);
+    object_property_add_child(obj, "pmu-cpu[*]", OBJECT(&s->cpu),
+                              &error_abort);
 }
 
 static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)
 {
-
+    XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);
+
+    object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
+                             "base-vectors", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
+                             &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
+                             &error_abort);
+    object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
+                            &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &error_fatal);
 }
 
 static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)

@@ -70,7 +103,35 @@ type_init(xlnx_zynqmp_pmu_register_types)
 
 static void xlnx_zcu102_pmu_init(MachineState *machine)
 {
-
+    XlnxZynqMPPMUState *pmu = g_new0(XlnxZynqMPPMUState, 1);
+    MemoryRegion *address_space_mem = get_system_memory();
+    MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
+    MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
+
+    /* Create the ROM */
+    memory_region_init_rom(pmu_rom, NULL, "xlnx-zcu102-pmu.rom",
+                           XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
+    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
+                                pmu_rom);
+
+    /* Create the RAM */
+    memory_region_init_ram(pmu_ram, NULL, "xlnx-zcu102-pmu.ram",
+                           machine->ram_size, &error_fatal);
+    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
+                                pmu_ram);
+
+    /* Create the PMU device */
+    object_initialize(pmu, sizeof(XlnxZynqMPPMUState), TYPE_XLNX_ZYNQMP_PMU);
+    object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
+                              &error_abort);
+    object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
+
+    /* Load the kernel */
+    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
+                           machine->ram_size,
+                           machine->kernel_filename,
+                           machine->dtb,
+                           NULL);
 }
 
 static void xlnx_zcu102_pmu_machine_init(MachineClass *mc)
Signature · 1 line
2.11.0
#3 lore raw

Re: [Qemu-arm] [Qemu-devel] [PATCH v2 2/6] xlnx-zynqmp-pmu: Add the CPU and memory

Quoted 37 lines · On Fri, 1 Sep 2017 14:00:37 -0700 Alistair Francis…

Connect the MicroBlaze CPU and the ROM and RAM memory regions.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/microblaze/xlnx-zynqmp-pmu.c | 65 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 63 insertions(+), 2 deletions(-)
hw/microblaze/xlnx-zynqmp-pmu.c +7 -0
index fc3c8b236f..33584cfa4d 100644
@@ -18,8 +18,11 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
+#include "exec/address-spaces.h"
 #include "hw/boards.h"
+#include "hw/qdev-properties.h"
 #include "cpu.h"
+#include "boot.h"
 
 /* Define the PMU device */
 

@@ -27,21 +30,51 @@
 #define XLNX_ZYNQMP_PMU(obj) OBJECT_CHECK(XlnxZynqMPPMUState, (obj), \
                                           TYPE_XLNX_ZYNQMP_PMU)
 
+#define XLNX_ZYNQMP_PMU_ROM_SIZE    0x8000
+#define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
+#define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000
+
 typedef struct XlnxZynqMPPMUState {
     /*< private >*/
     DeviceState parent_obj;
 
     /*< public >*/

hw/microblaze/xlnx-zynqmp-pmu.c line 51

Quoted 10 lines
hw/microblaze/xlnx-zynqmp-pmu.c +5 -0
+    MicroBlazeCPU cpu;
 }  XlnxZynqMPPMUState;
 
 static void xlnx_zynqmp_pmu_init(Object *obj)
 {
+    XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);
 
+    object_initialize(&s->cpu, sizeof(s->cpu),
+                      TYPE_MICROBLAZE_CPU);
+    object_property_add_child(obj, "pmu-cpu[*]", OBJECT(&s->cpu),

^^^ why do you use this syntax here?

Quoted 17 lines
hw/microblaze/xlnx-zynqmp-pmu.c +12 -1
+                              &error_abort);
 }
 
 static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)
 {
-
+    XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);
+
+    object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
+                             "base-vectors", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
+                             &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",

hw/microblaze/xlnx-zynqmp-pmu.c line 77

Quoted 10 lines
hw/microblaze/xlnx-zynqmp-pmu.c +10 -0
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
+                             &error_abort);
+    object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
+                            &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &error_fatal);

I'd replace error_fatal here with errp

Quoted 40 lines
hw/microblaze/xlnx-zynqmp-pmu.c +29 -1
 }
 
 static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)

@@ -70,7 +103,35 @@ type_init(xlnx_zynqmp_pmu_register_types)
 
 static void xlnx_zcu102_pmu_init(MachineState *machine)
 {
-
+    XlnxZynqMPPMUState *pmu = g_new0(XlnxZynqMPPMUState, 1);
+    MemoryRegion *address_space_mem = get_system_memory();
+    MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
+    MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
+
+    /* Create the ROM */
+    memory_region_init_rom(pmu_rom, NULL, "xlnx-zcu102-pmu.rom",
+                           XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
+    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
+                                pmu_rom);
+
+    /* Create the RAM */
+    memory_region_init_ram(pmu_ram, NULL, "xlnx-zcu102-pmu.ram",
+                           machine->ram_size, &error_fatal);
+    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
+                                pmu_ram);
+
+    /* Create the PMU device */
+    object_initialize(pmu, sizeof(XlnxZynqMPPMUState), TYPE_XLNX_ZYNQMP_PMU);
+    object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
+                              &error_abort);
+    object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
+
+    /* Load the kernel */
+    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
+                           machine->ram_size,
+                           machine->kernel_filename,
+                           machine->dtb,
+                           NULL);
 }
 
 static void xlnx_zcu102_pmu_machine_init(MachineClass *mc)
author
#4 lore raw

Re: [Qemu-arm] [Qemu-devel] [PATCH v2 2/6] xlnx-zynqmp-pmu: Add the CPU and memory

Quoted 43 lines · Igor Mammedov
Quoted 40 lines · On Fri, 1 Sep 2017 14:00:37 -0700 Alistair Francis…

Connect the MicroBlaze CPU and the ROM and RAM memory regions.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/microblaze/xlnx-zynqmp-pmu.c | 65 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 63 insertions(+), 2 deletions(-)
hw/microblaze/xlnx-zynqmp-pmu.c +8 -0
index fc3c8b236f..33584cfa4d 100644
@@ -18,8 +18,11 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
+#include "exec/address-spaces.h"
 #include "hw/boards.h"
+#include "hw/qdev-properties.h"
 #include "cpu.h"
+#include "boot.h"
 
 /* Define the PMU device */
 

@@ -27,21 +30,51 @@
 #define XLNX_ZYNQMP_PMU(obj) OBJECT_CHECK(XlnxZynqMPPMUState, (obj), \
                                           TYPE_XLNX_ZYNQMP_PMU)
 
+#define XLNX_ZYNQMP_PMU_ROM_SIZE    0x8000
+#define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
+#define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000
+
 typedef struct XlnxZynqMPPMUState {
     /*< private >*/
     DeviceState parent_obj;
 
     /*< public >*/
+    MicroBlazeCPU cpu;
 }  XlnxZynqMPPMUState;
Quoted 9 lines

hw/microblaze/xlnx-zynqmp-pmu.c line 51

Quoted 7 lines
hw/microblaze/xlnx-zynqmp-pmu.c +4 -0
 static void xlnx_zynqmp_pmu_init(Object *obj)
 {
+    XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);
 
+    object_initialize(&s->cpu, sizeof(s->cpu),
+                      TYPE_MICROBLAZE_CPU);
+    object_property_add_child(obj, "pmu-cpu[*]", OBJECT(&s->cpu),

^^^ why do you use this syntax here?

Woops, that was a left over from the ARM ZynqMP. I'll remove the '[*]'

Quoted 20 lines
Quoted 20 lines
hw/microblaze/xlnx-zynqmp-pmu.c +15 -1
+                              &error_abort);
 }
 
 static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)
 {
-
+    XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);
+
+    object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
+                             "base-vectors", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
+                             &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
+                             &error_abort);
Quoted 8 lines

hw/microblaze/xlnx-zynqmp-pmu.c line 77

Quoted 7 lines
hw/microblaze/xlnx-zynqmp-pmu.c +7 -0
+    object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
+                             &error_abort);
+    object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
+                            &error_abort);
+    object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
+    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &error_fatal);

I'd replace error_fatal here with errp

Will do.

Thanks,
Alistair

Quoted 42 lines
Quoted 41 lines
hw/microblaze/xlnx-zynqmp-pmu.c +29 -1
 }
 
 static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)

@@ -70,7 +103,35 @@ type_init(xlnx_zynqmp_pmu_register_types)
 
 static void xlnx_zcu102_pmu_init(MachineState *machine)
 {
-
+    XlnxZynqMPPMUState *pmu = g_new0(XlnxZynqMPPMUState, 1);
+    MemoryRegion *address_space_mem = get_system_memory();
+    MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
+    MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
+
+    /* Create the ROM */
+    memory_region_init_rom(pmu_rom, NULL, "xlnx-zcu102-pmu.rom",
+                           XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
+    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
+                                pmu_rom);
+
+    /* Create the RAM */
+    memory_region_init_ram(pmu_ram, NULL, "xlnx-zcu102-pmu.ram",
+                           machine->ram_size, &error_fatal);
+    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
+                                pmu_ram);
+
+    /* Create the PMU device */
+    object_initialize(pmu, sizeof(XlnxZynqMPPMUState), TYPE_XLNX_ZYNQMP_PMU);
+    object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
+                              &error_abort);
+    object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
+
+    /* Load the kernel */
+    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
+                           machine->ram_size,
+                           machine->kernel_filename,
+                           machine->dtb,
+                           NULL);
 }
 
 static void xlnx_zcu102_pmu_machine_init(MachineClass *mc)
author
#5 lore raw

PATCH v2 3/6 aarch64-softmmu.mak: Use an ARM specific config

In reply to Alistair Francis

In preperation for having an ARM and MicroBlaze ZynqMP machine let's split out the current ARM specific config options.

Signed-off-by Alistair Francis <[email protected]>

---

 default-configs/aarch64-softmmu.mak | 1 +
 hw/arm/Makefile.objs                | 2 +-
 hw/display/Makefile.objs            | 2 +-
 hw/dma/Makefile.objs                | 2 +-
 4 files changed, 4 insertions(+), 3 deletions(-)
default-configs/aarch64-softmmu.mak +1 -0
index 24494832cf..9ddccf855e 100644
@@ -7,3 +7,4 @@ CONFIG_AUX=y
 CONFIG_DDC=y
 CONFIG_DPCD=y
 CONFIG_XLNX_ZYNQMP=y
+CONFIG_XLNX_ZYNQMP_ARM=y
hw/arm/Makefile.objs +1 -1
index a2e56ecaae..95daa67836 100644
@@ -13,7 +13,7 @@ obj-y += omap1.o omap2.o strongarm.o
 obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
 obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
 obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
+obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-ep108.o
 obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
 obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
 obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
hw/display/Makefile.objs +1 -1
index 551c050a6a..d3a4cb396e 100644
@@ -40,4 +40,4 @@ virtio-gpu.o-libs += $(VIRGL_LIBS)
 virtio-gpu-3d.o-cflags := $(VIRGL_CFLAGS)
 virtio-gpu-3d.o-libs += $(VIRGL_LIBS)
 obj-$(CONFIG_DPCD) += dpcd.o
-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx_dp.o
+obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx_dp.o
hw/dma/Makefile.objs +1 -1
index 087c8e6855..be98d5d3d8 100644
@@ -9,7 +9,7 @@ common-obj-$(CONFIG_ZYNQ_DEVCFG) += xlnx-zynq-devcfg.o
 common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
 common-obj-$(CONFIG_STP2000) += sparc32_dma.o
 common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx_dpdma.o
+obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx_dpdma.o
 
 obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
 obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
Signature · 1 line
2.11.0
Acked-by on v2 3/6
#6 lore raw

Re: [Qemu-arm] [Qemu-devel] [PATCH v2 3/6] aarch64-softmmu.mak: Use an ARM specific config

Quoted 4 lines · Alistair Francis

In preperation for having an ARM and MicroBlaze ZynqMP machine let's split out the current ARM specific config options.

Signed-off-by Alistair Francis <[email protected]>
Acked-by Peter Maydell <[email protected]>

I'm assuming this series is going be reviewed and go into master via a microblaze tree, not the arm one...

thanks
-- PMM

author
#7 lore raw

Re: [Qemu-arm] [Qemu-devel] [PATCH v2 3/6] aarch64-softmmu.mak: Use an ARM specific config

Quoted 8 lines · Peter Maydell
Quoted 4 lines · Alistair Francis

In preperation for having an ARM and MicroBlaze ZynqMP machine let's split out the current ARM specific config options.

Signed-off-by Alistair Francis <[email protected]>
Acked-by Peter Maydell <[email protected]>

Thanks Peter.

Quoted 3 lines

I'm assuming this series is going be reviewed and go into master via a microblaze tree, not the arm one...

I talked to Edgar and that is the plan.

Thanks,
Alistair

Quoted 3 lines

thanks
-- PMM

author
#8 lore raw

PATCH v2 4/6 xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device

In reply to Alistair Francis

This is the initial version of the Inter Processor Interrupt device.

Signed-off-by Alistair Francis <[email protected]>

---

 default-configs/microblaze-softmmu.mak |   1 +
 hw/intc/Makefile.objs                  |   1 +
 hw/intc/xlnx-zynqmp-ipi.c              | 377 +++++++++++++++++++++++++++++++++
 include/hw/intc/xlnx-zynqmp-ipi.h      |  57 +++++
 4 files changed, 436 insertions(+)
 create mode 100644 hw/intc/xlnx-zynqmp-ipi.c
 create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h
default-configs/microblaze-softmmu.mak +1 -0
index ce2630818a..7fca8e4c99 100644
@@ -9,3 +9,4 @@ CONFIG_XILINX_SPI=y
 CONFIG_XILINX_ETHLITE=y
 CONFIG_SSI=y
 CONFIG_SSI_M25P80=y
+CONFIG_XLNX_ZYNQMP=y
hw/intc/Makefile.objs +1 -0
index 78426a7daf..be3a1873d1 100644
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_I8259) += i8259_common.o i8259.o
 common-obj-$(CONFIG_PL190) += pl190.o
 common-obj-$(CONFIG_PUV3) += puv3_intc.o
 common-obj-$(CONFIG_XILINX) += xilinx_intc.o
+common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o
 common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o
 common-obj-$(CONFIG_IMX) += imx_avic.o
 common-obj-$(CONFIG_LM32) += lm32_pic.o
hw/intc/xlnx-zynqmp-ipi.c new file +377 -0

377 lines not on this page · raw message

include/hw/intc/xlnx-zynqmp-ipi.h new file +57 -0

57 lines not on this page · raw message

Signature · 1 line
2.11.0
author
#9 lore raw

PATCH v2 5/6 xlnx-zynqmp-pmu: Connect the IPI device to the PMU

In reply to Alistair Francis
Signed-off-by Alistair Francis <[email protected]>

---

 hw/microblaze/xlnx-zynqmp-pmu.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
hw/microblaze/xlnx-zynqmp-pmu.c +28 -0
index 33584cfa4d..a6c14495ec 100644
@@ -24,6 +24,8 @@
 #include "cpu.h"
 #include "boot.h"
 
+#include "hw/intc/xlnx-zynqmp-ipi.h"
+
 /* Define the PMU device */
 
 #define TYPE_XLNX_ZYNQMP_PMU "xlnx,zynqmp-pmu"

@@ -34,27 +36,42 @@
 #define XLNX_ZYNQMP_PMU_ROM_ADDR    0xFFD00000
 #define XLNX_ZYNQMP_PMU_RAM_ADDR    0xFFDC0000
 
+#define XLNX_ZYNQMP_PMU_NUM_IPIS    4
+
+static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
+    0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
+};
+
 typedef struct XlnxZynqMPPMUState {
     /*< private >*/
     DeviceState parent_obj;
 
     /*< public >*/
     MicroBlazeCPU cpu;
+    XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
 }  XlnxZynqMPPMUState;
 
 static void xlnx_zynqmp_pmu_init(Object *obj)
 {
     XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);
+    int i;
 
     object_initialize(&s->cpu, sizeof(s->cpu),
                       TYPE_MICROBLAZE_CPU);
     object_property_add_child(obj, "pmu-cpu[*]", OBJECT(&s->cpu),
                               &error_abort);
+
+   for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+        object_initialize(&s->ipi[i], sizeof(s->ipi[i]), TYPE_XLNX_ZYNQMP_IPI);
+        qdev_set_parent_bus(DEVICE(&s->ipi[i]), sysbus_get_default());
+    }
 }
 
 static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)
 {
     XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);
+    Error *err = NULL;
+    int i;
 
     object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
                              "base-vectors", &error_abort);

@@ -75,6 +92,17 @@ static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)
                             &error_abort);
     object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &error_fatal);
+
+    for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+        object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
+        /* Need to connect this to an interrupt controller */
+    }
+
 }
 
 static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)
Signature · 1 line
2.11.0
author
#10 lore raw

PATCH v2 6/6 xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC

In reply to Alistair Francis
Signed-off-by Alistair Francis <[email protected]>

---

 hw/arm/xlnx-zynqmp.c         | 14 ++++++++++++++
 include/hw/arm/xlnx-zynqmp.h |  2 ++
 2 files changed, 16 insertions(+)
hw/arm/xlnx-zynqmp.c +14 -0
index 9eceadbdc8..1988cb47f4 100644
@@ -46,6 +46,9 @@
 #define DPDMA_ADDR          0xfd4c0000
 #define DPDMA_IRQ           116
 
+#define IPI_ADDR            0xFF300000
+#define IPI_IRQ             64
+
 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
 };

@@ -179,6 +182,9 @@ static void xlnx_zynqmp_init(Object *obj)
 
     object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
     qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
+
+    object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI);
+    qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default());
 }
 
 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)

@@ -427,6 +433,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
                              &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
+
+    object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 }
 
 static Property xlnx_zynqmp_props[] = {
include/hw/arm/xlnx-zynqmp.h +2 -0
index c2931bf39c..02a89766e8 100644
@@ -28,6 +28,7 @@
 #include "hw/ssi/xilinx_spips.h"
 #include "hw/dma/xlnx_dpdma.h"
 #include "hw/display/xlnx_dp.h"
+#include "hw/intc/xlnx-zynqmp-ipi.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \

@@ -85,6 +86,7 @@ typedef struct XlnxZynqMPState {
     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
     XlnxDPState dp;
     XlnxDPDMAState dpdma;
+    XlnxZynqMPIPI ipi;
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
Signature · 1 line
2.11.0