qat: remove atomics

PATCH Applied Anatoly Burakov 3 participants 12 messages Aug 25, 2017 – Sep 18, 2017 1 message not in the archive Crypto API

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Anatoly Burakov

author

2017-08-25 09:31 UTC #1 lore raw

PATCH v2 1/3 qat: remove atomics

From: "Burakov, Anatoly" <[email protected]>

Replacing atomics in the qat driver with simple 16-bit integers for number of inflight packets.

This adds a new limitation to the QAT driver: each queue pair is now explicitly single-threaded.

Signed-off-by Burakov, Anatoly <[email protected]>

---
 doc/guides/cryptodevs/qat.rst          |  1 +
 doc/guides/rel_notes/release_17_11.rst |  6 ++++++
 drivers/crypto/qat/qat_crypto.c        | 12 +++++-------
 drivers/crypto/qat/qat_crypto.h        |  2 +-
 drivers/crypto/qat/qat_qp.c            |  4 ++--
 5 files changed, 15 insertions(+), 10 deletions(-)

doc/guides/cryptodevs/qat.rst +1 -0

index a3fce7b..cb17b6b 100644
@@ -90,6 +90,7 @@ Limitations
 * No BSD support as BSD QAT kernel driver not available.
 * ZUC EEA3/EIA3 is not supported by dh895xcc devices
 * Maximum additional authenticated data (AAD) for GCM is 240 bytes long.
+* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
 
 
 Installation

doc/guides/rel_notes/release_17_11.rst +6 -0

index 170f4f9..67b6f68 100644
@@ -41,6 +41,12 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Updated qat crypto PMD.**
+
+  Performance enhancements:
+
+  * Removed atomics from the internal queue pair structure.
+
 
 Resolved Issues
 ---------------

drivers/crypto/qat/qat_crypto.c +5 -7

index 1f52cab..2ee5866 100644
@@ -52,7 +52,6 @@
 #include <rte_eal.h>
 #include <rte_per_lcore.h>
 #include <rte_lcore.h>
-#include <rte_atomic.h>
 #include <rte_branch_prediction.h>
 #include <rte_mempool.h>
 #include <rte_mbuf.h>

@@ -946,10 +945,10 @@ qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 	tail = queue->tail;
 
 	/* Find how many can actually fit on the ring */
-	overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
-				- queue->max_inflights;
+	tmp_qp->inflights16 += nb_ops;
+	overflow = tmp_qp->inflights16 - queue->max_inflights;
 	if (overflow > 0) {
-		rte_atomic16_sub(&tmp_qp->inflights16, overflow);
+		tmp_qp->inflights16 -= overflow;
 		nb_ops_possible = nb_ops - overflow;
 		if (nb_ops_possible == 0)
 			return 0;

@@ -964,8 +963,7 @@ qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 			 * This message cannot be enqueued,
 			 * decrease number of ops that wasn't sent
 			 */
-			rte_atomic16_sub(&tmp_qp->inflights16,
-					nb_ops_possible - nb_ops_sent);
+			tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
 			if (nb_ops_sent == 0)
 				return 0;
 			goto kick_tail;

@@ -1037,7 +1035,7 @@ qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 		WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
 					queue->hw_bundle_number,
 					queue->hw_queue_number, queue->head);
-		rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
+		tmp_qp->inflights16 -= msg_counter;
 		tmp_qp->stats.dequeued_count += msg_counter;
 	}
 	return msg_counter;

drivers/crypto/qat/qat_crypto.h +1 -1

index 3f35a00..7773b57 100644
@@ -77,7 +77,7 @@ struct qat_queue {
 
 struct qat_qp {
 	void			*mmap_bar_addr;
-	rte_atomic16_t		inflights16;
+	uint16_t		inflights16;
 	struct	qat_queue	tx_q;
 	struct	qat_queue	rx_q;
 	struct	rte_cryptodev_stats stats;

drivers/crypto/qat/qat_qp.c +2 -2

index 5048d21..e98bffe 100644
@@ -186,7 +186,7 @@ int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
 			RTE_CACHE_LINE_SIZE);
 
 	qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
-	rte_atomic16_init(&qp->inflights16);
+	qp->inflights16 = 0;
 
 	if (qat_tx_queue_create(dev, &(qp->tx_q),
 		queue_pair_id, qp_conf->nb_descriptors, socket_id) != 0) {

@@ -269,7 +269,7 @@ int qat_crypto_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)
 	}
 
 	/* Don't free memory if there are still responses to be processed */
-	if (rte_atomic16_read(&(qp->inflights16)) == 0) {
+	if (qp->inflights16 == 0) {
 		qat_queue_delete(&(qp->tx_q));
 		qat_queue_delete(&(qp->rx_q));
 	} else {

Signature · 1 line

2.7.4

Anatoly Burakov

author

2017-09-12 09:31 UTC #2 lore raw

PATCH v2 1/3 crypto/qat: remove atomics

Replacing atomics in the QAT driver with simple 16-bit integers for number of inflight packets.

This adds a new limitation to the QAT driver: each queue pair is now explicitly single-threaded.

Signed-off-by Anatoly Burakov <[email protected]>

---
v2: fixed commit message
fixed documentation

 doc/guides/cryptodevs/qat.rst          |  1 +
 doc/guides/rel_notes/release_17_11.rst |  6 ++++++
 drivers/crypto/qat/qat_crypto.c        | 12 +++++-------
 drivers/crypto/qat/qat_crypto.h        |  2 +-
 drivers/crypto/qat/qat_qp.c            |  4 ++--
 5 files changed, 15 insertions(+), 10 deletions(-)

doc/guides/cryptodevs/qat.rst +1 -0

index a3fce7b..cb17b6b 100644
@@ -90,6 +90,7 @@ Limitations
 * No BSD support as BSD QAT kernel driver not available.
 * ZUC EEA3/EIA3 is not supported by dh895xcc devices
 * Maximum additional authenticated data (AAD) for GCM is 240 bytes long.
+* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
 
 
 Installation

doc/guides/rel_notes/release_17_11.rst +6 -0

index 170f4f9..96f954f 100644
@@ -41,6 +41,12 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Updated QAT crypto PMD.**
+
+  Performance enhancements:
+
+  * Removed atomics from the internal queue pair structure.
+
 
 Resolved Issues
 ---------------

drivers/crypto/qat/qat_crypto.c +5 -7

index 62ee175..bb199ae 100644
@@ -51,7 +51,6 @@
 #include <rte_eal.h>
 #include <rte_per_lcore.h>
 #include <rte_lcore.h>
-#include <rte_atomic.h>
 #include <rte_branch_prediction.h>
 #include <rte_mempool.h>
 #include <rte_mbuf.h>

@@ -945,10 +944,10 @@ qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 	tail = queue->tail;
 
 	/* Find how many can actually fit on the ring */
-	overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
-				- queue->max_inflights;
+	tmp_qp->inflights16 += nb_ops;
+	overflow = tmp_qp->inflights16 - queue->max_inflights;
 	if (overflow > 0) {
-		rte_atomic16_sub(&tmp_qp->inflights16, overflow);
+		tmp_qp->inflights16 -= overflow;
 		nb_ops_possible = nb_ops - overflow;
 		if (nb_ops_possible == 0)
 			return 0;

@@ -963,8 +962,7 @@ qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 			 * This message cannot be enqueued,
 			 * decrease number of ops that wasn't sent
 			 */
-			rte_atomic16_sub(&tmp_qp->inflights16,
-					nb_ops_possible - nb_ops_sent);
+			tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
 			if (nb_ops_sent == 0)
 				return 0;
 			goto kick_tail;

@@ -1036,7 +1034,7 @@ qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 		WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
 					queue->hw_bundle_number,
 					queue->hw_queue_number, queue->head);
-		rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
+		tmp_qp->inflights16 -= msg_counter;
 		tmp_qp->stats.dequeued_count += msg_counter;
 	}
 	return msg_counter;

drivers/crypto/qat/qat_crypto.h +1 -1

index 3f35a00..7773b57 100644
@@ -77,7 +77,7 @@ struct qat_queue {
 
 struct qat_qp {
 	void			*mmap_bar_addr;
-	rte_atomic16_t		inflights16;
+	uint16_t		inflights16;
 	struct	qat_queue	tx_q;
 	struct	qat_queue	rx_q;
 	struct	rte_cryptodev_stats stats;

drivers/crypto/qat/qat_qp.c +2 -2

index 5048d21..e98bffe 100644
@@ -186,7 +186,7 @@ int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
 			RTE_CACHE_LINE_SIZE);
 
 	qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
-	rte_atomic16_init(&qp->inflights16);
+	qp->inflights16 = 0;
 
 	if (qat_tx_queue_create(dev, &(qp->tx_q),
 		queue_pair_id, qp_conf->nb_descriptors, socket_id) != 0) {

@@ -269,7 +269,7 @@ int qat_crypto_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)
 	}
 
 	/* Don't free memory if there are still responses to be processed */
-	if (rte_atomic16_read(&(qp->inflights16)) == 0) {
+	if (qp->inflights16 == 0) {
 		qat_queue_delete(&(qp->tx_q));
 		qat_queue_delete(&(qp->rx_q));
 	} else {

Signature · 1 line

2.7.4

Trahe, Fiona

Acked-by on v2 1/3

2017-09-15 11:35 UTC #3 lore raw

Re: [PATCH v2 1/3] crypto/qat: remove atomics

Quoted 10 lines

-----Original Message-----
From: Burakov, Anatoly
Sent: Tuesday, September 12, 2017 10:31 AM
To: [email protected]
Cc: Trahe, Fiona <[email protected]>; Griffin, John <[email protected]>; Jain, Deepak K <[email protected]>; De Lara Guarch, Pablo <[email protected]>
Subject: [PATCH v2 1/3] crypto/qat: remove atomics

Quoted 7 lines

Replacing atomics in the QAT driver with simple 16-bit integers for number of inflight packets.
This adds a new limitation to the QAT driver: each queue pair is now explicitly single-threaded.
Signed-off-by Anatoly Burakov <[email protected]>

Acked-by Fiona Trahe <[email protected]>

Anatoly Burakov

author

2017-08-25 09:31 UTC #4 lore raw

PATCH v2 2/3 qat: enable RX head writes coalescing

In reply to Anatoly Burakov

From: "Burakov, Anatoly" <[email protected]>

Don't write CSR head until we processed enough RX descriptors. Also delay marking them as free until we are writing CSR head.

Signed-off-by Burakov, Anatoly <[email protected]>

---
 doc/guides/rel_notes/release_17_11.rst |  1 +
 drivers/crypto/qat/qat_crypto.c        | 49 ++++++++++++++++++++++++++--------
 drivers/crypto/qat/qat_crypto.h        |  6 +++++
 3 files changed, 45 insertions(+), 11 deletions(-)

doc/guides/rel_notes/release_17_11.rst +1 -0

index 67b6f68..0a400cd 100644
@@ -46,6 +46,7 @@ New Features
   Performance enhancements:
 
   * Removed atomics from the internal queue pair structure.
+  * Coalesce writes to HEAD CSR on response processing.
 
 
 Resolved Issues

drivers/crypto/qat/qat_crypto.c +38 ~~-11~~

77 lines not on this page · raw message

drivers/crypto/qat/qat_crypto.h +6 -0

index 7773b57..d78957c 100644
@@ -50,6 +50,9 @@
 	(((num) + (align) - 1) & ~((align) - 1))
 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
 
+#define QAT_CSR_HEAD_WRITE_THRESH 32U
+/* number of requests to accumulate before writing head CSR */
+
 struct qat_session;
 
 enum qat_device_gen {

@@ -73,6 +76,9 @@ struct qat_queue {
 	uint8_t		hw_bundle_number;
 	uint8_t		hw_queue_number;
 	/* HW queue aka ring offset on bundle */
+	uint32_t	csr_head;		/* last written head value */
+	uint16_t	nb_processed_responses;
+	/* number of responses processed since last CSR head write */
 };
 
 struct qat_qp {

Signature · 1 line

2.7.4

De Lara Guarch, Pablo

2017-09-04 14:39 UTC #5 lore raw

In reply to Anatoly Burakov

Quoted 11 lines

-----Original Message-----
From: Burakov, Anatoly
Sent: Friday, August 25, 2017 10:31 AM
To: [email protected]
Cc: Griffin, John <[email protected]>; Trahe, Fiona <[email protected]>; Jain, Deepak K <[email protected]>; De Lara Guarch, Pablo <[email protected]>; Burakov, Anatoly <[email protected]>
Subject: [DPDK] [PATCH 1/3] qat: remove atomics

Title should be "crypto/qat: remove..."

Quoted 18 lines

From: "Burakov, Anatoly" <[email protected]>
Replacing atomics in the qat driver with simple 16-bit integers for number of inflight packets.
This adds a new limitation to the QAT driver: each queue pair is now explicitly single-threaded.
Signed-off-by Burakov, Anatoly <[email protected]>
---
 doc/guides/cryptodevs/qat.rst          |  1 +
 doc/guides/rel_notes/release_17_11.rst |  6 ++++++
 drivers/crypto/qat/qat_crypto.c        | 12 +++++-------
 drivers/crypto/qat/qat_crypto.h        |  2 +-
 drivers/crypto/qat/qat_qp.c            |  4 ++--
 5 files changed, 15 insertions(+), 10 deletions(-)

...

Quoted 11 lines

doc/guides/rel_notes/release_17_11.rst +0 -0
index 170f4f9..67b6f68 100644
@@ -41,6 +41,12 @@ New Features
      Also, make sure to start the actual text at the margin.
 
=========================================================
+* **Updated qat crypto PMD.**

"qat" should be in capital letters.

Quoted 6 lines

doc/guides/rel_notes/release_17_11.rst +5 -0

+
+  Performance enhancements:
+
+  * Removed atomics from the internal queue pair structure.
+

Anatoly Burakov

author

2017-09-12 09:31 UTC #6 lore raw

PATCH v2 2/3 crypto/qat: enable RX head writes coalescing

In reply to Anatoly Burakov

Don't write CSR head until we processed enough RX descriptors. Also delay marking them as free until we are writing CSR head.

Signed-off-by Anatoly Burakov <[email protected]>

---
v2: fixed commit message

 doc/guides/rel_notes/release_17_11.rst |  1 +
 drivers/crypto/qat/qat_crypto.c        | 49 ++++++++++++++++++++++++++--------
 drivers/crypto/qat/qat_crypto.h        |  6 +++++
 3 files changed, 45 insertions(+), 11 deletions(-)

doc/guides/rel_notes/release_17_11.rst +1 -0

index 96f954f..0b77095 100644
@@ -46,6 +46,7 @@ New Features
   Performance enhancements:
 
   * Removed atomics from the internal queue pair structure.
+  * Coalesce writes to HEAD CSR on response processing.
 
 
 Resolved Issues

drivers/crypto/qat/qat_crypto.c +38 ~~-11~~

77 lines not on this page · raw message

drivers/crypto/qat/qat_crypto.h +6 -0

index 7773b57..d78957c 100644
@@ -50,6 +50,9 @@
 	(((num) + (align) - 1) & ~((align) - 1))
 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
 
+#define QAT_CSR_HEAD_WRITE_THRESH 32U
+/* number of requests to accumulate before writing head CSR */
+
 struct qat_session;
 
 enum qat_device_gen {

@@ -73,6 +76,9 @@ struct qat_queue {
 	uint8_t		hw_bundle_number;
 	uint8_t		hw_queue_number;
 	/* HW queue aka ring offset on bundle */
+	uint32_t	csr_head;		/* last written head value */
+	uint16_t	nb_processed_responses;
+	/* number of responses processed since last CSR head write */
 };
 
 struct qat_qp {

Signature · 1 line

2.7.4

Trahe, Fiona

Acked-by on v2 2/3

2017-09-15 11:55 UTC #7 lore raw

Re: [PATCH v2 2/3] crypto/qat: enable RX head writes coalescing

Quoted 10 lines

-----Original Message-----
From: Burakov, Anatoly
Sent: Tuesday, September 12, 2017 10:31 AM
To: [email protected]
Cc: Trahe, Fiona <[email protected]>; Griffin, John <[email protected]>; Jain, Deepak K <[email protected]>; De Lara Guarch, Pablo <[email protected]>
Subject: [PATCH v2 2/3] crypto/qat: enable RX head writes coalescing

Quoted 4 lines

Don't write CSR head until we processed enough RX descriptors. Also delay marking them as free until we are writing CSR head.
Signed-off-by Anatoly Burakov <[email protected]>

Acked-by Fiona Trahe <[email protected]>

Anatoly Burakov

author

2017-09-12 09:31 UTC #8 lore raw

v2 cover performance enhancements for QAT driver

In reply to Anatoly Burakov

A few performance enhancements for QAT crypto driver. These include:
- Removing reliance on atomics on hot path
- This adds a new limitation, making queue pairs single-threaded
- Coalesce RX and TX CSR writes

v2: added cover letter
fixed commit messages
fixed documentation

Anatoly Burakov (3):
crypto/qat: remove atomics
crypto/qat: enable RX head writes coalescing
crypto/qat: enable TX tail writes coalescing

 doc/guides/cryptodevs/qat.rst          |  1 +
 doc/guides/rel_notes/release_17_11.rst |  8 ++++
 drivers/crypto/qat/qat_crypto.c        | 84 +++++++++++++++++++++++++---------
 drivers/crypto/qat/qat_crypto.h        | 15 +++++-
 drivers/crypto/qat/qat_qp.c            |  4 +-
 5 files changed, 88 insertions(+), 24 deletions(-)

Signature · 1 line

2.7.4

De Lara Guarch, Pablo

Applied

2017-09-18 11:03 UTC #9 lore raw

Re: [PATCH v2 0/3] performance enhancements for QAT driver

Quoted 33 lines

-----Original Message-----
From: Burakov, Anatoly
Sent: Tuesday, September 12, 2017 10:31 AM
To: [email protected]
Cc: Trahe, Fiona <[email protected]>; Griffin, John <[email protected]>; Jain, Deepak K <[email protected]>; De Lara Guarch, Pablo <[email protected]>
Subject: [PATCH v2 0/3] performance enhancements for QAT driver
A few performance enhancements for QAT crypto driver. These include:
- Removing reliance on atomics on hot path
- This adds a new limitation, making queue pairs single-threaded
- Coalesce RX and TX CSR writes
v2: added cover letter
fixed commit messages
fixed documentation
Anatoly Burakov (3):
crypto/qat: remove atomics
crypto/qat: enable RX head writes coalescing
crypto/qat: enable TX tail writes coalescing
 doc/guides/cryptodevs/qat.rst          |  1 +
 doc/guides/rel_notes/release_17_11.rst |  8 ++++
 drivers/crypto/qat/qat_crypto.c        | 84 +++++++++++++++++++++++++-
--------
 drivers/crypto/qat/qat_crypto.h        | 15 +++++-
 drivers/crypto/qat/qat_qp.c            |  4 +-
 5 files changed, 88 insertions(+), 24 deletions(-)

Quoted 2 lines

--
2.7.4

Applied to dpdk-next-crypto.
Thanks,

Pablo

Anatoly Burakov

author

2017-08-25 09:31 UTC #10 lore raw

PATCH v2 3/3 qat: enable TX tail writes coalescing

In reply to Anatoly Burakov

From: "Burakov, Anatoly" <[email protected]>

Don't write CSR tail until we processed enough TX descriptors.

To avoid crypto operations sitting in the TX ring indefinitely, the "force write" threshold is used:
- on TX, no tail write coalescing will occur if number of inflights is below force write threshold
- on RX, check if we have a number of crypto ops enqueued that is below force write threshold that are not yet submitted to processing.

Signed-off-by Burakov, Anatoly <[email protected]>

---
 doc/guides/rel_notes/release_17_11.rst |  1 +
 drivers/crypto/qat/qat_crypto.c        | 41 ++++++++++++++++++++++++----------
 drivers/crypto/qat/qat_crypto.h        |  7 ++++++
 3 files changed, 37 insertions(+), 12 deletions(-)

doc/guides/rel_notes/release_17_11.rst +1 -0

index 0a400cd..ad9474c 100644
@@ -47,6 +47,7 @@ New Features
 
   * Removed atomics from the internal queue pair structure.
   * Coalesce writes to HEAD CSR on response processing.
+  * Coalesce writes to TAIL CSR on request processing.
 
 
 Resolved Issues

drivers/crypto/qat/qat_crypto.c +29 ~~-12~~

83 lines not on this page · raw message

drivers/crypto/qat/qat_crypto.h +7 -0

index d78957c..0ebb083 100644
@@ -52,6 +52,10 @@
 
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */
+#define QAT_CSR_TAIL_WRITE_THRESH 32U
+/* number of requests to accumulate before writing tail CSR */
+#define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
+/* number of inflights below which no tail write coalescing should occur */
 
 struct qat_session;

@@ -77,8 +81,11 @@ struct qat_queue {
 	uint8_t		hw_queue_number;
 	/* HW queue aka ring offset on bundle */
 	uint32_t	csr_head;		/* last written head value */
+	uint32_t	csr_tail;		/* last written tail value */
 	uint16_t	nb_processed_responses;
 	/* number of responses processed since last CSR head write */
+	uint16_t	nb_pending_requests;
+	/* number of requests pending since last CSR tail write */
 };
 
 struct qat_qp {

Signature · 1 line

2.7.4

Anatoly Burakov

author

2017-09-12 09:31 UTC #11 lore raw

PATCH v2 3/3 crypto/qat: enable TX tail writes coalescing

In reply to Anatoly Burakov

Don't write CSR tail until we processed enough TX descriptors.

Signed-off-by Anatoly Burakov <[email protected]>

---
v2: fixed commit message

 doc/guides/rel_notes/release_17_11.rst |  1 +
 drivers/crypto/qat/qat_crypto.c        | 41 ++++++++++++++++++++++++----------
 drivers/crypto/qat/qat_crypto.h        |  7 ++++++
 3 files changed, 37 insertions(+), 12 deletions(-)

doc/guides/rel_notes/release_17_11.rst +1 -0

index 0b77095..f0d3960 100644
@@ -47,6 +47,7 @@ New Features
 
   * Removed atomics from the internal queue pair structure.
   * Coalesce writes to HEAD CSR on response processing.
+  * Coalesce writes to TAIL CSR on request processing.
 
 
 Resolved Issues

drivers/crypto/qat/qat_crypto.c +29 ~~-12~~

83 lines not on this page · raw message

drivers/crypto/qat/qat_crypto.h +7 -0

index d78957c..0ebb083 100644
@@ -52,6 +52,10 @@
 
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */
+#define QAT_CSR_TAIL_WRITE_THRESH 32U
+/* number of requests to accumulate before writing tail CSR */
+#define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
+/* number of inflights below which no tail write coalescing should occur */
 
 struct qat_session;

@@ -77,8 +81,11 @@ struct qat_queue {
 	uint8_t		hw_queue_number;
 	/* HW queue aka ring offset on bundle */
 	uint32_t	csr_head;		/* last written head value */
+	uint32_t	csr_tail;		/* last written tail value */
 	uint16_t	nb_processed_responses;
 	/* number of responses processed since last CSR head write */
+	uint16_t	nb_pending_requests;
+	/* number of requests pending since last CSR tail write */
 };
 
 struct qat_qp {

Signature · 1 line

2.7.4

Trahe, Fiona

Acked-by on v2 3/3

2017-09-15 13:17 UTC #12 lore raw

Re: [PATCH v2 3/3] crypto/qat: enable TX tail writes coalescing

Quoted 20 lines

-----Original Message-----
From: Burakov, Anatoly
Sent: Tuesday, September 12, 2017 10:31 AM
To: [email protected]
Cc: Trahe, Fiona <[email protected]>; Griffin, John <[email protected]>; Jain, Deepak K <[email protected]>; De Lara Guarch, Pablo <[email protected]>
Subject: [PATCH v2 3/3] crypto/qat: enable TX tail writes coalescing
Don't write CSR tail until we processed enough TX descriptors.
To avoid crypto operations sitting in the TX ring indefinitely, the "force write" threshold is used:
- on TX, no tail write coalescing will occur if number of inflights is below force write threshold
- on RX, check if we have a number of crypto ops enqueued that is below force write threshold that are not yet submitted to processing.

Quoted 1 line

Signed-off-by Anatoly Burakov <[email protected]>

Acked-by Fiona Trahe <[email protected]>