zynqmp: arm64: DT changes
Subsystems (4)
cover zynqmp: arm64: DT changes
This patchset is updating zynqmp DT binding.
Thanks,
Michal
Anurag Kumar Vulisha (6):
arm64: zynqmp: Add SMMU support for SATA IP
arm64: zynqmp: Add reset-controller support in serdes driver
arm64: zynqmp: Use reset controller framework for
asserting/de-asserting reset
arm64: zynqmp: Add support reading SoC revision using nvmem driver in
dwc3
arm64: zynqmp: Uncomment snps,quirk-frame-length-adjustment flag in
dwc3
arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USB
Bharat Kumar Gogada (1):
arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
Chirag Parekh (1):
arm64: zynqmp: Update device tree for gpio
Hyun Kwon (1):
arm64: zynqmp: Update the GPU address size
Jolly Shah (1):
arm64: zynqmp: Reduced min-residency time for idle state node
Jyotheeswar Reddy (1):
arm64: zynqmp: DT: Fix typo in idle-states node definition
Jyotheeswar Reddy Mutthareddyvari (1):
arm64: zynqmp: PM: Specify power domains for DP related nodes
Madhurkiran Harikrishnan (1):
arm64: zynqmp: Add clock name for GPU
Manish Narani (3):
arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0
silicon
arm64: zynqmp: Enabled CCI support for USB
arm64: zynqmmp: Add USB OTG interrupts support in dt
Michal Simek (16):
arm64: zynqmp: Add references to cpu nodes
arm64: zynqmp: Fix broken architected timer interrupt trigger
arm64: zynqmp: Add missing gpio property to dtsi
arm64: zynqmp: Use revision in dts file description
arm64: zynqmp: Add revB string to compatible string
arm64: zynqmp: Add missing alias for gem0 for ep108
arm64: zynqmp: Remove leading 0s from mtd table for spi flashes
arm64: zynqmp: Use SPDX license with dc4
arm64: zynqmp: Remove local-mac-address from dtsi file
arm64: zynqmp: Update device tree for pinmux
arm64: zynqmp: Add support for zcu102 1.0 rev
arm64: zynqmp: Remove tx_termination_fix detection on silicon v1
arm64: zynqmp: dt: Add AMS node
arm64: zynqmp: Move nodes which have no reg property out of bus
arm64: zynqmp: Remove clock setting from dtsi
arm64: zynqmp: Add note about si5328 interrupt
Naga Sureshkumar Relli (1):
arm64: zynqmp: disable smmu
Nava kishore Manne (3):
arm64: zynqmp: Label whole PL part as fpga_full region
arm64: zynqmp: rtc: Add calibration
arm64: zynqmp: Add support for zynqmp nvmem firmware driver
Rob Herring (1):
arm64: dts: xilinx: fix PCI bus dtc warnings
Shubhrajyoti Datta (2):
arm64: zynqmp: Update the OPPs for cpu freq
arm64: zynqmp: Enable watchdog by default
Soren Brinkmann (1):
arm64: zynqmp: PM: Add IRQ
arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-clk.dtsi | 2 +- arch/arm/dts/zynqmp-ep108-clk.dtsi | 2 +- arch/arm/dts/zynqmp-ep108.dts | 5 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 5 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 9 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 - arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 37 +++ arch/arm/dts/zynqmp-zcu102-revA.dts | 321 +++++++++++++++++++++++++- arch/arm/dts/zynqmp-zcu102-revB.dts | 1 + arch/arm/dts/zynqmp.dtsi | 284 +++++++++++++++-------- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 75 ++++++ include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 30 +++ 14 files changed, 653 insertions(+), 121 deletions(-) create mode 100644 arch/arm/dts/zynqmp-zcu102-rev1.0.dts create mode 100644 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h
Signature · 1 line
1.9.1
PATCH 1/40 arm64: zynqmp: Add references to cpu nodes
Add missing references to all cpu nodes.
---
arch/arm/dts/zynqmp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/dts/zynqmp.dtsi +4 -4
@@ -17,7 +17,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu at 0 { + cpu0: cpu at 0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci";
@@ -25,7 +25,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; }; - cpu at 1 { + cpu1: cpu at 1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci";
@@ -33,7 +33,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; }; - cpu at 2 { + cpu2: cpu at 2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci";
@@ -41,7 +41,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; }; - cpu at 3 { + cpu3: cpu at 3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci";
Signature · 1 line
1.9.1
PATCH 2/40 arm64: zynqmp: Update the OPPs for cpu freq
In reply to Michal SimekFrom: Shubhrajyoti Datta <[email protected]>
Add operating-points-v2.
---
arch/arm/dts/zynqmp.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
arch/arm/dts/zynqmp.dtsi +29 -0
@@ -21,6 +21,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; };
@@ -30,6 +31,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; };
@@ -38,6 +40,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; };
@@ -46,6 +49,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; };
@@ -63,6 +67,31 @@ }; }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <1199999988>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp01 { + opp-hz = /bits/ 64 <599999994>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp02 { + opp-hz = /bits/ 64 <399999996>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp03 { + opp-hz = /bits/ 64 <299999997>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + }; + dcc: dcc { compatible = "arm,dcc"; status = "disabled";
Signature · 1 line
1.9.1
PATCH 3/40 arm64: zynqmp: DT: Fix typo in idle-states node definition
In reply to Michal SimekFrom: Jyotheeswar Reddy <[email protected]>
Fixed a typo in specifying "entry-method"
---
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/dts/zynqmp.dtsi +1 -1
@@ -54,7 +54,7 @@ }; idle-states { - entry-mehod = "arm,psci"; + entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state";
Signature · 1 line
1.9.1
PATCH 4/40 arm64: zynqmp: Reduced min-residency time for idle state node
In reply to Michal SimekFrom: Jolly Shah <[email protected]>
Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0. Tried lower values 5ms and 8ms and it worked fine with Debug Off. But to accommodate PM Debug On case, 10 ms is required. With this change, low power idle state is into effect more frequently. Measured boot time with PM debugs On and Off. No change observed compared to 100ms value.
---
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/dts/zynqmp.dtsi +1 -1
@@ -62,7 +62,7 @@ local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; - min-residency-us = <800000>; + min-residency-us = <10000>; }; }; };
Signature · 1 line
1.9.1
PATCH 5/40 arm64: zynqmp: PM: Add IRQ
In reply to Michal SimekFrom: Soren Brinkmann <[email protected]>
PM callbacks are delivered to the NS OS. Let the PM driver handle the IRQ and retrieve callback data from the secure HW.
---
arch/arm/dts/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/dts/zynqmp.dtsi +2 -0
@@ -265,6 +265,8 @@ firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; }; timer {
Signature · 1 line
1.9.1
PATCH 6/40 arm64: zynqmp: Fix broken architected timer interrupt trigger
In reply to Michal SimekExtract from Linux mainline patch:
The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high.
The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs).
---
arch/arm/dts/zynqmp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/dts/zynqmp.dtsi +4 -4
@@ -272,10 +272,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; }; edac {
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1.9.1
PATCH 7/40 arm64: zynqmp: Label whole PL part as fpga_full region
In reply to Michal SimekFrom: Nava kishore Manne <[email protected]>
This will simplify dt overlay structure for the whole PL.
---
arch/arm/dts/zynqmp.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm/dts/zynqmp.dtsi +8 -1
@@ -282,7 +282,14 @@ compatible = "arm,cortex-a53-edac"; }; - pcap { + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&pcap>; + #address-cells = <2>; + #size-cells = <2>; + }; + + pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; };
Signature · 1 line
1.9.1
PATCH 8/40 arm64: zynqmp: Add clock name for GPU
In reply to Michal SimekFrom: Madhurkiran Harikrishnan <[email protected]>
This patch will add names to the clocks used by GPU.
---
arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/dts/zynqmp.dtsi +1 -0
@@ -474,6 +474,7 @@ interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; + clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; };
Signature · 1 line
1.9.1
PATCH 9/40 arm64: zynqmp: Update the GPU address size
In reply to Michal SimekFrom: Hyun Kwon <[email protected]>
The correct register size is 0x10000, otherwise
it overlaps with other register space.
---
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/dts/zynqmp.dtsi +1 -1
@@ -470,7 +470,7 @@ gpu: gpu at fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; - reg = <0x0 0xfd4b0000 0x0 0x30000>; + reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
Signature · 1 line
1.9.1
PATCH 10/40 arm64: zynqmp: Add missing gpio property to dtsi
In reply to Michal SimekAll gpio controllers should contain this property.
This property is not checked by the code that's why this issue wasn't found earlier.
---
arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/dts/zynqmp.dtsi +1 -0
@@ -672,6 +672,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; + gpio-controller; power-domains = <&pd_gpio>; };
Signature · 1 line
1.9.1
PATCH 11/40 arm64: dts: xilinx: fix PCI bus dtc warnings
In reply to Michal SimekFrom: Rob Herring <[email protected]>
dtc recently added PCI bus checks. Fix these warnings.
---
arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/dts/zynqmp.dtsi +1 -0
@@ -727,6 +727,7 @@ reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
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1.9.1
PATCH 12/40 arm64: zynqmp: Add SMMU support for SATA IP
In reply to Michal SimekFrom: Anurag Kumar Vulisha <[email protected]>
AXI master interface in CEVA AHCI controller requires two unique Write/Read ID tags per port. This is because, ahci controller uses different AXI ID[3:0] bits for identifying non-data transfers(like reading descriptors, updating PRD tables, etc) and data transfers (like sending/receiving FIS).To make SMMU work with SATA we need to add correct SMMU stream id for SATA. SMMU stream id for SATA is determined based on the AXI ID[1:0] as shown below
SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0] Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]
Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1 as said above) we get four different SMMU stream id's combinations for SATA. These AXI ID can be configured using PAXIC register. In this patch we assumed the below AXI ID values
Read ID/ Write ID for Non-Data Port0 transfers = 0 Read ID/ Write ID for Data Port0 transfers = 1 Read ID/ Write ID for Non-Data Port1 transfers = 2 Read ID/ Write ID for Data Port1 transfers = 3
Based on the above values,SMMU stream ID's for SATA will be 0x4c0 & 0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be added to iommus dts property. This patch does the same.
---
arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/dts/zynqmp.dtsi +4 -0
@@ -796,6 +796,10 @@ interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; + #stream-id-cells = <4>; + iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, + <&smmu 0x4c2>, <&smmu 0x4c3>; + /* dma-coherent; */ }; sdhci0: sdhci at ff160000 {
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1.9.1
PATCH 13/40 arm64: zynqmp: rtc: Add calibration
In reply to Michal SimekFrom: Nava kishore Manne <[email protected]>
This patch adds the calibration property with required value, calculated based on rtc input crystal oscillator frequency (32.768Khz).
---
arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/dts/zynqmp.dtsi +1 -0
@@ -764,6 +764,7 @@ interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; + calibration = <0x8000>; }; serdes: zynqmp_phy at fd400000 {
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1.9.1
PATCH 14/40 arm64: zynqmp: disable smmu
In reply to Michal SimekFrom: Naga Sureshkumar Relli <[email protected]>
This patch disables the smmu and also removes the mmu-masters
---
arch/arm/dts/zynqmp.dtsi | 27 +-------------------------- 1 file changed, 1 insertion(+), 26 deletions(-)
arch/arm/dts/zynqmp.dtsi +1 -26
@@ -835,6 +835,7 @@ compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; + status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>,
@@ -842,32 +843,6 @@ <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; - mmu-masters = < &gem0 0x874 - &gem1 0x875 - &gem2 0x876 - &gem3 0x877 - &usb0 0x860 - &usb1 0x861 - &qspi 0x873 - &lpd_dma_chan1 0x868 - &lpd_dma_chan2 0x869 - &lpd_dma_chan3 0x86a - &lpd_dma_chan4 0x86b - &lpd_dma_chan5 0x86c - &lpd_dma_chan6 0x86d - &lpd_dma_chan7 0x86e - &lpd_dma_chan8 0x86f - &fpd_dma_chan1 0x14e8 - &fpd_dma_chan2 0x14e9 - &fpd_dma_chan3 0x14ea - &fpd_dma_chan4 0x14eb - &fpd_dma_chan5 0x14ec - &fpd_dma_chan6 0x14ed - &fpd_dma_chan7 0x14ee - &fpd_dma_chan8 0x14ef - &sdhci0 0x870 - &sdhci1 0x871 - &nand0 0x872>; }; spi0: spi at ff040000 {
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1.9.1
PATCH 15/40 arm64: zynqmp: PM: Specify power domains for DP related nodes
In reply to Michal SimekFrom: Jyotheeswar Reddy Mutthareddyvari <jyothee@xhdsivadur40>
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is causing genpd to trigger a power down request for DP domain, making all DP related peripherals unusable. So assign power domains for all DP related nodes to enable proper accounting of DP power domain usage.
---
arch/arm/dts/zynqmp.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
arch/arm/dts/zynqmp.dtsi +3 -1
@@ -167,7 +167,6 @@ }; pd_dp: pd-dp { - /* fixme: what to attach to */ #power-domain-cells = <0x0>; pd-id = <0x29>; };
@@ -1014,6 +1013,7 @@ interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; + power-domains = <&pd_dp>; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>;
@@ -1063,6 +1063,7 @@ xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; + power-domains = <&pd_dp>; }; xlnx_dpdma: dma at fd4c0000 {
@@ -1072,6 +1073,7 @@ interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; + power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel {
Signature · 1 line
1.9.1
PATCH 16/40 arm64: zynqmp: Use revision in dts file description
In reply to Michal SimekTrivial change.
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/dts/zynqmp-zcu102-revA.dts +1 -1
@@ -1,5 +1,5 @@ /* - * dts file for Xilinx ZynqMP ZCU102 + * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015, Xilinx, Inc. *
Signature · 1 line
1.9.1
PATCH 17/40 arm64: zynqmp: Add revB string to compatible string
In reply to Michal SimekSome user space libraries reading platform compatible string and based on that changing behavior. Mark revB board with revB string.
---
arch/arm/dts/zynqmp-zcu102-revB.dts | 1 + 1 file changed, 1 insertion(+)
arch/arm/dts/zynqmp-zcu102-revB.dts +1 -0
@@ -12,6 +12,7 @@ / { model = "ZynqMP ZCU102 RevB"; + compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 {
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1.9.1
PATCH 18/40 arm64: zynqmp: Update device tree for gpio
In reply to Michal SimekFrom: Chirag Parekh <[email protected]>
Used defines rather than raw values for gpio configurations.
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/dts/zynqmp-zcu102-revA.dts +1 -1
@@ -60,7 +60,7 @@ compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; - gpios = <&gpio 23 0>; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; };
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1.9.1
PATCH 19/40 arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
In reply to Michal SimekFrom: Bharat Kumar Gogada <[email protected]>
- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/dts/zynqmp-zcu102-revA.dts +2 -2
@@ -168,7 +168,7 @@ gtr_sel0 { gpio-hog; gpios = <0 0>; - output-high; /* PCIE = 0, DP = 1 */ + output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 {
@@ -551,7 +551,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o }; &pcie { -/* status = "okay"; */ + status = "okay"; }; &qspi {
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1.9.1
PATCH 20/40 arm64: zynqmp: Add missing alias for gem0 for ep108
In reply to Michal SimekAdd missing alias for gem0 for ep108 to have proper sequence number.
---
arch/arm/dts/zynqmp-ep108.dts | 1 + 1 file changed, 1 insertion(+)
arch/arm/dts/zynqmp-ep108.dts +1 -0
@@ -17,6 +17,7 @@ model = "ZynqMP EP108"; aliases { + ethernet0 = &gem0; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &uart0;
Signature · 1 line
1.9.1
PATCH 21/40 arm64: zynqmp: Remove leading 0s from mtd table for spi flashes
In reply to Michal Simekdtc reports issues with it. arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node
/amba/spi at ff040000/spi0_flash0 at 0/spi0_flash0 at 00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node
/amba/spi at ff050000/spi1_flash0 at 0/spi1_flash0 at 00000000 unit name should not have leading 0sarch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node
/amba/spi at ff040000/spi0_flash0 at 0/spi0_flash0 at 00000000 unit name should not have leading 0sarch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node
/amba/spi at ff050000/spi1_flash0 at 0/spi1_flash0 at 00000000 unit name should not have leading 0s
---
arch/arm/dts/zynqmp-ep108.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/dts/zynqmp-ep108.dts +2 -2
@@ -174,7 +174,7 @@ spi-max-frequency = <50000000>; reg = <0>; - spi0_flash0 at 00000000 { + spi0_flash0 at 0 { label = "spi0_flash0"; reg = <0x0 0x100000>; };
@@ -191,7 +191,7 @@ spi-max-frequency = <50000000>; reg = <0>; - spi1_flash0 at 00000000 { + spi1_flash0 at 0 { label = "spi1_flash0"; reg = <0x0 0x100000>; };
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +2 -2
@@ -197,7 +197,7 @@ spi-max-frequency = <50000000>; reg = <0>; - spi0_flash0 at 00000000 { + spi0_flash0 at 0 { label = "spi0_flash0"; reg = <0x0 0x100000>; };
@@ -214,7 +214,7 @@ spi-max-frequency = <20000000>; reg = <0>; - spi1_flash0 at 00000000 { + spi1_flash0 at 0 { label = "spi1_flash0"; reg = <0x0 0x84000>; };
Signature · 1 line
1.9.1
PATCH 22/40 arm64: zynqmp: Use SPDX license with dc4
In reply to Michal SimekJust header change.
---
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +1 -4
@@ -5,10 +5,7 @@ * * Michal Simek <[email protected]> * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/;
Signature · 1 line
1.9.1
PATCH 23/40 arm64: zynqmp: Remove local-mac-address from dtsi file
In reply to Michal SimekGeneric dtsi file can't use the same mac address for all. U-Boot read mac from eeprom in zcu102 case and for others random mac address is generated.
---
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 4 ---- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 - arch/arm/dts/zynqmp-zcu102-revA.dts | 1 - 5 files changed, 8 deletions(-)
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +0 -1
@@ -84,7 +84,6 @@ &gem3 { status = "okay"; - local-mac-address = [00 0a 35 00 02 90]; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy at 0 {
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +0 -1
@@ -94,7 +94,6 @@ &gem2 { status = "okay"; - local-mac-address = [00 0a 35 00 02 90]; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy at 5 {
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +0 -4
@@ -136,7 +136,6 @@ &gem0 { status = "okay"; - local-mac-address = [00 0a 35 00 02 90]; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy at 0 { /* Marvell 88e1512 */
@@ -155,21 +154,18 @@ &gem1 { status = "okay"; - local-mac-address = [00 0a 35 00 02 91]; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; - local-mac-address = [00 0a 35 00 02 92]; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; - local-mac-address = [00 0a 35 00 02 93]; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; };
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +0 -1
@@ -82,7 +82,6 @@ &gem1 { status = "okay"; - local-mac-address = [00 0a 35 00 02 90]; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy at 0 {
arch/arm/dts/zynqmp-zcu102-revA.dts +0 -1
@@ -118,7 +118,6 @@ &gem3 { status = "okay"; - local-mac-address = [00 0a 35 00 02 90]; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy at 21 {
Signature · 1 line
1.9.1
PATCH 24/40 arm64: zynqmp: Update device tree for pinmux
In reply to Michal SimekAdded pin control support in device tree for zynqmp.
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 289 +++++++++++++++++++++++++++ arch/arm/dts/zynqmp.dtsi | 6 + include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 30 +++ 3 files changed, 325 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h
arch/arm/dts/zynqmp-zcu102-revA.dts +289 -0
@@ -13,6 +13,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> / { model = "ZynqMP ZCU102 RevA";
@@ -68,6 +69,8 @@ &can1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; }; &dcc {
@@ -120,6 +123,8 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy at 21 { reg = <21>; ti,rx-internal-delay = <0x8>;
@@ -130,6 +135,8 @@ &gpio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_default>; }; &gpu {
@@ -139,6 +146,11 @@ &i2c0 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio at 20 { /*
@@ -400,6 +412,12 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o &i2c1 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch at 74 { /* u34 */
@@ -549,6 +567,269 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o }; }; +&pinctrl0 { + status = "okay"; + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_14_grp", "gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp", "gpio0_15_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + mux { + groups = "gpio0_16_grp", "gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp", "gpio0_17_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_uart0_default: uart0-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_5_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_5_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO21"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO20"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + }; + + pinctrl_gem3_default: gem3-default { + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", + "MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", + "MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + }; + + pinctrl_can1_default: can1-default { + mux { + function = "can1"; + groups = "can1_6_grp"; + }; + + conf { + groups = "can1_6_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; + + pinctrl_sdhci1_default: sdhci1-default { + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-cd { + groups = "sdio1_0_cd_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_0_cd_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + mux-wp { + groups = "sdio1_0_wp_grp"; + function = "sdio1_wp"; + }; + + conf-wp { + groups = "sdio1_0_wp_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + }; + + pinctrl_gpio_default: gpio-default { + mux-sw { + function = "gpio0"; + groups = "gpio0_22_grp", "gpio0_23_grp"; + }; + + conf-sw { + groups = "gpio0_22_grp", "gpio0_23_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + mux-msp { + function = "gpio0"; + groups = "gpio0_13_grp", "gpio0_38_grp"; + }; + + conf-msp { + groups = "gpio0_13_grp", "gpio0_38_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-pull-up { + pins = "MIO22", "MIO23"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO13", "MIO38"; + bias-disable; + }; + }; +}; + &pcie { status = "okay"; };
@@ -603,21 +884,29 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o /* SD1 with level shifter */ &sdhci1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ xlnx,mio_bank = <1>; }; &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 {
arch/arm/dts/zynqmp.dtsi +6 -0
@@ -830,6 +830,12 @@ power-domains = <&pd_sd1>; }; + pinctrl0: pinctrl at ff180000 { + compatible = "xlnx,pinctrl-zynqmp"; + status = "disabled"; + reg = <0x0 0xff180000 0x0 0x1000>; + }; + smmu: smmu at fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>;
include/dt-bindings/pinctrl/pinctrl-zynqmp.h new file +30 -0
@@ -0,0 +1,30 @@ +/* +* MIO pin configuration defines for Xilinx ZynqMP +* +* Copyright (C) 2017 Xilinx, Inc. +* Author: Chirag Parekh <[email protected]> +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* version 2 as published by the Free Software Foundation. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +#define _DT_BINDINGS_PINCTRL_ZYNQMP_H + +/* Bit value for IO standards */ +#define IO_STANDARD_LVCMOS33 0 +#define IO_STANDARD_LVCMOS18 1 + +/* Bit values for Slew Rates */ +#define SLEW_RATE_FAST 0 +#define SLEW_RATE_SLOW 1 + +/* Bit values for Pin inputs */ +#define PIN_INPUT_TYPE_CMOS 0 +#define PIN_INPUT_TYPE_SCHMITT 1 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
Signature · 1 line
1.9.1
PATCH 25/40 arm64: zynqmp: Add support for zcu102 1.0 rev
In reply to Michal Simek1.0 rev is the latest rev. Describe information in eeprom.
---
arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 37 +++++++++++++ arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 75 +++++++++++++++++++++++++++ 4 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-zcu102-rev1.0.dts create mode 100644 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
arch/arm/dts/Makefile +1 -0
@@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ + zynqmp-zcu102-rev1.0.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm018-dc4.dtb \
arch/arm/dts/zynqmp-zcu102-rev1.0.dts new file +37 -0
@@ -0,0 +1,37 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 Rev1.0 + * + * (C) Copyright 2016, Xilinx, Inc. + * + * Michal Simek <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "zynqmp-zcu102-revB.dts" + +/ { + model = "ZynqMP ZCU102 Rev1.0"; + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +}; + +&eeprom { + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board_sn at 0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth_mac at 20 { + reg = <0x20 0x6>; + }; + + board_name: board_name at d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board_revision at e0 { + reg = <0xe0 0x3>; + }; +};
arch/arm/dts/zynqmp-zcu102-revA.dts +1 -1
@@ -437,7 +437,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ - eeprom at 54 { /* u23 */ + eeprom: eeprom at 54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; };
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig new file +75 -0
75 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH 26/40 arm64: zynqmp: Add support for zynqmp nvmem firmware driver
In reply to Michal SimekFrom: Nava kishore Manne <[email protected]>
Add support for zynqmp nvmem firmware driver.
---
arch/arm/dts/zynqmp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/dts/zynqmp.dtsi +10 -0
@@ -288,6 +288,16 @@ #size-cells = <2>; }; + nvmem_firmware { + compatible = "xlnx,zynqmp-nvmem-fw"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc_revision at 0 { + reg = <0x0 0x4>; + }; + }; + pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; };
Signature · 1 line
1.9.1
PATCH 27/40 arm64: zynqmp: Remove tx_termination_fix detection on silicon v1
In reply to Michal SimekOnly silicon v1 requires this termination fix. With new nvmem soc revision nvmem detection driver this can be autodetected at run time and this flag is not needed.
---
arch/arm/dts/zynqmp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm/dts/zynqmp.dtsi +2 -1
@@ -784,7 +784,8 @@ <0x0 0xfd1a0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; reg-names = "serdes", "siou", "fpd", "lpd"; - xlnx,tx_termination_fix; + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; lane0: lane0 { #phy-cells = <4>; };
Signature · 1 line
1.9.1
PATCH 28/40 arm64: zynqmp: Add reset-controller support in serdes driver
In reply to Michal SimekFrom: Anurag Kumar Vulisha <[email protected]>
This patch add the reset nodes in zynqmp.dtsi which are used by reset-controller framework
---
arch/arm/dts/zynqmp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/dts/zynqmp.dtsi +13 -0
@@ -302,6 +302,11 @@ compatible = "xlnx,zynqmp-pcap-fpga"; }; + rst: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + amba_apu: amba_apu at 0 { compatible = "simple-bus"; #address-cells = <2>;
@@ -786,6 +791,14 @@ reg-names = "serdes", "siou", "fpd", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; + resets = <&rst 16>, <&rst 59>, <&rst 60>, + <&rst 61>, <&rst 62>, <&rst 63>, + <&rst 64>, <&rst 3>, <&rst 29>, + <&rst 30>, <&rst 31>, <&rst 32>; + reset-names = "sata_rst", "usb0_crst", "usb1_crst", + "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", + "usb1_apbrst", "dp_rst", "gem0_rst", + "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; };
Signature · 1 line
1.9.1
PATCH 29/40 arm64: zynqmp: Use reset controller framework for asserting/de-asserting reset
In reply to Michal SimekFrom: Anurag Kumar Vulisha <[email protected]>
This patch modifies the phy_zynqmp.c driver to use reset-controller framework for asserting/de-asserting reset for High Speed modules.
Also fix documentation and dtsi.
---
arch/arm/dts/zynqmp.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
arch/arm/dts/zynqmp.dtsi +1 -2
@@ -786,9 +786,8 @@ status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, - <0x0 0xfd1a0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; - reg-names = "serdes", "siou", "fpd", "lpd"; + reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>,
Signature · 1 line
1.9.1
PATCH 30/40 arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon
In reply to Michal SimekFrom: Manish Narani <[email protected]>
This patch sets host quirk2 bit field for No 1.8V supported in case of 1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This property will ensure the SD runs on High Speed mode.
---
arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/dts/zynqmp.dtsi +4 -0
@@ -837,6 +837,8 @@ #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; }; sdhci1: sdhci at ff170000 {
@@ -851,6 +853,8 @@ #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; }; pinctrl0: pinctrl at ff180000 {
Signature · 1 line
1.9.1
PATCH 31/40 arm64: zynqmp: dt: Add AMS node
In reply to Michal SimekThe AMS includes an ADC as well as on-chip sensors that can be used to sample external voltages and monitor on-die operating conditions, such as temperature and supply voltage levels.
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 12 ++++++++++++ arch/arm/dts/zynqmp.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 38 insertions(+)
arch/arm/dts/zynqmp-zcu102-revA.dts +12 -0
@@ -914,6 +914,18 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o dr_mode = "host"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &xilinx_drm { status = "okay"; clocks = <&si570_1>;
arch/arm/dts/zynqmp.dtsi +26 -0
@@ -1018,6 +1018,32 @@ timeout-sec = <10>; }; + xilinx_ams: ams at ffa50000 { + compatible = "xlnx,zynqmp-ams"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 56 4>; + interrupt-names = "ams-irq"; + reg = <0x0 0xffa50000 0x0 0x800>; + reg-names = "ams-base"; + #address-cells = <2>; + #size-cells = <2>; + #io-channel-cells = <1>; + ranges; + + ams_ps: ams_ps at ffa50800 { + compatible = "xlnx,zynqmp-ams-ps"; + status = "disabled"; + reg = <0x0 0xffa50800 0x0 0x400>; + }; + + ams_pl: ams_pl at ffa50c00 { + compatible = "xlnx,zynqmp-ams-pl"; + status = "disabled"; + reg = <0x0 0xffa50c00 0x0 0x400>; + }; + }; + xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled";
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1.9.1
PATCH 32/40 arm64: zynqmp: Move nodes which have no reg property out of bus
In reply to Michal SimekNodes without reg properties shouldn't be placed in amba node. Move them out.
---
arch/arm/dts/zynqmp-clk.dtsi | 2 +- arch/arm/dts/zynqmp-ep108-clk.dtsi | 2 +- arch/arm/dts/zynqmp.dtsi | 96 +++++++++++++++++++------------------- 3 files changed, 50 insertions(+), 50 deletions(-)
arch/arm/dts/zynqmp-clk.dtsi +1 -1
@@ -8,7 +8,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -&amba { +/ { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>;
arch/arm/dts/zynqmp-ep108-clk.dtsi +1 -1
@@ -8,7 +8,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -&amba { +/ { misc_clk: misc_clk { compatible = "fixed-clock"; #clock-cells = <0>;
arch/arm/dts/zynqmp.dtsi +48 -48
114 lines not on this page · raw message
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1.9.1
PATCH 33/40 arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3
In reply to Michal SimekFrom: Anurag Kumar Vulisha <[email protected]>
This patch adds support for reading silicon revision using zynqmp nvmem driver.
---
arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/dts/zynqmp.dtsi +4 -0
@@ -1022,6 +1022,8 @@ iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; dwc3_0: dwc3 at fe200000 { compatible = "snps,dwc3";
@@ -1045,6 +1047,8 @@ iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; dwc3_1: dwc3 at fe300000 { compatible = "snps,dwc3";
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1.9.1
PATCH 34/40 arm64: zynqmp: Enabled CCI support for USB
In reply to Michal SimekFrom: Manish Narani <[email protected]>
This patch adds CCI support for USB when CCI is enabled in design. This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg' property is added in order to modify a register in that to enable coherency in Hardware.
Also add address to unit name to avoid dtc warning
---
arch/arm/dts/zynqmp.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
arch/arm/dts/zynqmp.dtsi +6 -2
@@ -1011,11 +1011,12 @@ power-domains = <&pd_uart1>; }; - usb0: usb0 { + usb0: usb0 at ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>;
@@ -1033,14 +1034,16 @@ interrupts = <0 65 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; + /* dma-coherent; */ }; }; - usb1: usb1 { + usb1: usb1 at ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>;
@@ -1058,6 +1061,7 @@ interrupts = <0 70 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; + /* dma-coherent; */ }; };
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1.9.1
PATCH 35/40 arm64: zynqmmp: Add USB OTG interrupts support in dt
In reply to Michal SimekFrom: Manish Narani <[email protected]>
This patch adds OTG interrupt support in device tree. It will add an extra interrupt line number dedicated to OTG events. This will enable OTG interrupts to serve in DWC3 OTG driver.
---
arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/dts/zynqmp.dtsi +2 -2
@@ -1031,7 +1031,7 @@ status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupts = <0 65 4>; + interrupts = <0 65 4>, <0 69 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; /* dma-coherent; */
@@ -1058,7 +1058,7 @@ status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupts = <0 70 4>; + interrupts = <0 70 4>, <0 74 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; /* dma-coherent; */
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1.9.1
PATCH 36/40 arm64: zynqmp: Uncomment snps, quirk-frame-length-adjustment flag in dwc3
In reply to Michal SimekFrom: Anurag Kumar Vulisha <[email protected]>
This patch uncomments snps,quirk-frame-length-adjustment which has the value to adjust the SOF/ITP generated from the controller.
---
arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/dts/zynqmp.dtsi +2 -2
@@ -1032,7 +1032,7 @@ reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>; - /* snps,quirk-frame-length-adjustment = <0x20>; */ + snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; /* dma-coherent; */ };
@@ -1059,7 +1059,7 @@ reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>; - /* snps,quirk-frame-length-adjustment = <0x20>; */ + snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; /* dma-coherent; */ };
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1.9.1
PATCH 37/40 arm64: zynqmp: Remove clock setting from dtsi
In reply to Michal Simekclock setting is handled via clk dtsi file.
---
arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-)
arch/arm/dts/zynqmp.dtsi +0 -2
@@ -1018,7 +1018,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; power-domains = <&pd_usb0>;
@@ -1045,7 +1044,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; power-domains = <&pd_usb1>;
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1.9.1
PATCH 38/40 arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USB
In reply to Michal SimekFrom: Anurag Kumar Vulisha <[email protected]>
This patch makes SMMU work by moving the iommus node under the dwc3 child entry from parent node.
---
arch/arm/dts/zynqmp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/dts/zynqmp.dtsi +4 -4
@@ -1018,8 +1018,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - #stream-id-cells = <1>; - iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>;
@@ -1031,6 +1029,8 @@ reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>; + #stream-id-cells = <1>; + iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; /* dma-coherent; */
@@ -1044,8 +1044,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - #stream-id-cells = <1>; - iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>;
@@ -1057,6 +1055,8 @@ reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>; + #stream-id-cells = <1>; + iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; /* dma-coherent; */
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1.9.1
PATCH 39/40 arm64: zynqmp: Add note about si5328 interrupt
In reply to Michal SimekAdd comment about irq present on the board connected to PL.
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/dts/zynqmp-zcu102-revA.dts +5 -0
@@ -485,6 +485,11 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o si5328: clock-generator4 at 69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ }; }; /* 5 - 7 unconnected */
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1.9.1
PATCH 40/40 arm64: zynqmp: Enable watchdog by default
In reply to Michal SimekFrom: Shubhrajyoti Datta <[email protected]>
Enable watchdog in dts for zcu102.
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/dts/zynqmp-zcu102-revA.dts +4 -0
@@ -919,6 +919,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o dr_mode = "host"; }; +&watchdog0 { + status = "okay"; +}; + &xilinx_ams { status = "okay"; };
Signature · 1 line
1.9.1