meson8b-odroidc1: ethernet support

Enable S805 (aka Meson8b) ethernet pin multiplexing and extend the controller description.
The programmable ethernet (PRG_ETHERNET) register address value (0xc1108108), contained in meson.dtsi, is overridden according to the value found in S805 SoC manual.
This also required to switch to "amlogic,meson8b-dwmac" compatible to correctly configure that register.
The two clock sources "clkin0" and "clkin1" are both equals to MPLL2 because, as reported in bit 9-7 register description, that is the only Meson8b ethernet clock source.

Signed-off-by Emiliano Ingrassia <[email protected]>

Enable S805 (aka Meson8b) ethernet pin multiplexing and extend the controller description.
The programmable ethernet (PRG_ETHERNET) register address value (0xc1108108), contained in meson.dtsi, is overridden according to the value found in S805 SoC manual.
This also required to switch to "amlogic,meson8b-dwmac" compatible to correctly configure that register.
The two clock sources "clkin0" and "clkin1" are both equals to MPLL2 because, as reported in bit 9-7 register description, that is the only Meson8b ethernet clock source.

Signed-off-by Emiliano Ingrassia <[email protected]>

---
 arch/arm/boot/dts/meson8b.dtsi | 35 +++++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

arch/arm/boot/dts/meson8b.dtsi +33 -3

index d75e0ceda8bb..fa5274aa370b 100644
@@ -185,6 +185,27 @@
                        #gpio-cells = <2>;
                        gpio-ranges = <&pinctrl_cbus 0 0 130>;
                };
+
+               eth_rgmii_pins: eth-rgmii {
+                       mux {
+                               groups = "eth_tx_clk",
+                                        "eth_tx_en",
+                                        "eth_txd1_0",
+                                        "eth_txd1_1",
+                                        "eth_txd0_0",
+                                        "eth_txd0_1",
+                                        "eth_rx_clk",
+                                        "eth_rx_dv",
+                                        "eth_rxd1",
+                                        "eth_rxd0",
+                                        "eth_mdio_en",
+                                        "eth_mdc",
+                                        "eth_ref_clk",
+                                        "eth_txd2",
+                                        "eth_txd3";
+                               function = "ethernet";
+                       };
+               };
        };
 };
 

@@ -203,8 +224,18 @@
 };
 
 &ethmac {
-       clocks = <&clkc CLKID_ETH>;
-       clock-names = "stmmaceth";
+       compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
+
+       reg = <0xc9410000 0x10000
+              0xc1108140 0x4>;
+
+       clocks = <&clkc CLKID_ETH>,
+                <&clkc CLKID_MPLL2>,
+                <&clkc CLKID_MPLL2>;
+       clock-names = "stmmaceth", "clkin0", "clkin1";
+
+       resets = <&reset RESET_ETHERNET>;
+       reset-names = "stmmaceth";
 };
 
 &gpio_intc {
--

2.15.1

The Odroid-C1+ board is equipped with an RTL8211F ethernet PHY which supports 10/100/1000 Mbps ethernet.
The PHY reset and interrupt lines are controlled by the SoC via two GPIO lines (GPIOH_4 and GPIOH_3 respectively).
The PHY energy efficient ethernet (eee) mode is marked as broken using "eee-broken-1000t" because, during tests, high packet losses were experienced without it.

Signed-off-by Emiliano Ingrassia <[email protected]>

Hi Emiliano,

Quoted 9 lines · Emiliano Ingrassia

The Odroid-C1+ board is equipped with an RTL8211F ethernet PHY which supports 10/100/1000 Mbps ethernet.
The PHY reset and interrupt lines are controlled by the SoC via two GPIO lines (GPIOH_4 and GPIOH_3 respectively).
The PHY energy efficient ethernet (eee) mode is marked as broken using "eee-broken-1000t" because, during tests, high packet losses were experienced without it.

Signed-off-by Emiliano Ingrassia <[email protected]>

I tested your patches on a 4.15-rc8 kernel with the following patches on top:

f120580deba4 ARM: dts: meson8b-odroidc1: ethernet support
22a6d87b9ee2 ARM: dts: meson8b: extend ethernet controller description 6d053e5f1f3b net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock 8a5f3df5bcfa net: stmmac: dwmac-meson8b: fix setting the RGMII TX clock on Meson8b c045d6785ec7 net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration 6b63adce0b60 net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode 9e8946eda815 clk: meson: mpll: use 64-bit maths in params_from_rate

And config file created via multiv7_defconfig.

I tested against a laptop with an Intel Core2Duo and an Intel 82567LM Gigabit network card.

These are the results I get with iperf3, running for 120s for each test:

# Direct Gigabit connection between Odroid C1+ and the laptop:

Odroid C1+ -> Laptop: 646MBit/s
Laptop -> Odroid C1+: 239MBit/s

# 100Mbit forced via 'ethtool advertise 0x008' on laptop:

Odroid C1+ -> Laptop: 84.6MBit/s
Laptop -> Odroid C1+: 52.7MBit/s

# Connection with a Gigabit switch in between:

Odroid C1+ -> GBit-SW -> Laptop: 626MBit/s
Laptop -> GBit-SW -> Odroid C1+: 248MBit/s

# Connection with a 100MBit switch in between:

Odroid C1+ -> 100MBit-SW -> Laptop: 91.7MBit/s
Laptop -> 100MBit-SW -> Odroid C1+: 43.7MBit/s

Not quite sure why RX is somehow slower than TX on the C1+. But other than that looks great :-). Many thanks to everyone who had contributed!

Tested-by Linus L?ssing <[email protected]>

The Odroid-C1+ board is equipped with an RTL8211F ethernet PHY which supports 10/100/1000 Mbps ethernet.
The PHY reset and interrupt lines are controlled by the SoC via two GPIO lines (GPIOH_4 and GPIOH_3 respectively).
The PHY energy efficient ethernet (eee) mode is marked as broken using "eee-broken-1000t" because, during tests, high packet losses were experienced without it.

Signed-off-by Emiliano Ingrassia <[email protected]>

---
 arch/arm/boot/dts/meson8b-odroidc1.dts | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

arch/arm/boot/dts/meson8b-odroidc1.dts +30 -1

index 9ff6ca4e20d0..d5e83051bb54 100644
@@ -99,3 +99,33 @@
 &usb1 {
        status = "okay";
 };
+
+&ethmac {
+       status = "okay";
+
+       snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 30000>;
+
+       pinctrl-0 = <&eth_rgmii_pins>;
+       pinctrl-names = "default";
+
+       phy-mode = "rgmii";
+       phy-handle = <&eth_phy>;
+       amlogic,tx-delay-ns = <4>;
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               /* Realtek RTL8211F (0x001cc916) */
+               eth_phy: ethernet-phy at 0 {
+                       reg = <0>;
+                       eee-broken-1000t;
+                       interrupt-parent = <&gpio_intc>;
+                       /* GPIOH_3 */
+                       interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
+};
--

2.15.1

This patchset, tested on an Odroid-C1+ board, enables ethernet support on Odroid-C1/C1+ boards, improving and extending the ethernet description in the relative device tree.

In particular:
- enables the Meson8b ethernet controller pin multiplexing;
- fixes and extends the Meson8b ethernet controller description;
- adds the Odroid-C1+ ethernet PHY description and enables the ethernet controller.

This patchset depends on patchset "dwmac-meson8b: clock fixes for Meson8b".