PCI: dwc: Enables MSI-X driver support
Subsystems (3)
v11 cover PCI: dwc: Enables MSI-X driver support
Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct msi_controller based API.
Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation.
The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed over 8 controller registers, therefore the maximum number of MSI IRQs can be changed to 256. The number of controllers can be calculated based on the number of vectors used by the specific SoC driver.
Adds Synopsys Root Complex driver support for MSI-X feature.
The patch set was made against the Bjorn's master branch (v4.16-rc1).
Gustavo Pimentel (4):
PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API
PCI: dwc: Remove old MSI IRQs API
PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256
PCI: dwc: Code cleanup
drivers/pci/dwc/pci-exynos.c | 18 -- drivers/pci/dwc/pci-imx6.c | 18 -- drivers/pci/dwc/pci-keystone-dw.c | 91 +------ drivers/pci/dwc/pci-keystone.c | 1 + drivers/pci/dwc/pci-keystone.h | 4 +- drivers/pci/dwc/pci-layerscape.c | 3 +- drivers/pci/dwc/pcie-artpec6.c | 18 -- drivers/pci/dwc/pcie-designware-host.c | 446 +++++++++++++++++++-------------- drivers/pci/dwc/pcie-designware-plat.c | 22 +- drivers/pci/dwc/pcie-designware.h | 31 ++- drivers/pci/dwc/pcie-histb.c | 15 -- drivers/pci/dwc/pcie-qcom.c | 16 -- 12 files changed, 292 insertions(+), 391 deletions(-)
Signature · 1 line
2.7.4
PATCH v11 1/4 PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API
Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct msi_controller based API.
Although the old implementation API is still available, pcie-designware will now use the multiplexed IRQ domains hierarchical API.
Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation.
---
Change v1->v2:
- num_vectors is now not configurable by the Device Tree. Now it is 32 by default and can be overridden by any specific SoC driver. Change v2->v3:
- Nothing changed, just to follow the patch set version.
Change v3->v4:
- Moved Kishon's fixes (PCI end point error and a dra7xx warning) from v3-0007 patch file to here.
- Undo the change of the function signature to be more coherent with the host mode specific functions (Thanks Kishon).
- Refactor the added functions in order to used host_data so that getting pp again back from pci could be avoided. (Thanks Kishon)
- Changed summary line to match the drivers/PCI convention and changelog to maintain the consistency (thanks Bjorn).
Change v4->v5:
- Implemented Kishon MSI multiple messages fix (thanks Kishon). Change v5->v6:
- Fixed rebase problem detected by Niklas (thanks Niklas). Change v6->v7:
- Implemented Marc review suggestions (thanks Marc).
Change v7->v8:
- Rebased against v4.16-rc1.
Change v8->v9:
- Squashed all patches [2-7] into this, following Lorenzo sugestion (thanks Lorenzo).
Change v9->v10:
- Log commit rewrite to be accurate by Lorenzo (thanks Lorenzo).
- Fixed kbuild test robot warning relatively to the raw_spin_lock.
- Extended patch fix to pcie-histb driver.
Change v10->v11:
- Replace unsign to sign variable type mistake (thanks Lucas).
drivers/pci/dwc/pci-exynos.c | 18 -- drivers/pci/dwc/pci-imx6.c | 18 -- drivers/pci/dwc/pci-keystone-dw.c | 89 +--------- drivers/pci/dwc/pci-keystone.c | 1 + drivers/pci/dwc/pci-keystone.h | 1 + drivers/pci/dwc/pcie-artpec6.c | 18 -- drivers/pci/dwc/pcie-designware-host.c | 294 +++++++++++++++++++++++++++++---- drivers/pci/dwc/pcie-designware-plat.c | 16 -- drivers/pci/dwc/pcie-designware.h | 18 ++ drivers/pci/dwc/pcie-histb.c | 15 -- drivers/pci/dwc/pcie-qcom.c | 16 -- 11 files changed, 290 insertions(+), 214 deletions(-)
drivers/pci/dwc/pci-exynos.c +0 -18
@@ -294,15 +294,6 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)return IRQ_HANDLED ; } -static irqreturn_t exynos_pcie_msi_irq_handler (int irq,void *arg) -{ -struct exynos_pcie *ep = arg; -struct dw_pcie *pci = ep->pci; -struct pcie_port *pp = &pci->pp; - -return dw_handle_msi_irq (pp); -} -static void exynos_pcie_msi_init (struct exynos_pcie *ep) {struct dw_pcie *pci = ep->pci;
@@ -428,15 +419,6 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep,dev_err (dev,"failed to get msi irq\n" );return pp->msi_irq; } - - ret =devm_request_irq (dev, pp->msi_irq, - exynos_pcie_msi_irq_handler, -IRQF_SHARED |IRQF_NO_THREAD , -"exynos-pcie" , ep); -if (ret) { -dev_err (dev,"failed to request msi irq\n" ); -return ret; - } } pp->root_bus_nr =-1 ;
drivers/pci/dwc/pci-imx6.c +0 -18
@@ -542,15 +542,6 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)return -EINVAL ; } -static irqreturn_t imx6_pcie_msi_handler (int irq,void *arg) -{ -struct imx6_pcie *imx6_pcie = arg; -struct dw_pcie *pci = imx6_pcie->pci; -struct pcie_port *pp = &pci->pp; - -return dw_handle_msi_irq (pp); -} -static int imx6_pcie_establish_link (struct imx6_pcie *imx6_pcie) {struct dw_pcie *pci = imx6_pcie->pci;
@@ -674,15 +665,6 @@ static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,dev_err (dev,"failed to get MSI irq\n" );return -ENODEV ; } - - ret =devm_request_irq (dev, pp->msi_irq, - imx6_pcie_msi_handler, -IRQF_SHARED |IRQF_NO_THREAD , -"mx6-pcie-msi" , imx6_pcie); -if (ret) { -dev_err (dev,"failed to request MSI irq\n" ); -return ret; - } } pp->root_bus_nr =-1 ;
drivers/pci/dwc/pci-keystone-dw.c +4 -85
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drivers/pci/dwc/pci-keystone.c +1 -0
@@ -297,6 +297,7 @@ static const struct dw_pcie_host_ops keystone_pcie_host_ops = { .msi_clear_irq = ks_dw_pcie_msi_clear_irq, .get_msi_addr = ks_dw_pcie_get_msi_addr, .msi_host_init = ks_dw_pcie_msi_host_init, + .msi_irq_ack = ks_dw_pcie_msi_irq_ack, .scan_bus = ks_dw_pcie_v3_65_scan_bus, };
drivers/pci/dwc/pci-keystone.h +1 -0
@@ -49,6 +49,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);void ks_dw_pcie_setup_rc_app_regs (struct keystone_pcie *ks_pcie);void ks_dw_pcie_initiate_link_train (struct keystone_pcie *ks_pcie); +void ks_dw_pcie_msi_irq_ack (int i,struct pcie_port *pp);void ks_dw_pcie_msi_set_irq (struct pcie_port *pp,int irq);void ks_dw_pcie_msi_clear_irq (struct pcie_port *pp,int irq);void ks_dw_pcie_v3_65_scan_bus (struct pcie_port *pp);
drivers/pci/dwc/pcie-artpec6.c +0 -18
@@ -383,15 +383,6 @@ static const struct dw_pcie_host_ops artpec6_pcie_host_ops = { .host_init = artpec6_pcie_host_init, }; -static irqreturn_t artpec6_pcie_msi_handler (int irq,void *arg) -{ -struct artpec6_pcie *artpec6_pcie = arg; -struct dw_pcie *pci = artpec6_pcie->pci; -struct pcie_port *pp = &pci->pp; - -return dw_handle_msi_irq (pp); -} -static int artpec6_add_pcie_port (struct artpec6_pcie *artpec6_pcie,struct platform_device *pdev) {
@@ -406,15 +397,6 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,dev_err (dev,"failed to get MSI irq\n" );return pp->msi_irq; } - - ret =devm_request_irq (dev, pp->msi_irq, - artpec6_pcie_msi_handler, -IRQF_SHARED |IRQF_NO_THREAD , -"artpec6-pcie-msi" , artpec6_pcie); -if (ret) { -dev_err (dev,"failed to request MSI irq\n" ); -return ret; - } } pp->root_bus_nr =-1 ;
drivers/pci/dwc/pcie-designware-host.c +266 -28
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drivers/pci/dwc/pcie-designware-plat.c +0 -16
@@ -25,13 +25,6 @@ struct dw_plat_pcie {struct dw_pcie *pci; }; -static irqreturn_t dw_plat_pcie_msi_irq_handler (int irq,void *arg) -{ -struct pcie_port *pp = arg; - -return dw_handle_msi_irq (pp); -} -static int dw_plat_pcie_host_init (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp);
@@ -63,15 +56,6 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp, pp->msi_irq =platform_get_irq (pdev,0 );if (pp->msi_irq <0 )return pp->msi_irq; - - ret =devm_request_irq (dev, pp->msi_irq, - dw_plat_pcie_msi_irq_handler, -IRQF_SHARED |IRQF_NO_THREAD , -"dw-plat-pcie-msi" , pp); -if (ret) { -dev_err (dev,"failed to request MSI IRQ\n" ); -return ret; - } } pp->root_bus_nr =-1 ;
drivers/pci/dwc/pcie-designware.h +18 -0
@@ -114,6 +114,7 @@*/ #define MAX_MSI_IRQS 32#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) +#define MSI_DEF_NUM_VECTORS 32/* Maximum number of inbound/outbound iATUs */ #define MAX_IATU_IN 256
@@ -149,7 +150,9 @@ struct dw_pcie_host_ops {phys_addr_t (*get_msi_addr)(struct pcie_port *pp);u32 (*get_msi_data)(struct pcie_port *pp,int pos);void (*scan_bus)(struct pcie_port *pp); +void (*set_num_vectors)(struct pcie_port *pp);int (*msi_host_init)(struct pcie_port *pp,struct msi_controller *chip); +void (*msi_irq_ack)(int irq,struct pcie_port *pp); };struct pcie_port {
@@ -174,7 +177,11 @@ struct pcie_port {const struct dw_pcie_host_ops *ops;int msi_irq;struct irq_domain *irq_domain; +struct irq_domain *msi_domain;dma_addr_t msi_data; +u32 num_vectors; +u32 irq_status[MAX_MSI_CTRLS ]; +raw_spinlock_t lock;DECLARE_BITMAP (msi_irq_in_use,MAX_MSI_IRQS ); };
@@ -316,8 +323,10 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)#ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq (struct pcie_port *pp);void dw_pcie_msi_init (struct pcie_port *pp); +void dw_pcie_free_msi (struct pcie_port *pp);void dw_pcie_setup_rc (struct pcie_port *pp);int dw_pcie_host_init (struct pcie_port *pp); +int dw_pcie_allocate_domains (struct pcie_port *pp);#else static inline irqreturn_t dw_handle_msi_irq (struct pcie_port *pp) {
@@ -328,6 +337,10 @@ static inline void dw_pcie_msi_init(struct pcie_port *pp) { } +static inline void dw_pcie_free_msi (struct pcie_port *pp) +{ +} +static inline void dw_pcie_setup_rc (struct pcie_port *pp) { }
@@ -336,6 +349,11 @@ static inline int dw_pcie_host_init(struct pcie_port *pp) {return 0 ; } + +static inline int dw_pcie_allocate_domains (struct pcie_port *pp) +{ +return 0 ; +}#endif #ifdef CONFIG_PCIE_DW_EP
drivers/pci/dwc/pcie-histb.c +0 -15
@@ -207,13 +207,6 @@ static struct dw_pcie_host_ops histb_pcie_host_ops = { .host_init = histb_pcie_host_init, }; -static irqreturn_t histb_pcie_msi_irq_handler (int irq,void *arg) -{ -struct pcie_port *pp = arg; - -return dw_handle_msi_irq (pp); -} -static void histb_pcie_host_disable (struct histb_pcie *hipcie) {reset_control_assert (hipcie->soft_reset);
@@ -393,14 +386,6 @@ static int histb_pcie_probe(struct platform_device *pdev)dev_err (dev,"Failed to get MSI IRQ\n" );return pp->msi_irq; } - - ret =devm_request_irq (dev, pp->msi_irq, - histb_pcie_msi_irq_handler, -IRQF_SHARED ,"histb-pcie-msi" , pp); -if (ret) { -dev_err (dev,"cannot request MSI IRQ\n" ); -return ret; - } } hipcie->phy =devm_phy_get (dev,"phy" );
drivers/pci/dwc/pcie-qcom.c +0 -16
@@ -180,13 +180,6 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)usleep_range (PERST_DELAY_US ,PERST_DELAY_US +500 ); } -static irqreturn_t qcom_pcie_msi_irq_handler (int irq,void *arg) -{ -struct pcie_port *pp = arg; - -return dw_handle_msi_irq (pp); -} -static int qcom_pcie_establish_link (struct qcom_pcie *pcie) {struct dw_pcie *pci = pcie->pci;
@@ -1262,15 +1255,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) pp->msi_irq =platform_get_irq_byname (pdev,"msi" );if (pp->msi_irq <0 )return pp->msi_irq; - - ret =devm_request_irq (dev, pp->msi_irq, - qcom_pcie_msi_irq_handler, -IRQF_SHARED |IRQF_NO_THREAD , -"qcom-pcie-msi" , pp); -if (ret) { -dev_err (dev,"cannot request msi irq\n" ); -return ret; - } } ret =phy_init (pcie->phy);
Signature · 1 line
2.7.4
PATCH v11 2/4 PCI: dwc: Remove old MSI IRQs API
In reply to Gustavo PimentelRemove the unused old MSI IRQs API from pcie-designware based on struct msi_controller that should now be considered obsolete.
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Change v3->v4:
- Patch renamed from v3-0008 to v4-0009.
- Changed summary line to match the drivers/PCI convention and changelog to maintain the consistency (thanks Bjorn).
Change v4->v5:
- Nothing changed, just to follow the patch set version.
Change v5->v6:
- Nothing changed, just to follow the patch set version.
Change v6->v7:
- Nothing changed, just to follow the patch set version.
Change v7->v8:
- Rebased against v4.16-rc1.
Change v8->v9:
- Changed patch indexation, due patch series squash.
Change v9->v10:
- Log commit rewrite to be accurate by Lorenzo (thanks Lorenzo). Change v10->v11:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pci-keystone-dw.c | 2 +- drivers/pci/dwc/pci-keystone.h | 3 +- drivers/pci/dwc/pci-layerscape.c | 3 +- drivers/pci/dwc/pcie-designware-host.c | 190 +-------------------------------- drivers/pci/dwc/pcie-designware.h | 2 +- 5 files changed, 5 insertions(+), 195 deletions(-)
drivers/pci/dwc/pci-keystone-dw.c +1 -1
@@ -157,7 +157,7 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) BIT(bit_pos)); } -int ks_dw_pcie_msi_host_init (struct pcie_port *pp,struct msi_controller *chip) +int ks_dw_pcie_msi_host_init (struct pcie_port *pp) {return dw_pcie_allocate_domains (pp); }
drivers/pci/dwc/pci-keystone.h +1 -2
@@ -53,6 +53,5 @@ void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);void ks_dw_pcie_msi_set_irq (struct pcie_port *pp,int irq);void ks_dw_pcie_msi_clear_irq (struct pcie_port *pp,int irq);void ks_dw_pcie_v3_65_scan_bus (struct pcie_port *pp); -int ks_dw_pcie_msi_host_init (struct pcie_port *pp, -struct msi_controller *chip); +int ks_dw_pcie_msi_host_init (struct pcie_port *pp);int ks_dw_pcie_link_up (struct dw_pcie *pci);
drivers/pci/dwc/pci-layerscape.c +1 -2
@@ -182,8 +182,7 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)return ls_pcie_host_init (pp); } -static int ls_pcie_msi_host_init (struct pcie_port *pp, -struct msi_controller *chip) +static int ls_pcie_msi_host_init (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp);struct device *dev = pci->dev;
drivers/pci/dwc/pcie-designware-host.c +1 -189
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drivers/pci/dwc/pcie-designware.h +1 -1
@@ -151,7 +151,7 @@ struct dw_pcie_host_ops {u32 (*get_msi_data)(struct pcie_port *pp,int pos);void (*scan_bus)(struct pcie_port *pp);void (*set_num_vectors)(struct pcie_port *pp); -int (*msi_host_init)(struct pcie_port *pp,struct msi_controller *chip); +int (*msi_host_init)(struct pcie_port *pp);void (*msi_irq_ack)(int irq,struct pcie_port *pp); };
Signature · 1 line
2.7.4
PATCH v11 3/4 PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256
In reply to Gustavo PimentelThe Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed over 8 controller registers, therefore the maximum number of MSI IRQs can be changed to 256. The number of controllers can be calculated based on the number of vectors used by the specific SoC driver.
Update the dwc host bridge driver maximum number of supported MSI IRQs.
---
Change v1->v2:
- New patch file.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Change v3->v4:
- Patch renamed from v3-0009 to v4-0010.
- Changed summary line to match the drivers/PCI convention and changelog to maintain the consistency (thanks Bjorn).
Change v4->v5:
- Nothing changed, just to follow the patch set version.
Change v5->v6:
- Nothing changed, just to follow the patch set version.
Change v6->v7:
- Nothing changed, just to follow the patch set version.
Change v7->v8:
- Rebased against v4.16-rc1.
Change v8->v9:
- Changed patch indexation, due patch series squash.
Change v9->v10:
- Log commit rewrite to be accurate by Lorenzo (thanks Lorenzo). Change v10->v11:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-host.c | 12 ++++++++---- drivers/pci/dwc/pcie-designware.h | 10 +++------- 2 files changed, 11 insertions(+), 11 deletions(-)
drivers/pci/dwc/pcie-designware-host.c +8 -4
@@ -76,11 +76,13 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {/* MSI int handler */ irqreturn_t dw_handle_msi_irq (struct pcie_port *pp) { -u32 val;int i, pos, irq; +u32 val, num_ctrls;irqreturn_t ret =IRQ_NONE ; -for (i =0 ; i <MAX_MSI_CTRLS ; i++) { + num_ctrls = pp->num_vectors /MAX_MSI_IRQS_PER_CTRL ; + +for (i =0 ; i < num_ctrls; i++) {dw_pcie_rd_own_conf (pp,PCIE_MSI_INTR0_STATUS + i *12 ,4 , &val);if (!val)
@@ -639,13 +641,15 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)void dw_pcie_setup_rc (struct pcie_port *pp) { -u32 val, ctrl; +u32 val, ctrl, num_ctrls;struct dw_pcie *pci =to_dw_pcie_from_pp (pp);dw_pcie_setup (pci); + num_ctrls = pp->num_vectors /MAX_MSI_IRQS_PER_CTRL ; +/* Initialize IRQ Status array */ -for (ctrl =0 ; ctrl <MAX_MSI_CTRLS ; ctrl++) +for (ctrl =0 ; ctrl < num_ctrls; ctrl++)dw_pcie_rd_own_conf (pp,PCIE_MSI_INTR0_ENABLE + (ctrl *12 ),4 , &pp->irq_status[ctrl]);/* setup RC BARs */
drivers/pci/dwc/pcie-designware.h +3 -7
@@ -107,13 +107,9 @@#define MSI_MESSAGE_DATA_32 0x58#define MSI_MESSAGE_DATA_64 0x5C -/* -* Maximum number of MSI IRQs can be 256 per controller. But keep -* it 32 as of now. Probably we will never need more than 32. If needed, -* then increment it in multiple of 32. -*/ -#define MAX_MSI_IRQS 32 -#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) +#define MAX_MSI_IRQS 256 +#define MAX_MSI_IRQS_PER_CTRL 32 +#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)#define MSI_DEF_NUM_VECTORS 32/* Maximum number of inbound/outbound iATUs */
Signature · 1 line
2.7.4
PATCH v11 4/4 PCI: dwc: Code cleanup
In reply to Gustavo PimentelReplace magic numbers by a well known define in order to make the code human readable and also facilitate the code reusability.
Add a callback to define the number of vectors as an example.
Exchange lower case into upper case in comments and debug printks.
--- drivers/pci/dwc/pcie-designware-host.c | 74 +++++++++++++++++++--------------- drivers/pci/dwc/pcie-designware-plat.c | 6 +++ drivers/pci/dwc/pcie-designware.h | 1 + 3 files changed, 48 insertions(+), 33 deletions(-)
drivers/pci/dwc/pcie-designware-host.c +41 -33
@@ -83,18 +83,23 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) num_ctrls = pp->num_vectors /MAX_MSI_IRQS_PER_CTRL ;for (i =0 ; i < num_ctrls; i++) { -dw_pcie_rd_own_conf (pp,PCIE_MSI_INTR0_STATUS + i *12 ,4 , - &val); +dw_pcie_rd_own_conf (pp,PCIE_MSI_INTR0_STATUS + + (i *MSI_REG_CTRL_BLOCK_SIZE ), +4 , &val);if (!val)continue ; ret =IRQ_HANDLED ; pos =0 ; -while ((pos =find_next_bit ((unsigned long *) &val,32 , - pos)) !=32 ) { - irq =irq_find_mapping (pp->irq_domain, i *32 + pos); +while ((pos =find_next_bit ((unsigned long *) &val, +MAX_MSI_IRQS_PER_CTRL , + pos)) !=MAX_MSI_IRQS_PER_CTRL ) { + irq =irq_find_mapping (pp->irq_domain, + (i *MAX_MSI_IRQS_PER_CTRL ) + + pos);generic_handle_irq (irq); -dw_pcie_wr_own_conf (pp,PCIE_MSI_INTR0_STATUS + i *12 , +dw_pcie_wr_own_conf (pp,PCIE_MSI_INTR0_STATUS + + (i *MSI_REG_CTRL_BLOCK_SIZE ),4 ,1 << pos); pos++; }
@@ -157,9 +162,9 @@ static void dw_pci_bottom_mask(struct irq_data *data)if (pp->ops->msi_clear_irq) { pp->ops->msi_clear_irq (pp, data->hwirq); }else { - ctrl = data->hwirq /32 ; - res = ctrl *12 ; - bit = data->hwirq %32 ; + ctrl = data->hwirq /MAX_MSI_IRQS_PER_CTRL ; + res = ctrl *MSI_REG_CTRL_BLOCK_SIZE ; + bit = data->hwirq %MAX_MSI_IRQS_PER_CTRL ; pp->irq_status[ctrl] &= ~(1 << bit); dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
@@ -180,9 +185,9 @@ static void dw_pci_bottom_unmask(struct irq_data *data)if (pp->ops->msi_set_irq) { pp->ops->msi_set_irq (pp, data->hwirq); }else { - ctrl = data->hwirq /32 ; - res = ctrl *12 ; - bit = data->hwirq %32 ; + ctrl = data->hwirq /MAX_MSI_IRQS_PER_CTRL ; + res = ctrl *MSI_REG_CTRL_BLOCK_SIZE ; + bit = data->hwirq %MAX_MSI_IRQS_PER_CTRL ; pp->irq_status[ctrl] |=1 << bit; dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
@@ -248,8 +253,10 @@ static void dw_pcie_irq_domain_free(struct irq_domain *domain,unsigned long flags;raw_spin_lock_irqsave (&pp->lock, flags); +bitmap_release_region (pp->msi_irq_in_use, data->hwirq,order_base_2 (nr_irqs)); +raw_spin_unlock_irqrestore (&pp->lock, flags); }
@@ -266,7 +273,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) pp->irq_domain =irq_domain_create_linear (fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp);if (!pp->irq_domain) { -dev_err (pci->dev,"failed to create IRQ domain\n" ); +dev_err (pci->dev,"Failed to create IRQ domain\n" );return -ENOMEM ; }
@@ -274,7 +281,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) &dw_pcie_msi_domain_info, pp->irq_domain);if (!pp->msi_domain) { -dev_err (pci->dev,"failed to create MSI domain\n" ); +dev_err (pci->dev,"Failed to create MSI domain\n" );irq_domain_remove (pp->irq_domain);return -ENOMEM ; }
@@ -307,7 +314,7 @@ void dw_pcie_msi_init(struct pcie_port *pp) } msi_target = (u64 )pp->msi_data; -/* program the msi_data */ +/* Program the msi_data */ dw_pcie_wr_own_conf (pp,PCIE_MSI_ADDR_LO ,4 ,lower_32_bits (msi_target)); dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
@@ -330,12 +337,12 @@ int dw_pcie_host_init(struct pcie_port *pp) cfg_res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"config" );if (cfg_res) { - pp->cfg0_size =resource_size (cfg_res) /2 ; - pp->cfg1_size =resource_size (cfg_res) /2 ; + pp->cfg0_size =resource_size (cfg_res) >>1 ; + pp->cfg1_size =resource_size (cfg_res) >>1 ; pp->cfg0_base = cfg_res->start; pp->cfg1_base = cfg_res->start + pp->cfg0_size; }else if (!pp->va_cfg0_base) { -dev_err (dev,"missing *config* reg space\n" ); +dev_err (dev,"Missing *config* reg space\n" ); } bridge =pci_alloc_host_bridge (0 );
@@ -357,7 +364,7 @@ int dw_pcie_host_init(struct pcie_port *pp)case IORESOURCE_IO : ret =pci_remap_iospace (win->res, pp->io_base);if (ret) { -dev_warn (dev,"error %d: failed to map resource %pR\n" , +dev_warn (dev,"Error %d: failed to map resource %pR\n" , ret, win->res);resource_list_destroy_entry (win); }else {
@@ -375,8 +382,8 @@ int dw_pcie_host_init(struct pcie_port *pp)break ;case 0 : pp->cfg = win->res; - pp->cfg0_size =resource_size (pp->cfg) /2 ; - pp->cfg1_size =resource_size (pp->cfg) /2 ; + pp->cfg0_size =resource_size (pp->cfg) >>1 ; + pp->cfg1_size =resource_size (pp->cfg) >>1 ; pp->cfg0_base = pp->cfg->start; pp->cfg1_base = pp->cfg->start + pp->cfg0_size;break ;
@@ -391,7 +398,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg->start, resource_size(pp->cfg));if (!pci->dbi_base) { -dev_err (dev,"error with ioremap\n" ); +dev_err (dev,"Error with ioremap\n" ); ret = -ENOMEM ; goto error; }
@@ -403,7 +410,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->va_cfg0_base =devm_pci_remap_cfgspace (dev, pp->cfg0_base, pp->cfg0_size);if (!pp->va_cfg0_base) { -dev_err (dev,"error with ioremap in function\n" ); +dev_err (dev,"Error with ioremap in function\n" ); ret = -ENOMEM ; goto error; }
@@ -414,7 +421,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg1_base, pp->cfg1_size);if (!pp->va_cfg1_base) { -dev_err (dev,"error with ioremap\n" ); +dev_err (dev,"Error with ioremap\n" ); ret = -ENOMEM ; goto error; }
@@ -586,7 +593,7 @@ static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,return 0 ; } -/* access only one slot on each root port */ +/* Access only one slot on each root port */ if (bus->number == pp->root_bus_nr && dev >0 )return 0 ;
@@ -650,13 +657,14 @@ void dw_pcie_setup_rc(struct pcie_port *pp)/* Initialize IRQ Status array */ for (ctrl =0 ; ctrl < num_ctrls; ctrl++) -dw_pcie_rd_own_conf (pp,PCIE_MSI_INTR0_ENABLE + (ctrl *12 ),4 , - &pp->irq_status[ctrl]); -/* setup RC BARs */ +dw_pcie_rd_own_conf (pp,PCIE_MSI_INTR0_ENABLE + + (ctrl *MSI_REG_CTRL_BLOCK_SIZE ), +4 , &pp->irq_status[ctrl]); +/* Setup RC BARs */ dw_pcie_writel_dbi (pci,PCI_BASE_ADDRESS_0 ,0x00000004 );dw_pcie_writel_dbi (pci,PCI_BASE_ADDRESS_1 ,0x00000000 ); -/* setup interrupt pins */ +/* Setup interrupt pins */ dw_pcie_dbi_ro_wr_en (pci); val =dw_pcie_readl_dbi (pci,PCI_INTERRUPT_LINE ); val &=0xffff00ff ;
@@ -664,13 +672,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)dw_pcie_writel_dbi (pci,PCI_INTERRUPT_LINE , val);dw_pcie_dbi_ro_wr_dis (pci); -/* setup bus numbers */ +/* Setup bus numbers */ val =dw_pcie_readl_dbi (pci,PCI_PRIMARY_BUS ); val &=0xff000000 ; val |=0x00010100 ;dw_pcie_writel_dbi (pci,PCI_PRIMARY_BUS , val); -/* setup command register */ +/* Setup command register */ val =dw_pcie_readl_dbi (pci,PCI_COMMAND ); val &=0xffff0000 ; val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
@@ -683,7 +691,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)* we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { -/* get iATU unroll support */ +/* Get iATU unroll support */ pci->iatu_unroll_enabled =dw_pcie_iatu_unroll_enabled (pci);dev_dbg (pci->dev,"iATU unroll: %s\n" , pci->iatu_unroll_enabled ?"enabled" :"disabled" );
@@ -701,7 +709,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)/* Enable write permission for the DBI read-only register */ dw_pcie_dbi_ro_wr_en (pci); -/* program correct class for RC */ +/* Program correct class for RC */ dw_pcie_wr_own_conf (pp,PCI_CLASS_DEVICE ,2 ,PCI_CLASS_BRIDGE_PCI );/* Better disable write permission right after the update */ dw_pcie_dbi_ro_wr_dis (pci);
drivers/pci/dwc/pcie-designware-plat.c +6 -0
@@ -38,8 +38,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp)return 0 ; } +static void dw_plat_set_num_vectors (struct pcie_port *pp) +{ + pp->num_vectors =MSI_DEF_NUM_VECTORS ; +} +static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { .host_init = dw_plat_pcie_host_init, + .set_num_vectors = dw_plat_set_num_vectors, }; static int dw_plat_add_pcie_port(struct pcie_port *pp,
drivers/pci/dwc/pcie-designware.h +1 -0
@@ -110,6 +110,7 @@#define MAX_MSI_IRQS 256#define MAX_MSI_IRQS_PER_CTRL 32#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) +#define MSI_REG_CTRL_BLOCK_SIZE 12#define MSI_DEF_NUM_VECTORS 32/* Maximum number of inbound/outbound iATUs */
Signature · 1 line
2.7.4
Quoted 16 lines · Gustavo Pimentel
Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct
msi_controllerbased API.Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation.
The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed over 8 controller registers, therefore the maximum number of MSI IRQs can be changed to 256. The number of controllers can be calculated based on the number of vectors used by the specific SoC driver.
Adds Synopsys Root Complex driver support for MSI-X feature.
Quoted 7 lines
The patch set was made against the Bjorn's master branch (v4.16-rc1).
Gustavo Pimentel (4):
PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API
PCI: dwc: Remove old MSI IRQs API
PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256
PCI: dwc: Code cleanup
Ok, so a couple of suggestions:
0) Remove Gabriele from the CC list - his email must be bouncing for you too right ?
1) Consider patches on my pci/dwc-msi branch immutable from now onwards, that's important for me and other maintainers CC'ed
2) Related to (1), first 3 patches must NOT be posted again
3) Patch (4) is a potpourri of clean-ups. It is tempting to squash all clean ups in one patch but every patch has to be *logically* split so that it contains one logical change. I will comment on it. You will need to split patch (4) and repost it, but first trim the CC list, do not copy any maintainer other than pci/dwc ones on the series resulting from patch (4) rework.
If there is anything unclear please do let me know.
Thanks,
Lorenzo
Hi Lorenzo,
Quoted 25 lines · Lorenzo Pieralisi
Quoted 16 lines · Gustavo Pimentel
Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct
msi_controllerbased API.Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation.
The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed over 8 controller registers, therefore the maximum number of MSI IRQs can be changed to 256. The number of controllers can be calculated based on the number of vectors used by the specific SoC driver.
Adds Synopsys Root Complex driver support for MSI-X feature.
Quoted 7 lines
The patch set was made against the Bjorn's master branch (v4.16-rc1).
Gustavo Pimentel (4):
PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API
PCI: dwc: Remove old MSI IRQs API
PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256
PCI: dwc: Code cleanup
Quoted 4 lines
Ok, so a couple of suggestions:
0) Remove Gabriele from the CC list - his email must be bouncing for you too right ?
Done.
Quoted 2 lines
1) Consider patches on my pci/dwc-msi branch immutable from now onwards, that's important for me and other maintainers CC'ed
Ok.
Quoted 1 line
2) Related to (1), first 3 patches must NOT be posted againI thought it was mandatory to ensure the cleanup patch would be attached to that
series, if not, it's even better :) I'll assume that you will guarantee that then, since you are aware of it, right?
Quoted 6 lines
3) Patch (4) is a potpourri of clean-ups. It is tempting to squash all clean ups in one patch but every patch has to be *logically* split so that it contains one logical change. I will comment on it. You will need to split patch (4) and repost it, but first trim the CC list, do not copy any maintainer other than pci/dwc ones on the series resulting from patch (4) rework.
I'll split the patch in several and also rebased against your pci/dwc-msi branch. I'll waiting your and others feedback :)
Quoted 2 lines
If there is anything unclear please do let me know.
Ok, thank you for teaching me. The next time will be better, for sure!
Quoted 4 lines
Thanks,
Lorenzo
Thanks,
Gustavo