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Add DesignWare EP support

PATCH Applied Gustavo Pimentel 2 participants 6 messages May 15, 2018

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#0 lore raw

v2 cover Add DesignWare EP support

Patch set was made against the Lorenzo's pci/dwc branch.

The PCIe controller dual mode is capable of operating in RC mode as well as EP mode by configuration option. Till now only RC mode was supported, with this patch is add EP support to the DesignWare driver.

Gustavo Pimentel (4):
bindings: PCI: designware: Example update
PCI: dwc: Add support for EP mode
bindings: PCI: designware: Add support for EP in DesignWare driver
misc: pci_endpoint_test: Add DesignWare EP entry

 .../devicetree/bindings/pci/designware-pcie.txt    |  24 +++-
 drivers/misc/pci_endpoint_test.c                   |   1 +
 drivers/pci/dwc/Kconfig                            |  37 +++--
 drivers/pci/dwc/pcie-designware-ep.c               |   3 +
 drivers/pci/dwc/pcie-designware-plat.c             | 149 +++++++++++++++++++--
 drivers/pci/endpoint/functions/pci-epf-test.c      |   7 +
 include/linux/pci-epc.h                            |   8 ++
 7 files changed, 205 insertions(+), 24 deletions(-)
Signature · 1 line
2.7.4
#1 lore raw

PATCH v2 1/4 bindings: PCI: designware: Example update

Replace "ctrlreg" reg-name by "dbi" to be coherent with similar drivers, however it still be compatible with any previous DT that uses the old reg-name.

Replace the PCIe base address example by a real PCIe base address in use.

---
 Documentation/devicetree/bindings/pci/designware-pcie.txt | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/pci/designware-pcie.txt +6 -6
index 1da7ade..7f9804d 100644
@@ -1,7 +1,8 @@
 * Synopsys DesignWare PCIe interface
 
 Required properties:
-- compatible: should contain "snps,dw-pcie" to identify the core.
+- compatible:
+	"snps,dw-pcie" for RC mode;
 - reg: Should contain the configuration address space.
 - reg-names: Must be "config" for the PCIe configuration space.
     (The old way of getting the configuration address space from "ranges"
@@ -41,11 +42,11 @@ EP mode:
 
 Example configuration:
 
-	pcie: pcie@dffff000 {
+	pcie: pcie@dfc00000 {
 		compatible = "snps,dw-pcie";
-		reg = <0xdffff000 0x1000>, /* Controller registers */
-		      <0xd0000000 0x2000>; /* PCI config space */
-		reg-names = "ctrlreg", "config";
+		reg = <0xdfc00000 0x0001000>, /* IP registers */
+		      <0xd0000000 0x0002000>; /* Configuration space */
+		reg-names = "dbi", "config";
 		#address-cells = <3>;
 		#size-cells = <2>;
 		device_type = "pci";
@@ -54,5 +55,4 @@ Example configuration:
 		interrupts = <25>, <24>;
 		#interrupt-cells = <1>;
 		num-lanes = <1>;
-		num-viewport = <3>;
 	};
Signature · 1 line
2.7.4
#2 lore raw

PATCH v2 2/4 PCI: dwc: Add support for EP mode

In reply to Gustavo Pimentel

The PCIe controller dual mode is capable of operating in RC mode as well as EP mode by configuration option. Till now only RC mode was supported, with this patch is add EP support to the DesignWare driver.

Add new property on pci_epc structure which allow to configure pci_epf_test driver accordingly to the controller specific requirements.

---
 drivers/pci/dwc/Kconfig                       |  37 +++++--
 drivers/pci/dwc/pcie-designware-ep.c          |   3 +
 drivers/pci/dwc/pcie-designware-plat.c        | 149 ++++++++++++++++++++++++--
 drivers/pci/endpoint/functions/pci-epf-test.c |   7 ++
 include/linux/pci-epc.h                       |   8 ++
 5 files changed, 186 insertions(+), 18 deletions(-)
drivers/pci/dwc/Kconfig +29 -8
index 8c1a516..ce9e5a5 100644
@@ -51,16 +51,37 @@ config PCI_DRA7XX_EP
 	  This uses the DesignWare core.
 
 config PCIE_DW_PLAT
-	bool "Platform bus based DesignWare PCIe Controller"
-	depends on PCI_MSI_IRQ_DOMAIN
-	select PCIE_DW_HOST
-	---help---
-	 This selects the DesignWare PCIe controller support. Select this if
-	 you have a PCIe controller on Platform bus.
+	bool
 
-	 If you have a controller with this interface, say Y or M here.
+config PCIE_DW_PLAT_HOST
+	bool "Platform bus based DesignWare PCIe Controller - Host mode"
+	depends on PCI && PCI_MSI_IRQ_DOMAIN
+	select PCIE_DW_HOST
+	select PCIE_DW_PLAT
+	default y
+	help
+	  Enables support for the PCIe controller in the Designware IP to
+	  work in host mode. There are two instances of PCIe controller in
+	  Designware IP.
+	  This controller can work either as EP or RC. In order to enable
+	  host-specific features PCIE_DW_PLAT_HOST must be selected and in
+	  order to enable device-specific features PCI_DW_PLAT_EP must be
+	  selected.
 
-	 If unsure, say N.
+config PCIE_DW_PLAT_EP
+	bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
+	depends on PCI && PCI_MSI_IRQ_DOMAIN
+	depends on PCI_ENDPOINT
+	select PCIE_DW_EP
+	select PCIE_DW_PLAT
+	help
+	  Enables support for the PCIe controller in the Designware IP to
+	  work in endpoint mode. There are two instances of PCIe controller
+	  in Designware IP.
+	  This controller can work either as EP or RC. In order to enable
+	  host-specific features PCIE_DW_PLAT_HOST must be selected and in
+	  order to enable device-specific features PCI_DW_PLAT_EP must be
+	  selected.
 
 config PCI_EXYNOS
 	bool "Samsung Exynos PCIe controller"
drivers/pci/dwc/pcie-designware-ep.c +3 -0
index 15b22a6..1eec441 100644
@@ -411,6 +411,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		return -ENOMEM;
 	}
 
+	epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER;
+	EPC_FEATURE_SET_BAR(epc->features, BAR_0);
+
 	ep->epc = epc;
 	epc_set_drvdata(epc, ep);
 	dw_pcie_setup(pci);
drivers/pci/dwc/pcie-designware-plat.c +139 -10

211 lines not on this page · raw message

drivers/pci/endpoint/functions/pci-epf-test.c +7 -0
index 7cef851..bee401d 100644
@@ -435,6 +435,13 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 	if (WARN_ON_ONCE(!epc))
 		return -EINVAL;
 
+	if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
+		epf_test->linkup_notifier = false;
+	else
+		epf_test->linkup_notifier = true;
+
+	epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features);
+
 	ret = pci_epc_write_header(epc, epf->func_no, header);
 	if (ret) {
 		dev_err(dev, "configuration header write failed\n");
include/linux/pci-epc.h +8 -0
index af657ca..243eaa5 100644
@@ -90,8 +90,16 @@ struct pci_epc {
 	struct config_group		*group;
 	/* spinlock to protect against concurrent access of EP controller */
 	spinlock_t			lock;
+	unsigned int			features;
 };
 
+#define EPC_FEATURE_NO_LINKUP_NOTIFIER		BIT(0)
+#define EPC_FEATURE_BAR_MASK			(BIT(1) | BIT(2) | BIT(3))
+#define EPC_FEATURE_SET_BAR(features, bar)	\
+		(features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
+#define EPC_FEATURE_GET_BAR(features)		\
+		((features & EPC_FEATURE_BAR_MASK) >> 1)
+
 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
 
 #define pci_epc_create(dev, ops)    \
Signature · 1 line
2.7.4
#3 lore raw

PATCH v2 3/4 bindings: PCI: designware: Add support for EP in DesignWare driver

In reply to Gustavo Pimentel

Add device tree binding documentation for the EP in PCIe DesignWare driver.

---
 Documentation/devicetree/bindings/pci/designware-pcie.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
Documentation/devicetree/bindings/pci/designware-pcie.txt +12 -0
index 7f9804d..c124f9b 100644
@@ -3,6 +3,7 @@
 Required properties:
 - compatible:
 	"snps,dw-pcie" for RC mode;
+	"snps,dw-pcie-ep" for EP mode;
 - reg: Should contain the configuration address space.
 - reg-names: Must be "config" for the PCIe configuration space.
     (The old way of getting the configuration address space from "ranges"
@@ -56,3 +57,14 @@ Example configuration:
 		#interrupt-cells = <1>;
 		num-lanes = <1>;
 	};
+or
+	pcie: pcie@dfc00000 {
+		compatible = "snps,dw-pcie-ep";
+		reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
+		      <0xdfc01000 0x0001000>, /* IP registers 2 */
+		      <0xd0000000 0x2000000>; /* Configuration space */
+		reg-names = "dbi", "dbi2", "addr_space";
+		num-ib-windows = <6>;
+		num-ob-windows = <2>;
+		num-lanes = <1>;
+	};
Signature · 1 line
2.7.4
#4 lore raw

PATCH v2 4/4 misc: pci_endpoint_test: Add DesignWare EP entry

In reply to Gustavo Pimentel

Add the DesignWare EP device ID entry to pci_endpoint_test driver table.

Allow the device to be recognize and handle by the pci_endpoint_test driver.

---
 drivers/misc/pci_endpoint_test.c | 1 +
 1 file changed, 1 insertion(+)
drivers/misc/pci_endpoint_test.c +1 -0
index fe8897e..58a88ba 100644
@@ -634,6 +634,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
 static const struct pci_device_id pci_endpoint_test_tbl[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
Signature · 1 line
2.7.4
#5 lore raw
In reply to Gustavo Pimentel
Quoted 12 lines · Gustavo Pimentel

Patch set was made against the Lorenzo's pci/dwc branch.

The PCIe controller dual mode is capable of operating in RC mode as well as EP mode by configuration option. Till now only RC mode was supported, with this patch is add EP support to the DesignWare driver.

Gustavo Pimentel (4):
bindings: PCI: designware: Example update
PCI: dwc: Add support for EP mode
bindings: PCI: designware: Add support for EP in DesignWare driver
misc: pci_endpoint_test: Add DesignWare EP entry

Quoted 8 lines
 .../devicetree/bindings/pci/designware-pcie.txt    |  24 +++-
 drivers/misc/pci_endpoint_test.c                   |   1 +
 drivers/pci/dwc/Kconfig                            |  37 +++--
 drivers/pci/dwc/pcie-designware-ep.c               |   3 +
 drivers/pci/dwc/pcie-designware-plat.c             | 149 +++++++++++++++++++--
 drivers/pci/endpoint/functions/pci-epf-test.c      |   7 +
 include/linux/pci-epc.h                            |   8 ++
 7 files changed, 205 insertions(+), 24 deletions(-)

Applied to pci/dwc for v4.18 with some small commit log tweaks.

Thanks,
Lorenzo