clocksource: add gx6605s SOC system timer
v8 cover clocksource: add gx6605s SOC system timer
- Dt-bindings documentation
- timer-gx6605s driver
Guo Ren (2):
clocksource: add gx6605s SOC system timer
dt-bindings: timer: gx6605s SOC timer
.../bindings/timer/csky,gx6605s-timer.txt | 42 ++++++ drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-gx6605s.c | 150 +++++++++++++++++++++ 4 files changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt create mode 100644 drivers/clocksource/timer-gx6605s.c
Signature · 1 line
2.7.4
PATCH v8 1/2 clocksource: add gx6605s SOC system timer
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Use clksource_mmio framework
--- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/clocksource/timer-gx6605s.c
drivers/clocksource/Kconfig +8 -0
@@ -620,4 +620,12 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems. +config GX6605S_TIMER + bool "Gx6605s SOC system timer driver" + depends on CSKY + select CLKSRC_MMIO + select TIMER_OF + help + This option enables support for gx6605s SOC's timer. + endmenu
drivers/clocksource/Makefile +1 -0
@@ -79,3 +79,4 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o +obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
drivers/clocksource/timer-gx6605s.c new file +150 -0
150 lines not on this page · raw message
Signature · 1 line
2.7.4
Quoted 21 lines · Guo Ren
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Useclksource_mmioframeworkSigned-off-by Guo Ren <[email protected]>--- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/clocksource/timer-gx6605s.cdrivers/clocksource/Kconfig +0
-0@@ -620,4 +620,12 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems.
drivers/clocksource/Kconfig config RISCV_TIMER · line 631
Quoted 10 lines
drivers/clocksource/Kconfig +8
-0+config GX6605S_TIMER + bool "Gx6605s SOC system timer driver" + depends on CSKY + select CLKSRC_MMIO + select TIMER_OF + help + This option enables support for gx6605s SOC's timer. + endmenu
Please make the option not visible as default. There are currently two approaches look at MTK_TIMER and SPRD_TIMER.
Apart the two nits below, the driver looks fine.
Thanks!
-- Daniel
Quoted 32 lines
drivers/clocksource/Makefile +1
-0@@ -79,3 +79,4 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o +obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.odrivers/clocksource/timer-gx6605s.c new file +17
-0@@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/sched_clock.h> + +#include "timer-of.h" + +#define CLKSRC_OFFSET 0x40 + +#define TIMER_STATUS 0x00 +#define TIMER_VALUE 0x04 +#define TIMER_CONTRL 0x10 +#define TIMER_CONFIG 0x20 +#define TIMER_DIV 0x24 +#define TIMER_INI 0x28
drivers/clocksource/timer-gx6605s.c line 27
Quoted 10 lines
drivers/clocksource/timer-gx6605s.c new file +10
-0+ +#define GX6605S_STATUS_CLR BIT(0) +#define GX6605S_CONTRL_RST BIT(0) +#define GX6605S_CONTRL_START BIT(1) +#define GX6605S_CONFIG_EN BIT(0) +#define GX6605S_CONFIG_IRQ_EN BIT(1) + +static irqreturn_t gx6605s_timer_interrupt (int irq,void *dev) +{ +struct clock_event_device *ce = (struct clock_event_device *) dev;
nit: no cast is needed.
Quoted 60 lines
drivers/clocksource/timer-gx6605s.c new file +60
-0+void __iomem *base =timer_of_base (to_timer_of (ce)); + +writel_relaxed (GX6605S_STATUS_CLR , base +TIMER_STATUS ); + + ce->event_handler (ce); + +return IRQ_HANDLED ; +} + +static int gx6605s_timer_set_oneshot (struct clock_event_device *ce) +{ +void __iomem *base =timer_of_base (to_timer_of (ce)); + +/* reset and stop counter */ +writel_relaxed (GX6605S_CONTRL_RST , base +TIMER_CONTRL ); + +/* enable with irq and start */ +writel_relaxed (GX6605S_CONFIG_EN |GX6605S_CONFIG_IRQ_EN , base +TIMER_CONFIG ); + +return 0 ; +} + +static int gx6605s_timer_set_next_event (unsigned long delta,struct clock_event_device *ce) +{ +void __iomem *base =timer_of_base (to_timer_of (ce)); + +/* use reset to pause timer */ +writel_relaxed (GX6605S_CONTRL_RST , base +TIMER_CONTRL ); + +/* config next timeout value */ +writel_relaxed (ULONG_MAX - delta, base +TIMER_INI ); +writel_relaxed (GX6605S_CONTRL_START , base +TIMER_CONTRL ); + +return 0 ; +} + +static int gx6605s_timer_shutdown (struct clock_event_device *ce) +{ +void __iomem *base =timer_of_base (to_timer_of (ce)); + +writel_relaxed (0 , base +TIMER_CONTRL ); +writel_relaxed (0 , base +TIMER_CONFIG ); + +return 0 ; +} + +static struct timer_of to = { + .flags =TIMER_OF_IRQ |TIMER_OF_BASE |TIMER_OF_CLOCK , + .clkevt = { + .rating =300 , + .features =CLOCK_EVT_FEAT_DYNIRQ | +CLOCK_EVT_FEAT_ONESHOT , + .set_state_shutdown = gx6605s_timer_shutdown, + .set_state_oneshot = gx6605s_timer_set_oneshot, + .set_next_event = gx6605s_timer_set_next_event, + .cpumask = cpu_possible_mask, + }, + .of_irq = { + .handler = gx6605s_timer_interrupt, + .flags =IRQF_TIMER |IRQF_IRQPOLL ,
drivers/clocksource/timer-gx6605s.c line 97
Quoted 10 lines
drivers/clocksource/timer-gx6605s.c new file +10
-0+ }, +}; + +static u64 notrace gx6605s_sched_clock_read(void) +{ +void __iomem *base; + + base =timer_of_base (&to) +CLKSRC_OFFSET ; + +return (u64 )readl_relaxed (base +TIMER_VALUE );
nit: extra space after '(u64)'
Quoted 54 lines
drivers/clocksource/timer-gx6605s.c new file +53
-0+} + +static void gx6605s_clkevt_init (void __iomem *base) +{ +writel_relaxed (0 , base +TIMER_DIV ); +writel_relaxed (0 , base +TIMER_CONFIG ); + +clockevents_config_and_register (&to.clkevt,timer_of_rate (&to),2 ,ULONG_MAX ); +} + +static int gx6605s_clksrc_init (void __iomem *base) +{ +writel_relaxed (0 , base +TIMER_DIV ); +writel_relaxed (0 , base +TIMER_INI ); + +writel_relaxed (GX6605S_CONTRL_RST , base +TIMER_CONTRL ); + +writel_relaxed (GX6605S_CONFIG_EN , base +TIMER_CONFIG ); + +writel_relaxed (GX6605S_CONTRL_START , base +TIMER_CONTRL ); + +sched_clock_register (gx6605s_sched_clock_read,32 ,timer_of_rate (&to)); + +return clocksource_mmio_init (base +TIMER_VALUE ,"gx6605s" ,timer_of_rate (&to), +200 ,32 , clocksource_mmio_readl_up); +} + +static int __init gx6605s_timer_init (struct device_node *np) +{ +int ret; + +/* +* The timer driver is for nationalchip gx6605s SOC and there are two same timer +* in gx6605s. We use one for clkevt and another for clksrc. +* +* The timer is mmio map to access, so we need give mmio addres in dts. +* +* It provides a 32bit countup timer and interrupt will be caused by count-overflow. +* So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg. +* +* The counter at 0x0 offset is clock event. +* The counter at 0x40 offset is clock source. +* They are the same in hardware, just different used by driver. +*/ + ret =timer_of_init (np, &to); +if (ret) +return ret; + +gx6605s_clkevt_init (timer_of_base (&to)); + +return gx6605s_clksrc_init (timer_of_base (&to) +CLKSRC_OFFSET ); +} +TIMER_OF_DECLARE (csky_gx6605s_timer,"csky,gx6605s-timer" , gx6605s_timer_init);
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Quoted 23 lines · Daniel Lezcano
Quoted 22 lines · Guo Ren
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Useclksource_mmioframeworkSigned-off-by Guo Ren <[email protected]>--- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/clocksource/timer-gx6605s.cdrivers/clocksource/Kconfig +0
-0@@ -620,4 +620,12 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems.
Quoted 12 lines
drivers/clocksource/Kconfig config RISCV_TIMER · line 631
Quoted 9 lines
drivers/clocksource/Kconfig +8
-0+config GX6605S_TIMER + bool "Gx6605s SOC system timer driver" + depends on CSKY + select CLKSRC_MMIO + select TIMER_OF + help + This option enables support for gx6605s SOC's timer. + endmenuPlease make the option not visible as default. There are currently two approaches look at
MTK_TIMERandSPRD_TIMER.
Em ... (ot sure why COMPILE_TEST?):
bool "Gx6605s SOC system timer driver" if COMPILE_TEST
Hmm?
Quoted 5 lines
drivers/clocksource/Kconfig
Quoted 3 lines
drivers/clocksource/Kconfig +3
-0+static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev) +{ + struct clock_event_device *ce = (struct clock_event_device *) dev;nit: no cast is needed.
Yes, change to:
struct clock_event_device *ce = dev;
Quoted 9 lines
drivers/clocksource/Kconfig
Quoted 7 lines
drivers/clocksource/Kconfig +7
-0+static u64 notrace gx6605s_sched_clock_read(void) +{ + void __iomem *base; + + base = timer_of_base(&to) + CLKSRC_OFFSET; + + return (u64) readl_relaxed(base + TIMER_VALUE);nit: extra space after '(u64)'
Ok
return (u64)readl_relaxed(base + TIMER_VALUE);
Best Regards
Guo Ren
Quoted 36 lines · Guo Ren
Quoted 23 lines · Daniel Lezcano
Quoted 22 lines · Guo Ren
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Useclksource_mmioframeworkSigned-off-by Guo Ren <[email protected]>--- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/clocksource/timer-gx6605s.cdrivers/clocksource/Kconfig +0
-0@@ -620,4 +620,12 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems.Quoted 12 lines
drivers/clocksource/Kconfig config RISCV_TIMER · line 631
Quoted 9 lines
drivers/clocksource/Kconfig +8
-0+config GX6605S_TIMER + bool "Gx6605s SOC system timer driver" + depends on CSKY + select CLKSRC_MMIO + select TIMER_OF + help + This option enables support for gx6605s SOC's timer. + endmenuPlease make the option not visible as default. There are currently two approaches look at
MTK_TIMERandSPRD_TIMER.
Quoted 3 lines
Em ... (ot sure why
COMPILE_TEST?):
bool "Gx6605s SOC system timer driver" ifCOMPILE_TEST
Hmm?
Because by enabling the COMPILE_TEST, you give the opportunity to someone without the hardware to cross-compile test your driver and catch errors very soon before the changes hit your tree.
There are several Continuous Integration loop around running the latest changes in the kernel (kernelci, 01.org, etc ...) and all drivers with this flag are compiled tested.
If the option is not set, the timer is silently selected by your platform's Kconfig only, without giving the opportunity to an non-expert user to unselect the timer leading to, maybe, an unbootable board.
Quoted 24 lines
Quoted 5 lines
drivers/clocksource/Kconfig
Quoted 3 lines
drivers/clocksource/Kconfig +3
-0+static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev) +{ + struct clock_event_device *ce = (struct clock_event_device *) dev;nit: no cast is needed.
Yes, change to:
struct clock_event_device *ce = dev;Quoted 9 lines
drivers/clocksource/Kconfig
Quoted 7 lines
drivers/clocksource/Kconfig +7
-0+static u64 notrace gx6605s_sched_clock_read(void) +{ + void __iomem *base; + + base = timer_of_base(&to) + CLKSRC_OFFSET; + + return (u64) readl_relaxed(base + TIMER_VALUE);nit: extra space after '(u64)'
Ok
return (u64)readl_relaxed(base + TIMER_VALUE);Best Regards
Guo Ren
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Quoted 45 lines · Daniel Lezcano
Quoted 36 lines · Guo Ren
Quoted 23 lines · Daniel Lezcano
Quoted 22 lines · Guo Ren
Changelog:
- Add License and Copyright
- Use timer-of framework
- Change name with upstream feedback
- Useclksource_mmioframeworkSigned-off-by Guo Ren <[email protected]>--- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/clocksource/timer-gx6605s.cdrivers/clocksource/Kconfig +0
-0@@ -620,4 +620,12 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems.Quoted 12 lines
drivers/clocksource/Kconfig config RISCV_TIMER · line 631
Quoted 9 lines
drivers/clocksource/Kconfig +8
-0+config GX6605S_TIMER + bool "Gx6605s SOC system timer driver" + depends on CSKY + select CLKSRC_MMIO + select TIMER_OF + help + This option enables support for gx6605s SOC's timer. + endmenuPlease make the option not visible as default. There are currently two approaches look at
MTK_TIMERandSPRD_TIMER.Quoted 3 lines
Em ... (ot sure why
COMPILE_TEST?):
bool "Gx6605s SOC system timer driver" ifCOMPILE_TEST
Hmm?Because by enabling the
COMPILE_TEST, you give the opportunity to someone without the hardware to cross-compile test your driver and catch errors very soon before the changes hit your tree.
Quoted 8 lines
There are several Continuous Integration loop around running the latest changes in the kernel (kernelci, 01.org, etc ...) and all drivers with this flag are compiled tested.
If the option is not set, the timer is silently selected by your platform's
Kconfigonly, without giving the opportunity to an non-expert user to unselect the timer leading to, maybe, an unbootable board.
I got it, thx for the reply.
Best Regards
Guo Ren
PATCH v8 2/2 dt-bindings: timer: gx6605s SOC timer
In reply to Guo Ren- Dt-bindings doc for gx6605s SOC's system timer.
--- .../bindings/timer/csky,gx6605s-timer.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt
Documentation/devicetree/bindings/timer/csky,gx6605s-timer.txt new file +42 -0
@@ -0,0 +1,42 @@ +================= +gx6605s SOC Timer +================= + +The timer is used in gx6605s soc as system timer and the driver +contain clk event and clk source. + +============================== +timer node bindings definition +============================== + + Description: Describes gx6605s SOC timer + + PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: must be "csky,gx6605s-timer" + - reg + Usage: required + Value type: <u32 u32> + Definition: <phyaddr size> in soc from cpu view + - clocks + Usage: required + Value type: phandle + clock specifier cells + Definition: must be input clk node + - interrupt + Usage: required + Value type: <u32> + Definition: must be timer irq num defined by soc + +Examples: +--------- + + timer0: timer@20a000 { + compatible = "csky,gx6605s-timer"; + reg = <0x0020a000 0x400>; + clocks = <&dummy_apb_clk>; + interrupts = <10>; + interrupt-parent = <&intc>; + };
Signature · 1 line
2.7.4