initial support for "suniv" Allwinner new ARM9 SoC

PATCH Superseded Mesih Kilinc 4 participants 25 messages Nov 28, 2018 – Dec 2, 2018

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Device tree bindings Arm (32-bit) Arm sub-architectures GPIO +8 more subsystems

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Mesih Kilinc

author

2018-11-28 22:33 UTC #0 lore raw

v5 cover initial support for "suniv" Allwinner new ARM9 SoC

This is the fifth version of patchset for Allwinner ARMv5 F1C100s SoC. Addressed comments from Maxime Ripard and Rob Herring, added signatures.

Changes since v4:
- Patch "dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl"
- This patch applied for 4.21.
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)"
- This patch applied for 4.21.
- Patch "dt-bindings: clock: Add Allwinner suniv F1C100s CCU"
- Fixed license identifier position
- Added DMA fields.
- Patch "clk: sunxi-ng: add support for suniv F1C100s SoC"
- Added DMA reset and clock support.
- Patch "ARM: dts: suniv: add initial DTSI file for F1C100s"
- Remove dt-binding headers.
- Fix uart0 pin label.
- Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano"
- Fix uart0 pin label.

Changes since v3:
- Patch "ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs"
- Remove CONFIG_ARCH_SUNXI_Vx. Use ARCH_MULTI_Vx to differentiate SoC's
- Change KConfig ARCH_SUNXI selection: 'select' to 'default'.
- Patch "irqchip/sun4i: Add a struct to hold global variables"
- Split irq_sun4i.c changes to 3 patch.
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)"
- pinctrl-suniv-f1c100s: remove: disable_strict_mode = true
- Patch "ARM: dts: suniv: add initial DTSI file for F1C100s"
- suniv-f1c100s.dtsi: remove unnecessary componenets.
- Instead of patching drivers, add original compatible string with
f1c100s compatibles.
- Add Acked-by signatures.

Changes since v2:
- Patch "ARM: sunxi: add Allwinner ARMv5 SoCs"
- Move SUN4I_TIMER option to ARCH_SUNXI
- Added help text for MACH_SUNIV
- Patch "irqchip/sun4i: add support for suniv interrupt controller"
- Defined sunxi_irq_chip_data struct and used it to differentiate registers between different chips.
- Patch " ARM: dts: suniv: add initial DTSI file for F1C100s"
- Removed unnecessary fake clock.
- Fixed compatible strings.

Changes since v1:
- Patch "ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs"
- Instead of using a common bool config use a common menuconfig.
- Use ARCH_MULTI_V7 to differentiate V7 SoCs.
- Addressed comment from Julian Calaby
- Patch "ARM: sunxi: add Allwinner ARMv5 SoCs"
- Use ARCH_MULTI_V5 to differentiate V5 SoCs.
- removed "allwinner,suniv" board compatible string
- Added dt-bindings
- Patch "irqchip/sun4i: add support for suniv interrupt controller"
- Added dt-bindings
- Changed "allwinner,suniv-ic" to "allwinner,suniv-f1c100s-ic"
- Patch "clocksource: sun4i: add a compatible for suniv"
- Added dt-bindings
- Changed "allwinner,suniv-timer" to "allwinner,suniv-f1c100s-timer"
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)"
- Added dt-bindings
- Renamed suniv-pinctrl to suniv-f1c100s-pinctrl
- Patch "clk: sunxi-ng: add support for suniv F1C100s SoC"
- Added dt-bindings
- Renamed suniv-ccu to suniv-f1c100s-ccu
- Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano"
- Addressed comment from Rask Ingemann Lambertsen

Thanks!

Mesih Kilinc (17):
ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs
dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC
ARM: sunxi: add Allwinner ARMv5 SoCs
dt-bindings: interrupt-controller: Add suniv interrupt-controller irqchip/sun4i: Add a struct to hold global variables irqchip/sun4i: Move IC specific register offsets to struct irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s
dt-bindings: timer: Add Allwinner suniv timer
clocksource: sun4i: add a compatible for suniv
dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl
pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
clk: sunxi-ng: add support for suniv F1C100s SoC
dt-bindings: sram: Add Allwinner suniv F1C100s
dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt
ARM: dts: suniv: add initial DTSI file for F1C100s
ARM: suniv: f1c100s: add device tree for Lichee Pi Nano

 Documentation/devicetree/bindings/arm/sunxi.txt    |   1 +
 .../devicetree/bindings/clock/sunxi-ccu.txt        |   1 +
 .../interrupt-controller/allwinner,sun4i-ic.txt    |   4 +-
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 .../devicetree/bindings/sram/sunxi-sram.txt        |   4 +
 .../bindings/timer/allwinner,sun4i-timer.txt       |   4 +-
 .../devicetree/bindings/watchdog/sunxi-wdt.txt     |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  |  26 +
 arch/arm/boot/dts/suniv-f1c100s.dtsi               | 147 ++++++
 arch/arm/mach-sunxi/Kconfig                        |  19 +-
 arch/arm/mach-sunxi/sunxi.c                        |  10 +
 drivers/clk/sunxi-ng/Kconfig                       |   5 +
 drivers/clk/sunxi-ng/Makefile                      |   1 +
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c           | 541 +++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h           |  34 ++
 drivers/clocksource/sun4i_timer.c                  |   5 +-
 drivers/irqchip/irq-sun4i.c                        | 106 ++--
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c      | 416 ++++++++++++++++
 include/dt-bindings/clock/suniv-ccu-f1c100s.h      |  70 +++
 include/dt-bindings/reset/suniv-ccu-f1c100s.h      |  38 ++
 23 files changed, 1408 insertions(+), 33 deletions(-)
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
 create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
 create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #1 lore raw

PATCH v5 1/17 ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs

Allwinner also has some ARMv5 SoCs.

In order to add support for them, check ARM_MULTI_V7 before enabling ARMv7 SoC's. Add help text for ARCH_SUNXI menuconfig.

Signed-off-by Mesih Kilinc <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/mach-sunxi/Kconfig +6 -0

index d9c8ecf..185c573 100644
@@ -9,9 +9,13 @@ menuconfig ARCH_SUNXI
 	select PM_OPP
 	select SUN4I_TIMER
 	select RESET_CONTROLLER
+	help
+	  Support for Allwinner ARM-based family of processors
 
 if ARCH_SUNXI
 
+if ARCH_MULTI_V7
+
 config MACH_SUN4I
 	bool "Allwinner A10 (sun4i) SoCs support"
 	default ARCH_SUNXI

@@ -56,3 +60,5 @@ config ARCH_SUNXI_MC_SMP
 	select ARM_CPU_SUSPEND
 
 endif
+
+endif

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #2 lore raw

PATCH v5 2/17 dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC

In reply to Mesih Kilinc

Add new Allwinner ARMv5 F1C100s SoC's compatible string

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/arm/sunxi.txt +1 -0

index e4beec3..f9ddc05 100644
@@ -18,4 +18,5 @@ using one of the following compatible strings:
   allwinner,sun8i-v3s
   allwinner,sun9i-a80
   allwinner,sun50i-a64
+  allwinner,suniv-f1c100s
   nextthing,gr8

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #3 lore raw

PATCH v5 3/17 ARM: sunxi: add Allwinner ARMv5 SoCs

In reply to Mesih Kilinc

Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600).

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 13 ++++++++++++-
 arch/arm/mach-sunxi/sunxi.c | 10 ++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

arch/arm/mach-sunxi/Kconfig +12 -1

index 185c573..7fa6a3d 100644
@@ -1,6 +1,6 @@
 menuconfig ARCH_SUNXI
 	bool "Allwinner SoCs"
-	depends on ARCH_MULTI_V7
+	depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
 	select ARCH_HAS_RESET_CONTROLLER
 	select CLKSRC_MMIO
 	select GENERIC_IRQ_CHIP

@@ -61,4 +61,15 @@ config ARCH_SUNXI_MC_SMP
 
 endif
 
+if ARCH_MULTI_V5
+
+config MACH_SUNIV
+	bool "Allwinner ARMv5 F-series (suniv) SoCs support"
+	default ARCH_SUNXI
+	help
+	  Support for Allwinner suniv ARMv5 SoCs.
+	  (F1C100A, F1C100s, F1C200s, F1C500, F1C600)
+
+endif
+
 endif

arch/arm/mach-sunxi/sunxi.c +10 -0

index de4b0e9..155cd9e 100644
@@ -101,3 +101,13 @@ static const char * const sun9i_board_dt_compat[] = {
 DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family")
 	.dt_compat	= sun9i_board_dt_compat,
 MACHINE_END
+
+static const char * const suniv_board_dt_compat[] = {
+	"allwinner,suniv-f1c100s",
+	NULL,
+};
+
+DT_MACHINE_START(SUNIV_DT, "Allwinner suniv Family")
+	.dt_compat	= suniv_board_dt_compat,
+MACHINE_END
+

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #4 lore raw

PATCH v5 4/17 dt-bindings: interrupt-controller: Add suniv interrupt-controller

In reply to Mesih Kilinc

Add compatible string for Alwinner suniv F1C100s SoC interrupt controller which is stripped version of sun4i

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 .../devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt   | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +3 -1

index b290ca1..4043525 100644
@@ -2,7 +2,9 @@ Allwinner Sunxi Interrupt Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-a10-ic"
+- compatible : should be one of the following:
+              "allwinner,sun4i-a10-ic"
+              "allwinner,suniv-f1c100s-ic"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #5 lore raw

PATCH v5 5/17 irqchip/sun4i: Add a struct to hold global variables

In reply to Mesih Kilinc

In order to support different chips, IC specific data should be hold in a struct. This patch moves irq_base and irq_domain global variables to struct.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
 drivers/irqchip/irq-sun4i.c | 64 +++++++++++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 26 deletions(-)

drivers/irqchip/irq-sun4i.c +38 ~~-26~~

index e3e5b91..0c32506 100644
@@ -31,8 +31,12 @@
 #define SUN4I_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
 #define SUN4I_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
 
-static void __iomem *sun4i_irq_base;
-static struct irq_domain *sun4i_irq_domain;
+struct sun4i_irq_chip_data {
+	void __iomem *irq_base;
+	struct irq_domain *irq_domain;
+};
+
+static struct sun4i_irq_chip_data *irq_ic_data;
 
 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);

@@ -43,7 +47,7 @@ static void sun4i_irq_ack(struct irq_data *irqd)
 	if (irq != 0)
 		return; /* Only IRQ 0 / the ENMI needs to be acked */
 
-	writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
+	writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
 }
 
 static void sun4i_irq_mask(struct irq_data *irqd)

@@ -53,9 +57,9 @@ static void sun4i_irq_mask(struct irq_data *irqd)
 	int reg = irq / 32;
 	u32 val;
 
-	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 	writel(val & ~(1 << irq_off),
-	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 }
 
 static void sun4i_irq_unmask(struct irq_data *irqd)

@@ -65,9 +69,9 @@ static void sun4i_irq_unmask(struct irq_data *irqd)
 	int reg = irq / 32;
 	u32 val;
 
-	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 	writel(val | (1 << irq_off),
-	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 }
 
 static struct irq_chip sun4i_irq_chip = {

@@ -95,35 +99,41 @@ static const struct irq_domain_ops sun4i_irq_ops = {
 static int __init sun4i_of_init(struct device_node *node,
 				struct device_node *parent)
 {
-	sun4i_irq_base = of_iomap(node, 0);
-	if (!sun4i_irq_base)
+	irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
+	if (!irq_ic_data) {
+		pr_err("kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	irq_ic_data->irq_base = of_iomap(node, 0);
+	if (!irq_ic_data->irq_base)
 		panic("%pOF: unable to map IC registers\n",
 			node);
 
 	/* Disable all interrupts */
-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2));
 
 	/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2));
 
 	/* Clear all the pending interrupts */
-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
 
 	/* Enable protection mode */
-	writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
+	writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
 
 	/* Configure the external interrupt source type */
-	writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
+	writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
 
-	sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
+	irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,
 						 &sun4i_irq_ops, NULL);
-	if (!sun4i_irq_domain)
+	if (!irq_ic_data->irq_domain)
 		panic("%pOF: unable to create IRQ domain\n", node);
 
 	set_handle_irq(sun4i_handle_irq);

@@ -146,13 +156,15 @@ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
 	 * the extra check in the common case of 1 hapening after having
 	 * read the vector-reg once.
 	 */
-	hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+	hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
 	if (hwirq == 0 &&
-		  !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
+		  !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) &
+			  BIT(0)))
 		return;
 
 	do {
-		handle_domain_irq(sun4i_irq_domain, hwirq, regs);
-		hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+		handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs);
+		hwirq = readl(irq_ic_data->irq_base +
+				SUN4I_IRQ_VECTOR_REG) >> 2;
 	} while (hwirq != 0);
 }

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #6 lore raw

PATCH v5 6/17 irqchip/sun4i: Move IC specific register offsets to struct

In reply to Mesih Kilinc

This patch moves IC specific register offsets to sun4i_irq_chip_data struct in order to support different chips.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
 drivers/irqchip/irq-sun4i.c | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

drivers/irqchip/irq-sun4i.c +21 ~~-12~~

index 0c32506..507f4e3 100644
@@ -28,12 +28,16 @@
 #define SUN4I_IRQ_NMI_CTRL_REG		0x0c
 #define SUN4I_IRQ_PENDING_REG(x)	(0x10 + 0x4 * x)
 #define SUN4I_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
-#define SUN4I_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
-#define SUN4I_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
+#define SUN4I_IRQ_ENABLE_REG(data, x)	((data)->enable_reg_offset + 0x4 * x)
+#define SUN4I_IRQ_MASK_REG(data, x)	((data)->mask_reg_offset + 0x4 * x)
+#define SUN4I_IRQ_ENABLE_REG_OFFSET	0x40
+#define SUN4I_IRQ_MASK_REG_OFFSET	0x50
 
 struct sun4i_irq_chip_data {
 	void __iomem *irq_base;
 	struct irq_domain *irq_domain;
+	u32 enable_reg_offset;
+	u32 mask_reg_offset;
 };
 
 static struct sun4i_irq_chip_data *irq_ic_data;

@@ -57,9 +61,10 @@ static void sun4i_irq_mask(struct irq_data *irqd)
 	int reg = irq / 32;
 	u32 val;
 
-	val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	val = readl(irq_ic_data->irq_base +
+			SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
 	writel(val & ~(1 << irq_off),
-	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
 }
 
 static void sun4i_irq_unmask(struct irq_data *irqd)

@@ -69,9 +74,10 @@ static void sun4i_irq_unmask(struct irq_data *irqd)
 	int reg = irq / 32;
 	u32 val;
 
-	val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	val = readl(irq_ic_data->irq_base +
+			SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
 	writel(val | (1 << irq_off),
-	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
 }
 
 static struct irq_chip sun4i_irq_chip = {

@@ -105,20 +111,23 @@ static int __init sun4i_of_init(struct device_node *node,
 		return -ENOMEM;
 	}
 
+	irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
+	irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET;
+
 	irq_ic_data->irq_base = of_iomap(node, 0);
 	if (!irq_ic_data->irq_base)
 		panic("%pOF: unable to map IC registers\n",
 			node);
 
 	/* Disable all interrupts */
-	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0));
-	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1));
-	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2));
 
 	/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
-	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0));
-	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1));
-	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2));
 
 	/* Clear all the pending interrupts */
 	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #7 lore raw

PATCH v5 7/17 irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s

In reply to Mesih Kilinc

This patch adds support for suniv Allwinner ARMv5 F1C100s SoC which has stripped version of interrupt controller that found in A10/A13.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
 drivers/irqchip/irq-sun4i.c | 47 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 37 insertions(+), 10 deletions(-)

drivers/irqchip/irq-sun4i.c +37 ~~-10~~

index 507f4e3..fb78d66 100644
@@ -32,6 +32,8 @@
 #define SUN4I_IRQ_MASK_REG(data, x)	((data)->mask_reg_offset + 0x4 * x)
 #define SUN4I_IRQ_ENABLE_REG_OFFSET	0x40
 #define SUN4I_IRQ_MASK_REG_OFFSET	0x50
+#define SUNIV_IRQ_ENABLE_REG_OFFSET	0x20
+#define SUNIV_IRQ_MASK_REG_OFFSET	0x30
 
 struct sun4i_irq_chip_data {
 	void __iomem *irq_base;

@@ -105,15 +107,6 @@ static const struct irq_domain_ops sun4i_irq_ops = {
 static int __init sun4i_of_init(struct device_node *node,
 				struct device_node *parent)
 {
-	irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
-	if (!irq_ic_data) {
-		pr_err("kzalloc failed!\n");
-		return -ENOMEM;
-	}
-
-	irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
-	irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET;
-
 	irq_ic_data->irq_base = of_iomap(node, 0);
 	if (!irq_ic_data->irq_base)
 		panic("%pOF: unable to map IC registers\n",

@@ -149,7 +142,41 @@ static int __init sun4i_of_init(struct device_node *node,
 
 	return 0;
 }
-IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
+
+static int __init sun4i_ic_of_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
+	if (!irq_ic_data) {
+		pr_err("kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
+	irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET;
+
+	return sun4i_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init);
+
+static int __init suniv_ic_of_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
+	if (!irq_ic_data) {
+		pr_err("kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;
+	irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET;
+
+	return sun4i_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic",
+		suniv_ic_of_init);
 
 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
 {

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #8 lore raw

PATCH v5 8/17 dt-bindings: timer: Add Allwinner suniv timer

In reply to Mesih Kilinc

Add compatible string for Allwinner suniv timer which is similar to sun4i timer.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt +3 -1

index 5c2e235..3da9d51 100644
@@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-a10-timer"
+- compatible : should be one of the following:
+              "allwinner,sun4i-a10-timer"
+              "allwinner,suniv-f1c100s-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : The interrupt of the first timer
 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #9 lore raw

PATCH v5 9/17 clocksource: sun4i: add a compatible for suniv

In reply to Mesih Kilinc

The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels.

Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed.

The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

Acked-by Daniel Lezcano <[email protected]>

---
 drivers/clocksource/sun4i_timer.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

drivers/clocksource/sun4i_timer.c +4 -1

index 6e0180a..65f38f6 100644
@@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node)
 	 */
 	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
 	    of_machine_is_compatible("allwinner,sun5i-a13") ||
-	    of_machine_is_compatible("allwinner,sun5i-a10s"))
+	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
+	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
 		sched_clock_register(sun4i_timer_sched_read, 32,
 				     timer_of_rate(&to));

@@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node)
 }
 TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
 		       sun4i_timer_init);
+TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
+		       sun4i_timer_init);

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #10 lore raw

PATCH v5 10/17 dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl

In reply to Mesih Kilinc

Add compatible string for Allwinner suniv F1C100s SoC's pinctrl.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

Patch applied to the pin control tree for v4.21.

---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +1 -0

index 258a464..a7f7133 100644
@@ -29,6 +29,7 @@ Required properties:
   "allwinner,sun50i-h5-pinctrl"
   "allwinner,sun50i-h6-pinctrl"
   "allwinner,sun50i-h6-r-pinctrl"
+  "allwinner,suniv-f1c100s-pinctrl"
   "nextthing,gr8-pinctrl"
 
 - reg: Should contain the register physical address and length for the

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #11 lore raw

PATCH v5 11/17 pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)

In reply to Mesih Kilinc

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin
controller like other SoCs from Allwinner.

Add support for it.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

Patch applied to the pin control tree for v4.21.

---
 drivers/pinctrl/sunxi/Kconfig                 |   4 +
 drivers/pinctrl/sunxi/Makefile                |   1 +
 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c | 416 ++++++++++++++++++++++++++
 3 files changed, 421 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c

drivers/pinctrl/sunxi/Kconfig +4 -0

index 95282cd..a731fc9 100644
@@ -6,6 +6,10 @@ config PINCTRL_SUNXI
 	select GENERIC_PINCONF
 	select GPIOLIB
 
+config PINCTRL_SUNIV_F1C100S
+	def_bool MACH_SUNIV
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN4I_A10
 	def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
 	select PINCTRL_SUNXI

drivers/pinctrl/sunxi/Makefile +1 -0

index adb8443..fafcdae 100644
@@ -3,6 +3,7 @@
 obj-y					+= pinctrl-sunxi.o
 
 # SoC Drivers
+obj-$(CONFIG_PINCTRL_SUNIV_F1C100S)	+= pinctrl-suniv-f1c100s.o
 obj-$(CONFIG_PINCTRL_SUN4I_A10)		+= pinctrl-sun4i-a10.o
 obj-$(CONFIG_PINCTRL_SUN5I)		+= pinctrl-sun5i.o
 obj-$(CONFIG_PINCTRL_SUN6I_A31)		+= pinctrl-sun6i-a31.o

drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c new file +416 -0

416 lines not on this page · raw message

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #12 lore raw

PATCH v5 12/17 dt-bindings: clock: Add Allwinner suniv F1C100s CCU

In reply to Mesih Kilinc

Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
 .../devicetree/bindings/clock/sunxi-ccu.txt        |  1 +
 include/dt-bindings/clock/suniv-ccu-f1c100s.h      | 70 ++++++++++++++++++++++
 include/dt-bindings/reset/suniv-ccu-f1c100s.h      | 38 ++++++++++++
 3 files changed, 109 insertions(+)
 create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
 create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h

Documentation/devicetree/bindings/clock/sunxi-ccu.txt +1 -0

index 47d2e90..e3bd88a 100644
@@ -22,6 +22,7 @@ Required properties :
 		- "allwinner,sun50i-h5-ccu"
 		- "allwinner,sun50i-h6-ccu"
 		- "allwinner,sun50i-h6-r-ccu"
+		- "allwinner,suniv-f1c100s-ccu"
 		- "nextthing,gr8-ccu"
 
 - reg: Must contain the registers base address and length

include/dt-bindings/clock/suniv-ccu-f1c100s.h new file +70 -0

70 lines not on this page · raw message

include/dt-bindings/reset/suniv-ccu-f1c100s.h new file +38 -0

new file mode 100644
index 0000000..6a4b438
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ *
+ * Copyright (C) 2018 Icenowy Zheng <[email protected]>
+ *
+ */
+
+#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
+
+#define RST_USB_PHY0		0
+#define RST_BUS_DMA		1
+#define RST_BUS_MMC0		2
+#define RST_BUS_MMC1		3
+#define RST_BUS_DRAM		4
+#define RST_BUS_SPI0		5
+#define RST_BUS_SPI1		6
+#define RST_BUS_OTG		7
+#define RST_BUS_VE		8
+#define RST_BUS_LCD		9
+#define RST_BUS_DEINTERLACE	10
+#define RST_BUS_CSI		11
+#define RST_BUS_TVD		12
+#define RST_BUS_TVE		13
+#define RST_BUS_DE_BE		14
+#define RST_BUS_DE_FE		15
+#define RST_BUS_CODEC		16
+#define RST_BUS_SPDIF		17
+#define RST_BUS_IR		18
+#define RST_BUS_RSB		19
+#define RST_BUS_I2S0		20
+#define RST_BUS_I2C0		21
+#define RST_BUS_I2C1		22
+#define RST_BUS_I2C2		23
+#define RST_BUS_UART0		24
+#define RST_BUS_UART1		25
+#define RST_BUS_UART2		26
+
+#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */

Signature · 1 line

2.7.4

Stephen Boyd

maintainer Acked-by on v5 12/17

2018-11-29 00:47 UTC #13 lore raw

Re: [PATCH v5 12/17] dt-bindings: clock: Add Allwinner suniv F1C100s CCU

Quoting Mesih Kilinc (2018-11-28 14:33:22)

Quoted 6 lines

Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions.
Signed-off-by Mesih Kilinc <[email protected]>
Acked-by Maxime Ripard <[email protected]>
---

Acked-by Stephen Boyd <[email protected]>

Mesih Kilinc

author

2018-11-28 22:33 UTC #14 lore raw

PATCH v5 13/17 clk: sunxi-ng: add support for suniv F1C100s SoC

In reply to Mesih Kilinc

The suniv F1C100s SoC (the chip in some new F-series products of Allwinner)
has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i.

Add support for the CCU.

Signed-off-by Mesih Kilinc <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
 drivers/clk/sunxi-ng/Kconfig             |   5 +
 drivers/clk/sunxi-ng/Makefile            |   1 +
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 541 +++++++++++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h |  34 ++
 4 files changed, 581 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h

drivers/clk/sunxi-ng/Kconfig +5 -0

index 826674d..429ea4a 100644
@@ -6,6 +6,11 @@ config SUNXI_CCU
 
 if SUNXI_CCU
 
+config SUNIV_F1C100S_CCU
+	bool "Support for the Allwinner newer F1C100s CCU"
+	default MACH_SUNIV
+	depends on MACH_SUNIV || COMPILE_TEST
+
 config SUN50I_A64_CCU
 	bool "Support for the Allwinner A64 CCU"
 	default ARM64 && ARCH_SUNXI

drivers/clk/sunxi-ng/Makefile +1 -0

index 4945470..4c7bee8 100644
@@ -21,6 +21,7 @@ obj-y				+= ccu_nm.o
 obj-y				+= ccu_mp.o
 
 # SoC support
+obj-$(CONFIG_SUNIV_F1C100S_CCU)	+= ccu-suniv-f1c100s.o
 obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o
 obj-$(CONFIG_SUN50I_H6_CCU)	+= ccu-sun50i-h6.o
 obj-$(CONFIG_SUN50I_H6_R_CCU)	+= ccu-sun50i-h6-r.o

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file +541 -0

541 lines not on this page · raw message

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h new file +34 -0

new file mode 100644
index 0000000..1da687a
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2017 Icenowy Zheng <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CCU_SUNIV_F1C100S_H_
+#define _CCU_SUNIV_F1C100S_H_
+
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
+#define CLK_PLL_CPU		0
+#define CLK_PLL_AUDIO_BASE	1
+#define CLK_PLL_AUDIO		2
+#define CLK_PLL_AUDIO_2X	3
+#define CLK_PLL_AUDIO_4X	4
+#define CLK_PLL_AUDIO_8X	5
+#define CLK_PLL_VIDEO		6
+#define CLK_PLL_VIDEO_2X	7
+#define CLK_PLL_VE		8
+#define CLK_PLL_DDR0		9
+#define CLK_PLL_PERIPH		10
+
+/* CPU clock is exported */
+
+#define CLK_AHB			12
+#define CLK_APB			13
+
+/* All bus gates, DRAM gates and mod clocks are exported */
+
+#define CLK_NUMBER		(CLK_AVS + 1)
+
+#endif /* _CCU_SUNIV_F1C100S_H_ */

Signature · 1 line

2.7.4

Stephen Boyd

maintainer

2018-11-29 00:47 UTC #15 lore raw

Re: [PATCH v5 13/17] clk: sunxi-ng: add support for suniv F1C100s SoC

Quoting Mesih Kilinc (2018-11-28 14:33:23)

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c line 4

Quoted 10 lines

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file +4 -0

new file mode 100644
index 0000000..d4bc1b8
@@ -0,0 +1,541 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0

Please fix this location.

Quoted 10 lines

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file +4 -0
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h new file +0 -0
new file mode 100644
index 0000000..1da687a

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h line 4

Quoted 4 lines

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h new file +4 -0

@@ -0,0 +1,34 @@
+/*
+ * Copyright 2017 Icenowy Zheng <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+

Ditto.

Quoted 2 lines

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h new file +2 -0
+ */
+

Mesih Kilinc

author

2018-11-29 06:39 UTC #16 lore raw

Re: [PATCH v5 13/17] clk: sunxi-ng: add support for suniv F1C100s SoC

Quoted 13 lines · Stephen Boyd

Quoting Mesih Kilinc (2018-11-28 14:33:23)
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c line 4
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file +4 -0
new file mode 100644
index 0000000..d4bc1b8
@@ -0,0 +1,541 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0
Please fix this location.

I am very sorry, I should have been more carefull. Should I resend whole patchset or just resending this patch is enough?

Thanks,
Mesih

Stephen Boyd

maintainer

2018-11-29 23:37 UTC #17 lore raw

Re: [PATCH v5 13/17] clk: sunxi-ng: add support for suniv F1C100s SoC

Quoting Mesih Kilinc (2018-11-28 22:39:52)

Quoted 15 lines · Stephen Boyd

Quoted 13 lines
Quoting Mesih Kilinc (2018-11-28 14:33:23)
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c line 4
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file +4 -0
new file mode 100644
index 0000000..d4bc1b8
@@ -0,0 +1,541 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0
Please fix this location.

Quoted 3 lines

I am very sorry, I should have been more carefull. Should I resend whole patchset or just resending this patch is enough?

Just this one? Who do you intend to pick up these patches?

Mesih Kilinc

author

2018-12-02 20:26 UTC #18 lore raw

Re: [PATCH v5 13/17] clk: sunxi-ng: add support for suniv F1C100s SoC

Quoted 16 lines · Stephen Boyd

Quoting Mesih Kilinc (2018-11-28 22:39:52)
Quoted 15 lines · Stephen Boyd
Quoted 13 lines
Quoting Mesih Kilinc (2018-11-28 14:33:23)
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c line 4
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c new file +4 -0
new file mode 100644
index 0000000..d4bc1b8
@@ -0,0 +1,541 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0
Please fix this location.

Quoted 6 lines

Quoted 3 lines
I am very sorry, I should have been more carefull. Should I resend whole patchset or just resending this patch is enough?
Just this one? Who do you intend to pick up these patches?

I have send as v6 patchset. Thanks!

Mesih

Mesih Kilinc

author

2018-11-28 22:33 UTC #19 lore raw

PATCH v5 14/17 dt-bindings: sram: Add Allwinner suniv F1C100s

In reply to Mesih Kilinc

The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10. Add compatible string for it.

Signed-off-by Mesih Kilinc <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/sram/sunxi-sram.txt +4 -0

index 62dd074..5c84850 100644
@@ -19,6 +19,7 @@ Required properties:
     - "allwinner,sun50i-a64-sram-controller" (deprecated)
     - "allwinner,sun50i-a64-system-control"
     - "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control"
+    - "allwinner,suniv-f1c100s-system-control", "allwinner,sun4i-a10-system-control"
 - reg : sram controller register offset + length
 
 SRAM nodes

@@ -58,6 +59,9 @@ The valid sections compatible for A64 are:
 The valid sections compatible for H6 are:
     - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c
 
+The valid sections compatible for F1C100s are:
+    - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d
+
 Devices using SRAM sections
 ---------------------------

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #20 lore raw

PATCH v5 15/17 dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt

In reply to Mesih Kilinc

Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31. Add definition for it.

Signed-off-by Mesih Kilinc <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +1 -0

index ed11ce0..4605525 100644
@@ -6,6 +6,7 @@ Required properties:
 	"allwinner,sun4i-a10-wdt"
 	"allwinner,sun6i-a31-wdt"
 	"allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
+	"allwinner,suniv-f1c100s-wdt", "allwinner,sun4i-a10-wdt"
 - reg : Specifies base physical address and size of the registers.
 
 Optional properties:

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #21 lore raw

PATCH v5 16/17 ARM: dts: suniv: add initial DTSI file for F1C100s

In reply to Mesih Kilinc

F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it.

Signed-off-by Mesih Kilinc <[email protected]>

---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi

arch/arm/boot/dts/suniv-f1c100s.dtsi new file +147 -0

new file mode 100644
index 0000000..aff5f90
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <[email protected]>
+ * Copyright 2018 Mesih Kilinc <[email protected]>
+ */
+
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&intc>;
+
+	clocks {
+		osc24M: clk-24M {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: clk-32k {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+	};
+
+	cpus {
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram-controller at 1c00000 {
+			compatible = "allwinner,suniv-f1c100s-system-control",
+				     "allwinner,sun4i-a10-system-control";
+			reg = <0x01c00000 0x30>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_d: sram at 10000 {
+				compatible = "mmio-sram";
+				reg = <0x00010000 0x1000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00010000 0x1000>;
+
+				otg_sram: sram-section at 0 {
+					compatible = "allwinner,suniv-f1c100s-sram-d",
+						     "allwinner,sun4i-a10-sram-d";
+					reg = <0x0000 0x1000>;
+					status = "disabled";
+				};
+			};
+		};
+
+		ccu: clock at 1c20000 {
+			compatible = "allwinner,suniv-f1c100s-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		intc: interrupt-controller at 1c20400 {
+			compatible = "allwinner,suniv-f1c100s-ic";
+			reg = <0x01c20400 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		pio: pinctrl at 1c20800 {
+			compatible = "allwinner,suniv-f1c100s-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <38>, <39>, <40>;
+			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#gpio-cells = <3>;
+
+			uart0_pe_pins: uart0-pe-pins {
+				pins = "PE0", "PE1";
+				function = "uart0";
+			};
+		};
+
+		timer at 1c20c00 {
+			compatible = "allwinner,suniv-f1c100s-timer";
+			reg = <0x01c20c00 0x90>;
+			interrupts = <13>;
+			clocks = <&osc24M>;
+		};
+
+		wdt: watchdog at 1c20ca0 {
+			compatible = "allwinner,suniv-f1c100s-wdt",
+				     "allwinner,sun4i-a10-wdt";
+			reg = <0x01c20ca0 0x20>;
+		};
+
+		uart0: serial at 1c25000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c25000 0x400>;
+			interrupts = <1>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu 38>;
+			resets = <&ccu 24>;
+			status = "disabled";
+		};
+
+		uart1: serial at 1c25400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c25400 0x400>;
+			interrupts = <2>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu 39>;
+			resets = <&ccu 25>;
+			status = "disabled";
+		};
+
+		uart2: serial at 1c25800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c25800 0x400>;
+			interrupts = <3>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu 40>;
+			resets = <&ccu 26>;
+			status = "disabled";
+		};
+	};
+};

Signature · 1 line

2.7.4

Mesih Kilinc

author

2018-11-28 22:33 UTC #22 lore raw

PATCH v5 17/17 ARM: suniv: f1c100s: add device tree for Lichee Pi Nano

In reply to Mesih Kilinc

Lichee Pi Nano is a F1C100s board by Lichee Pi.

Add initial device tree for it.

Signed-off-by Icenowy Zheng <[email protected]>

Signed-off-by Mesih Kilinc <[email protected]>

---
 arch/arm/boot/dts/Makefile                        |  2 ++
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 26 +++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts

arch/arm/boot/dts/Makefile +2 -0

index b0e966d..2b96a5b 100644
@@ -1066,6 +1066,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
+dtb-$(CONFIG_MACH_SUNIV) += \
+	suniv-f1c100s-licheepi-nano.dtb
 dtb-$(CONFIG_ARCH_TANGO) += \
 	tango4-vantage-1172.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \

arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts new file +26 -0

new file mode 100644
index 0000000..a1154e6
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <[email protected]>
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+/ {
+	model = "Lichee Pi Nano";
+	compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pe_pins>;
+	status = "okay";
+};

Signature · 1 line

2.7.4

Priit Laes

2018-11-29 21:47 UTC #23 lore raw

In reply to Mesih Kilinc

Quoted 2 lines · Mesih Kilinc

This is the fifth version of patchset for Allwinner ARMv5 F1C100s SoC. Addressed comments from Maxime Ripard and Rob Herring, added signatures.

IIRC, the original author of these patches was Icenowy, what happened to this?

Quoted 127 lines

Changes since v4:
- Patch "dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl"
- This patch applied for 4.21.
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)"
- This patch applied for 4.21.
- Patch "dt-bindings: clock: Add Allwinner suniv F1C100s CCU"
- Fixed license identifier position
- Added DMA fields.
- Patch "clk: sunxi-ng: add support for suniv F1C100s SoC"
- Added DMA reset and clock support.
- Patch "ARM: dts: suniv: add initial DTSI file for F1C100s"
- Remove dt-binding headers.
- Fix uart0 pin label.
- Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano"
- Fix uart0 pin label.
Changes since v3:
- Patch "ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs"
- Remove CONFIG_ARCH_SUNXI_Vx. Use ARCH_MULTI_Vx to differentiate SoC's
- Change KConfig ARCH_SUNXI selection: 'select' to 'default'.
- Patch "irqchip/sun4i: Add a struct to hold global variables"
- Split irq_sun4i.c changes to 3 patch.
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)"
- pinctrl-suniv-f1c100s: remove: disable_strict_mode = true
- Patch "ARM: dts: suniv: add initial DTSI file for F1C100s"
- suniv-f1c100s.dtsi: remove unnecessary componenets.
- Instead of patching drivers, add original compatible string with
f1c100s compatibles.
- Add Acked-by signatures.
Changes since v2:
- Patch "ARM: sunxi: add Allwinner ARMv5 SoCs"
- Move SUN4I_TIMER option to ARCH_SUNXI
- Added help text for MACH_SUNIV
- Patch "irqchip/sun4i: add support for suniv interrupt controller"
- Defined sunxi_irq_chip_data struct and used it to differentiate registers between different chips.
- Patch " ARM: dts: suniv: add initial DTSI file for F1C100s"
- Removed unnecessary fake clock.
- Fixed compatible strings.
Changes since v1:
- Patch "ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs"
- Instead of using a common bool config use a common menuconfig.
- Use ARCH_MULTI_V7 to differentiate V7 SoCs.
- Addressed comment from Julian Calaby
- Patch "ARM: sunxi: add Allwinner ARMv5 SoCs"
- Use ARCH_MULTI_V5 to differentiate V5 SoCs.
- removed "allwinner,suniv" board compatible string
- Added dt-bindings
- Patch "irqchip/sun4i: add support for suniv interrupt controller"
- Added dt-bindings
- Changed "allwinner,suniv-ic" to "allwinner,suniv-f1c100s-ic"
- Patch "clocksource: sun4i: add a compatible for suniv"
- Added dt-bindings
- Changed "allwinner,suniv-timer" to "allwinner,suniv-f1c100s-timer"
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)"
- Added dt-bindings
- Renamed suniv-pinctrl to suniv-f1c100s-pinctrl
- Patch "clk: sunxi-ng: add support for suniv F1C100s SoC"
- Added dt-bindings
- Renamed suniv-ccu to suniv-f1c100s-ccu
- Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano"
- Addressed comment from Rask Ingemann Lambertsen
Thanks!
Mesih Kilinc (17):
ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs
dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC
ARM: sunxi: add Allwinner ARMv5 SoCs
dt-bindings: interrupt-controller: Add suniv interrupt-controller irqchip/sun4i: Add a struct to hold global variables irqchip/sun4i: Move IC specific register offsets to struct irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s
dt-bindings: timer: Add Allwinner suniv timer
clocksource: sun4i: add a compatible for suniv
dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl
pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
clk: sunxi-ng: add support for suniv F1C100s SoC
dt-bindings: sram: Add Allwinner suniv F1C100s
dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt
ARM: dts: suniv: add initial DTSI file for F1C100s
ARM: suniv: f1c100s: add device tree for Lichee Pi Nano
 Documentation/devicetree/bindings/arm/sunxi.txt    |   1 +
 .../devicetree/bindings/clock/sunxi-ccu.txt        |   1 +
 .../interrupt-controller/allwinner,sun4i-ic.txt    |   4 +-
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 .../devicetree/bindings/sram/sunxi-sram.txt        |   4 +
 .../bindings/timer/allwinner,sun4i-timer.txt       |   4 +-
 .../devicetree/bindings/watchdog/sunxi-wdt.txt     |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  |  26 +
 arch/arm/boot/dts/suniv-f1c100s.dtsi               | 147 ++++++
 arch/arm/mach-sunxi/Kconfig                        |  19 +-
 arch/arm/mach-sunxi/sunxi.c                        |  10 +
 drivers/clk/sunxi-ng/Kconfig                       |   5 +
 drivers/clk/sunxi-ng/Makefile                      |   1 +
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c           | 541 +++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h           |  34 ++
 drivers/clocksource/sun4i_timer.c                  |   5 +-
 drivers/irqchip/irq-sun4i.c                        | 106 ++--
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c      | 416 ++++++++++++++++
 include/dt-bindings/clock/suniv-ccu-f1c100s.h      |  70 +++
 include/dt-bindings/reset/suniv-ccu-f1c100s.h      |  38 ++
 23 files changed, 1408 insertions(+), 33 deletions(-)
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
 create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
 create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h
Signature · 6 lines
2.7.4

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Icenowy Zheng

2018-11-29 23:45 UTC #24 lore raw

于 2018年11月30日 GMT+08:00 上午5:47:30, Priit Laes <plaes-q/[email protected]> 写到:

Quoted 7 lines · Mesih Kilinc

Quoted 2 lines
This is the fifth version of patchset for Allwinner ARMv5 F1C100s SoC. Addressed comments from Maxime Ripard and Rob Herring, added
signatures.
IIRC, the original author of these patches was Icenowy, what happened to this?

I lost interest on maintaining this.

Quoted 137 lines

Quoted 5 lines
Changes since v4:
- Patch "dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl"
- This patch applied for 4.21.
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer
F-series SoCs)"
Quoted 12 lines
- This patch applied for 4.21.
- Patch "dt-bindings: clock: Add Allwinner suniv F1C100s CCU"
- Fixed license identifier position
- Added DMA fields.
- Patch "clk: sunxi-ng: add support for suniv F1C100s SoC"
- Added DMA reset and clock support.
- Patch "ARM: dts: suniv: add initial DTSI file for F1C100s"
- Remove dt-binding headers.
- Fix uart0 pin label.
- Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano"
- Fix uart0 pin label.
Quoted 2 lines
Changes since v3:
- Patch "ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner
SoCs"
Quoted 1 line
- Remove CONFIG_ARCH_SUNXI_Vx. Use ARCH_MULTI_Vx to differentiate
SoC's
Quoted 4 lines
- Change KConfig ARCH_SUNXI selection: 'select' to 'default'.
- Patch "irqchip/sun4i: Add a struct to hold global variables"
- Split irq_sun4i.c changes to 3 patch.
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer
F-series SoCs)"
Quoted 18 lines
- pinctrl-suniv-f1c100s: remove: disable_strict_mode = true
- Patch "ARM: dts: suniv: add initial DTSI file for F1C100s"
- suniv-f1c100s.dtsi: remove unnecessary componenets.
- Instead of patching drivers, add original compatible string with
f1c100s compatibles.
- Add Acked-by signatures.
Changes since v2:
- Patch "ARM: sunxi: add Allwinner ARMv5 SoCs"
- Move SUN4I_TIMER option to ARCH_SUNXI
- Added help text for MACH_SUNIV
- Patch "irqchip/sun4i: add support for suniv interrupt controller"
- Defined sunxi_irq_chip_data struct and used it to differentiate registers between different chips.
- Patch " ARM: dts: suniv: add initial DTSI file for F1C100s"
- Removed unnecessary fake clock.
- Fixed compatible strings.
Quoted 16 lines
Changes since v1:
- Patch "ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs"
- Instead of using a common bool config use a common menuconfig.
- Use ARCH_MULTI_V7 to differentiate V7 SoCs.
- Addressed comment from Julian Calaby
- Patch "ARM: sunxi: add Allwinner ARMv5 SoCs"
- Use ARCH_MULTI_V5 to differentiate V5 SoCs.
- removed "allwinner,suniv" board compatible string
- Added dt-bindings
- Patch "irqchip/sun4i: add support for suniv interrupt controller"
- Added dt-bindings
- Changed "allwinner,suniv-ic" to "allwinner,suniv-f1c100s-ic"
- Patch "clocksource: sun4i: add a compatible for suniv"
- Added dt-bindings
- Changed "allwinner,suniv-timer" to
"allwinner,suniv-f1c100s-timer"
Quoted 1 line
- Patch "pinctrl: sunxi: add support for suniv F1C100s (newer
F-series SoCs)"
Quoted 29 lines
- Added dt-bindings
- Renamed suniv-pinctrl to suniv-f1c100s-pinctrl
- Patch "clk: sunxi-ng: add support for suniv F1C100s SoC"
- Added dt-bindings
- Renamed suniv-ccu to suniv-f1c100s-ccu
- Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano"
- Addressed comment from Rask Ingemann Lambertsen
Thanks!
Mesih Kilinc (17):
ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs
dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC
ARM: sunxi: add Allwinner ARMv5 SoCs
dt-bindings: interrupt-controller: Add suniv interrupt-controller irqchip/sun4i: Add a struct to hold global variables irqchip/sun4i: Move IC specific register offsets to struct irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s
dt-bindings: timer: Add Allwinner suniv timer
clocksource: sun4i: add a compatible for suniv
dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl
pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
clk: sunxi-ng: add support for suniv F1C100s SoC
dt-bindings: sram: Add Allwinner suniv F1C100s
dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt
ARM: dts: suniv: add initial DTSI file for F1C100s
ARM: suniv: f1c100s: add device tree for Lichee Pi Nano
Quoted 15 lines
 Documentation/devicetree/bindings/arm/sunxi.txt    |   1 +
 .../devicetree/bindings/clock/sunxi-ccu.txt        |   1 +
 .../interrupt-controller/allwinner,sun4i-ic.txt    |   4 +-
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 .../devicetree/bindings/sram/sunxi-sram.txt        |   4 +
 .../bindings/timer/allwinner,sun4i-timer.txt       |   4 +-
 .../devicetree/bindings/watchdog/sunxi-wdt.txt     |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  |  26 +
 arch/arm/boot/dts/suniv-f1c100s.dtsi               | 147 ++++++
 arch/arm/mach-sunxi/Kconfig                        |  19 +-
 arch/arm/mach-sunxi/sunxi.c                        |  10 +
 drivers/clk/sunxi-ng/Kconfig                       |   5 +
 drivers/clk/sunxi-ng/Makefile                      |   1 +
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c           | 541
+++++++++++++++++++++
Quoted 6 lines
 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h           |  34 ++
 drivers/clocksource/sun4i_timer.c                  |   5 +-
 drivers/irqchip/irq-sun4i.c                        | 106 ++--
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c      | 416
++++++++++++++++
Quoted 16 lines
 include/dt-bindings/clock/suniv-ccu-f1c100s.h      |  70 +++
 include/dt-bindings/reset/suniv-ccu-f1c100s.h      |  38 ++
 23 files changed, 1408 insertions(+), 33 deletions(-)
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
 create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
 create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h
Signature · 4 lines
2.7.4

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Quoted 1 line
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