MIPS: CI20: DTS: Add nodes to Creator CI20 board

PATCH Applied Alexandre GRIVEAUX 2 participants 12 messages Oct 1, 2019 – Oct 7, 2019

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Device tree bindings MIPS Ingenic JZ47xx SoCs

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Alexandre GRIVEAUX

author

2019-10-01 19:08 UTC #0 lore raw

v2 cover MIPS: CI20: DTS: Add nodes to Creator CI20 board

Attemping to make my CI20 more usefull than a paperweight, I add nodes to Devicetree, at this time:

- Add I2C node PMU and RTC.
- The IW8103 need some work to stay alive because power seem to turn off.
- The leds patch lack of correct option in ci20_defconfig.
- The Cpu patch isn't usefull without SMP support of jz4780.

Alexandre GRIVEAUX (5):
MIPS: JZ4780: DTS: Add I2C nodes
MIPS: CI20: DTS: Add I2C nodes
MIPS: CI20: DTS: Add IW8103 Wifi + bluetooth
MIPS: CI20: DTS: Add Leds
MIPS: JZ4780: DTS: Add CPU nodes

v2 adding previous sended patch: JZ4780: DTS: Add I2C nodes

 arch/mips/boot/dts/ingenic/ci20.dts    | 214 +++++++++++++++++++++++++
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 103 ++++++++++++
 2 files changed, 317 insertions(+)

base-commit: 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c

Signature · 1 line

2.20.1

Alexandre GRIVEAUX

author

2019-10-01 19:08 UTC #1 lore raw

PATCH v2 1/5 MIPS: JZ4780: DTS: Add I2C nodes

Add the devicetree nodes for the I2C core of the JZ4780 SoC, disabled by default.

Signed-off-by Alexandre GRIVEAUX <[email protected]>

---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 86 ++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

arch/mips/boot/dts/ingenic/jz4780.dtsi +86 -0

index c54bd7cfec55..f928329b034b 100644
@@ -262,6 +262,92 @@
 		status = "disabled";
 	};
 
+	i2c0: i2c@10050000 {
+		compatible = "ingenic,jz4780-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg = <0x10050000 0x1000>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <60>;
+
+		clocks = <&cgu JZ4780_CLK_SMB0>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pins_i2c0_data>;
+
+		status = "disabled";
+	};
+
+	i2c1: i2c@10051000 {
+		compatible = "ingenic,jz4780-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x10051000 0x1000>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <59>;
+
+		clocks = <&cgu JZ4780_CLK_SMB1>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pins_i2c1_data>;
+
+		status = "disabled";
+	};
+
+	i2c2: i2c@10052000 {
+		compatible = "ingenic,jz4780-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x10052000 0x1000>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <58>;
+
+		clocks = <&cgu JZ4780_CLK_SMB2>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pins_i2c2_data>;
+
+		status = "disabled";
+	};
+
+	i2c3: i2c@10053000 {
+		compatible = "ingenic,jz4780-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x10053000 0x1000>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <57>;
+
+		clocks = <&cgu JZ4780_CLK_SMB3>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pins_i2c3_data>;
+
+		status = "disabled";
+	};
+
+	i2c4: i2c@10054000 {
+		compatible = "ingenic,jz4780-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x10054000 0x1000>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <56>;
+
+		clocks = <&cgu JZ4780_CLK_SMB4>;
+		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pins_i2c4_data>;
+
+		status = "disabled";
+	};
+
 	watchdog: watchdog@10002000 {
 		compatible = "ingenic,jz4780-watchdog";
 		reg = <0x10002000 0x10>;

Signature · 1 line

2.20.1

Paul Burton

Applied

2019-10-07 17:53 UTC #2 lore raw

Re: [PATCH v2 1/5] MIPS: JZ4780: DTS: Add I2C nodes

Hello,

Quoted 2 lines · Alexandre GRIVEAUX

Add the devicetree nodes for the I2C core of the JZ4780 SoC, disabled by default.

Applied to mips-next.

Quoted 5 lines

commit f56a040c9faf
https://git.kernel.org/mips/c/f56a040c9faf
Signed-off-by Alexandre GRIVEAUX <[email protected]>
Signed-off-by Paul Burton <[email protected]>

Thanks,
Paul

[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]

Alexandre GRIVEAUX

author

2019-10-01 19:09 UTC #3 lore raw

PATCH v2 2/5 MIPS: CI20: DTS: Add I2C nodes

In reply to Alexandre GRIVEAUX

Adding missing I2C nodes and some peripheral:
- PMU
- RTC

Signed-off-by Alexandre GRIVEAUX <[email protected]>

---
 arch/mips/boot/dts/ingenic/ci20.dts | 147 ++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

arch/mips/boot/dts/ingenic/ci20.dts +147 -0

index 2e9952311ecd..4a77fa30a9cd 100644
@@ -87,6 +87,123 @@
 	pinctrl-0 = <&pins_uart4>;
 };
 
+&i2c0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_i2c0>;
+
+	clock-frequency = <400000>;
+
+	act8600: act8600@5a {
+		compatible = "active-semi,act8600";
+		reg = <0x5a>;
+		status = "okay";
+
+		regulators {
+			vddcore: SUDCDC1 {
+				regulator-name = "VDDCORE";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+			vddmem: SUDCDC2 {
+				regulator-name = "VDDMEM";
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+			};
+			vcc_33: SUDCDC3 {
+				regulator-name = "VCC33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+			vcc_50: SUDCDC4 {
+				regulator-name = "VCC50";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				regulator-always-on;
+			};
+			vcc_25: LDO_REG5 {
+				regulator-name = "VCC25";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-always-on;
+			};
+			wifi_io: LDO_REG6 {
+				regulator-name = "WIFIIO";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-always-on;
+			};
+			vcc_28: LDO_REG7 {
+				regulator-name = "VCC28";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+			};
+			vcc_15: LDO_REG8 {
+				regulator-name = "VCC15";
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+			};
+			vcc_18: LDO_REG9 {
+				regulator-name = "VCC18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+			vcc_11: LDO_REG10 {
+				regulator-name = "VCC11";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_i2c1>;
+
+};
+
+&i2c2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_i2c2>;
+
+};
+
+&i2c3 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_i2c3>;
+
+};
+
+&i2c4 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_i2c4>;
+
+	clock-frequency = <400000>;
+
+		rtc@51 {
+			compatible = "nxp,pcf8563";
+			reg = <0x51>;
+			interrupts = <110>;
+		};
+};
+
 &nemc {
 	status = "okay";

@@ -209,6 +326,36 @@
 		bias-disable;
 	};
 
+	pins_i2c0: i2c0 {
+		function = "i2c0";
+		groups = "i2c0-data";
+		bias-disable;
+	};
+
+	pins_i2c1: i2c1 {
+		function = "i2c1";
+		groups = "i2c1-data";
+		bias-disable;
+	};
+
+	pins_i2c2: i2c2 {
+		function = "i2c2";
+		groups = "i2c2-data";
+		bias-disable;
+	};
+
+	pins_i2c3: i2c3 {
+		function = "i2c3";
+		groups = "i2c3-data";
+		bias-disable;
+	};
+
+	pins_i2c4: i2c4 {
+		function = "i2c4";
+		groups = "i2c4-data-e";
+		bias-disable;
+	};
+
 	pins_nemc: nemc {
 		function = "nemc";
 		groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";

Signature · 1 line

2.20.1

Paul Burton

Applied

2019-10-07 17:53 UTC #4 lore raw

Re: [PATCH v2 2/5] MIPS: CI20: DTS: Add I2C nodes

Hello,

Quoted 3 lines · Alexandre GRIVEAUX

Adding missing I2C nodes and some peripheral:
- PMU
- RTC

Applied to mips-next.

Quoted 5 lines

commit 73f2b940474d
https://git.kernel.org/mips/c/73f2b940474d
Signed-off-by Alexandre GRIVEAUX <[email protected]>
Signed-off-by Paul Burton <[email protected]>

Thanks,
Paul

[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]

Alexandre GRIVEAUX

author

2019-10-01 19:09 UTC #5 lore raw

PATCH v2 3/5 MIPS: CI20: DTS: Add IW8103 Wifi + bluetooth

In reply to Alexandre GRIVEAUX

Add IW8103 Wifi + bluetooth module to device tree and related power domain.

Signed-off-by Alexandre GRIVEAUX <[email protected]>

---
 arch/mips/boot/dts/ingenic/ci20.dts | 39 +++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

arch/mips/boot/dts/ingenic/ci20.dts +39 -0

index 4a77fa30a9cd..c62c36ae94c2 100644
@@ -31,6 +31,13 @@
 		gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
 		enable-active-high;
 	};
+
+	wlan0_power: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "wlan0_power";
+		gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
+		enable-active-high;
+	};
 };
 
 &ext {

@@ -54,9 +61,18 @@
 
 	bus-width = <4>;
 	max-frequency = <50000000>;
+	non-removable;
 
 	pinctrl-names = "default";
 	pinctrl-0 = <&pins_mmc1>;
+
+	brcmf: wifi@1 {
+/*		reg = <4>;*/
+		compatible = "brcm,bcm4330-fmac";
+		vcc-supply = <&wlan0_power>;
+		device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &uart0 {

@@ -73,6 +89,23 @@
 	pinctrl-0 = <&pins_uart1>;
 };
 
+&uart2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_uart2>;
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm4330-bt";
+		reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>;
+		vcc-supply = <&wlan0_power>;
+		device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &uart3 {
 	status = "okay";

@@ -314,6 +347,12 @@
 		bias-disable;
 	};
 
+	pins_uart2: uart2 {
+		function = "uart2";
+		groups = "uart2-data", "uart2-hwflow";
+		bias-disable;
+	};
+
 	pins_uart3: uart3 {
 		function = "uart3";
 		groups = "uart3-data", "uart3-hwflow";

Signature · 1 line

2.20.1

Paul Burton

Applied

2019-10-07 17:53 UTC #6 lore raw

Re: [PATCH v2 3/5] MIPS: CI20: DTS: Add IW8103 Wifi + bluetooth

Hello,

Quoted 1 line · Alexandre GRIVEAUX

Add IW8103 Wifi + bluetooth module to device tree and related power domain.

Applied to mips-next.

Quoted 5 lines

commit 948f2708f945
https://git.kernel.org/mips/c/948f2708f945
Signed-off-by Alexandre GRIVEAUX <[email protected]>
Signed-off-by Paul Burton <[email protected]>

Thanks,
Paul

[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]

Alexandre GRIVEAUX

author

2019-10-01 19:09 UTC #7 lore raw

PATCH v2 4/5 MIPS: CI20: DTS: Add Leds

In reply to Alexandre GRIVEAUX

Adding leds and related triggers.

Signed-off-by Alexandre GRIVEAUX <[email protected]>

---
 arch/mips/boot/dts/ingenic/ci20.dts | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

arch/mips/boot/dts/ingenic/ci20.dts +28 -0

index c62c36ae94c2..37b93166bf22 100644
@@ -25,6 +25,34 @@
 		       0x30000000 0x30000000>;
 	};
 
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			label = "ci20:red:led0";
+			gpios = <&gpc 3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "none";
+		};
+
+		led1 {
+			label = "ci20:red:led1";
+			gpios = <&gpc 2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "nand-disk";
+		};
+
+		led2 {
+			label = "ci20:red:led2";
+			gpios = <&gpc 1 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "cpu1";
+		};
+
+		led3 {
+			label = "ci20:red:led3";
+			gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "cpu0";
+		};
+	};
+
 	eth0_power: fixedregulator@0 {
 		compatible = "regulator-fixed";
 		regulator-name = "eth0_power";

Signature · 1 line

2.20.1

Paul Burton

Applied

2019-10-07 17:53 UTC #8 lore raw

Re: [PATCH v2 4/5] MIPS: CI20: DTS: Add Leds

Hello,

Quoted 1 line · Alexandre GRIVEAUX

Adding leds and related triggers.

Applied to mips-next.

Quoted 5 lines

commit 24b0cb4f883a
https://git.kernel.org/mips/c/24b0cb4f883a
Signed-off-by Alexandre GRIVEAUX <[email protected]>
Signed-off-by Paul Burton <[email protected]>

Thanks,
Paul

[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]

Alexandre GRIVEAUX

author

2019-10-01 19:09 UTC #9 lore raw

PATCH v2 5/5 MIPS: JZ4780: DTS: Add CPU nodes

In reply to Alexandre GRIVEAUX

The JZ4780 have 2 core, adding to DT.

Signed-off-by Alexandre GRIVEAUX <[email protected]>

---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

arch/mips/boot/dts/ingenic/jz4780.dtsi +17 -0

index f928329b034b..9c7346724f1f 100644
@@ -7,6 +7,23 @@
 	#size-cells = <1>;
 	compatible = "ingenic,jz4780";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "ingenic,jz4780";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "ingenic,jz4780";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;

Signature · 1 line

2.20.1

Paul Burton

2019-10-01 23:20 UTC #10 lore raw

Re: [PATCH v2 5/5] MIPS: JZ4780: DTS: Add CPU nodes

Hi Alexandre,

Quoted 12 lines · Alexandre GRIVEAUX

The JZ4780 have 2 core, adding to DT.
Signed-off-by Alexandre GRIVEAUX <[email protected]>
---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
arch/mips/boot/dts/ingenic/jz4780.dtsi +0 -0
index f928329b034b..9c7346724f1f 100644

arch/mips/boot/dts/ingenic/jz4780.dtsi line 15

Quoted 9 lines

arch/mips/boot/dts/ingenic/jz4780.dtsi +6 -0

@@ -7,6 +7,23 @@
 	#size-cells = <1>;
 	compatible = "ingenic,jz4780";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "ingenic,jz4780";

This should probably be something like ingenic,xburst2. JZ4780 is the SoC. It also should be a documented binding, but I think it would be worth holding off on the whole thing until we actually get SMP support merged - just in case we come up with a binding that doesn't actually work out.

So I expect I'll just apply patches 1-4 for now.

Thanks for working on it!

Paul

Quoted 17 lines

arch/mips/boot/dts/ingenic/jz4780.dtsi +11 -0

+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "ingenic,jz4780";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;

Signature · 1 line

2.20.1

Alexandre GRIVEAUX

author

2019-10-02 19:07 UTC #11 lore raw

Re: [PATCH v2 5/5] MIPS: JZ4780: DTS: Add CPU nodes

Hi Paul and other.

Quoted 10 lines

Hi Alexandre,
This should probably be something like ingenic,xburst2. JZ4780 is the SoC. It also should be a documented binding, but I think it would be worth holding off on the whole thing until we actually get SMP support merged - just in case we come up with a binding that doesn't actually work out.
So I expect I'll just apply patches 1-4 for now.
Thanks for working on it!

I holding the CPU patch at this time for more work later, I would like to upstream some patchs from this repository:

https://github.com/MIPS/CI20_linux.git

How i can do that and keep the contributors history ?

Thanks for the help.

Ps: I try to unban my e-mail server from office365...