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dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

PATCH Superseded Alexander Gordeev 1 participant 2 messages Oct 16, 2019 dmaengine

v3 of 5 Superseded Latest is v5 →

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v3 cover dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

This series is against v5.4-rc3

I am posting "avalon-dma" update alone and going to post "avalon-test" update as a follow-up or in the next round.

Changes since v2:
- avalon_dma_register() return value bug fixed;
- device_prep_slave_sg() does not crash dmaengine_prep_slave_single() now;
- kernel configuration options removed in favour of module parameters;
- BUG_ONs, WARN_ONs and dev_dbgs removed;
- goto labels renamed, other style issues addressed;
- polling loop in interrupt handler commented;

Changes since v1:
- "avalon-dma" converted to "dmaengine" model;
- "avalon-drv" renamed to "avalon-test";

The Avalon-MM DMA Interface for PCIe is a design used in hard IPs for Intel Arria, Cyclone or Stratix FPGAs. It transfers data between on-chip memory and system memory.

Testing was done using a custom FPGA build with Arria 10 FPGA streaming data to target device RAM:

  +----------+    +----------+    +----------+        +----------+
  | Nios CPU |<-->|   RAM    |<-->|  Avalon  |<-PCIe->| Host CPU |
  +----------+    +----------+    +----------+        +----------+

The RAM was examined for data integrity by examining RAM contents from host CPU (indirectly - checking data DMAed to the system) and from Nios CPU that has direct access to the device RAM. A companion tool using "avalon-test" driver was used to DMA files to the device:
https://github.com/a-gordeev/avalon-tool.git

Alexander Gordeev (1):
dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

 drivers/dma/Kconfig              |   2 +
 drivers/dma/Makefile             |   1 +
 drivers/dma/avalon/Kconfig       |  14 +
 drivers/dma/avalon/Makefile      |   6 +
 drivers/dma/avalon/avalon-core.c | 476 +++++++++++++++++++++++++++++++
 drivers/dma/avalon/avalon-core.h |  92 ++++++
 drivers/dma/avalon/avalon-hw.c   | 186 ++++++++++++
 drivers/dma/avalon/avalon-hw.h   |  85 ++++++
 drivers/dma/avalon/avalon-pci.c  | 144 ++++++++++
 9 files changed, 1006 insertions(+)
 create mode 100644 drivers/dma/avalon/Kconfig
 create mode 100644 drivers/dma/avalon/Makefile
 create mode 100644 drivers/dma/avalon/avalon-core.c
 create mode 100644 drivers/dma/avalon/avalon-core.h
 create mode 100644 drivers/dma/avalon/avalon-hw.c
 create mode 100644 drivers/dma/avalon/avalon-hw.h
 create mode 100644 drivers/dma/avalon/avalon-pci.c

Because the amount of changes since the previous version is quite big, I am also posting the interdiff.

drivers/dma/avalon/Kconfig +0 -74
diff -u b/drivers/dma/avalon/Kconfig b/drivers/dma/avalon/Kconfig
@@ -15,74 +14,0 @@
-
-if AVALON_DMA
-
-config AVALON_DMA_MASK_WIDTH
-	int "Avalon DMA streaming and coherent bitmask width"
-	range 0 64
-	default 64
-	help
-	  Width of bitmask for streaming and coherent DMA operations
-
-config AVALON_DMA_CTRL_BASE
-	hex "Avalon DMA controllers base"
-	default "0x00000000"
-
-config AVALON_DMA_RD_EP_DST_LO
-	hex "Avalon DMA read controller base low"
-	default "0x80000000"
-	help
-	  Specifies the lower 32-bits of the base address of the read
-	  status and descriptor table in the Root Complex memory.
-
-config AVALON_DMA_RD_EP_DST_HI
-	hex "Avalon DMA read controller base high"
-	default "0x00000000"
-	help
-	  Specifies the upper 32-bits of the base address of the read
-	  status and descriptor table in the Root Complex memory.
-
-config AVALON_DMA_WR_EP_DST_LO
-	hex "Avalon DMA write controller base low"
-	default "0x80002000"
-	help
-	  Specifies the lower 32-bits of the base address of the write
-	  status and descriptor table in the Root Complex memory.
-
-config AVALON_DMA_WR_EP_DST_HI
-	hex "Avalon DMA write controller base high"
-	default "0x00000000"
-	help
-	  Specifies the upper 32-bits of the base address of the write
-	  status and descriptor table in the Root Complex memory.
-
-config AVALON_DMA_PCI_VENDOR_ID
-	hex "PCI vendor ID"
-	default "0x1172"
-
-config AVALON_DMA_PCI_DEVICE_ID
-	hex "PCI device ID"
-	default "0xe003"
-
-config AVALON_DMA_PCI_BAR
-	int "PCI device BAR the Avalon DMA controller is mapped to"
-	range 0 5
-	default 0
-	help
-	  Number of PCI BAR the DMA controller is mapped to
-
-config AVALON_DMA_PCI_MSI_COUNT_ORDER
-	int "Count of MSIs the PCI device provides (order)"
-	range 0 5
-	default 5
-	help
-	  Number of vectors the PCI device uses in multiple MSI mode.
-	  This number is provided as the power of two.
-
-config AVALON_DMA_PCI_MSI_VECTOR
-	int "Vector number the DMA controller is mapped to"
-	range 0 31
-	default 0
-	help
-	  Number of MSI vector the DMA controller is mapped to in
-	  multiple MSI mode.
-
-endif
drivers/dma/avalon/avalon-core.c +112 -68

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drivers/dma/avalon/avalon-core.h +6 -4
diff -u b/drivers/dma/avalon/avalon-core.h b/drivers/dma/avalon/avalon-core.h
@@ -12,6 +12,8 @@
 
 #include "../virt-dma.h"
 
+#include "avalon-hw.h"
+
 struct avalon_dma_desc {
 	struct virt_dma_desc	vdesc;
 
@@ -19,11 +21,11 @@
 
 	dma_addr_t		dev_addr;
 
-	struct scatterlist	*sg;
-	unsigned int		sg_len;
+	unsigned int		seg_curr;
+	unsigned int		seg_off;
 
-	struct scatterlist	*sg_curr;
-	unsigned int		sg_offset;
+	unsigned int		nr_segs;
+	struct dma_segment	seg[];
 };
 
 struct avalon_dma_hw {
drivers/dma/avalon/avalon-hw.c +57 -83

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drivers/dma/avalon/avalon-hw.h +31 -32

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drivers/dma/avalon/avalon-pci.c +43 -49

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Signature · 1 line
2.23.0
#1 lore raw

PATCH v3 1/1 dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe

Support Avalon-MM DMA Interface for PCIe used in hard IPs for Intel Arria, Cyclone or Stratix FPGAs.

---
 drivers/dma/Kconfig              |   2 +
 drivers/dma/Makefile             |   1 +
 drivers/dma/avalon/Kconfig       |  14 +
 drivers/dma/avalon/Makefile      |   6 +
 drivers/dma/avalon/avalon-core.c | 476 +++++++++++++++++++++++++++++++
 drivers/dma/avalon/avalon-core.h |  92 ++++++
 drivers/dma/avalon/avalon-hw.c   | 186 ++++++++++++
 drivers/dma/avalon/avalon-hw.h   |  85 ++++++
 drivers/dma/avalon/avalon-pci.c  | 144 ++++++++++
 9 files changed, 1006 insertions(+)
 create mode 100644 drivers/dma/avalon/Kconfig
 create mode 100644 drivers/dma/avalon/Makefile
 create mode 100644 drivers/dma/avalon/avalon-core.c
 create mode 100644 drivers/dma/avalon/avalon-core.h
 create mode 100644 drivers/dma/avalon/avalon-hw.c
 create mode 100644 drivers/dma/avalon/avalon-hw.h
 create mode 100644 drivers/dma/avalon/avalon-pci.c
drivers/dma/Kconfig +2 -0
index 7af874b69ffb..f6f43480a4a4 100644
@@ -669,6 +669,8 @@ source "drivers/dma/sh/Kconfig"
 
 source "drivers/dma/ti/Kconfig"
 
+source "drivers/dma/avalon/Kconfig"
+
 # clients
 comment "DMA Clients"
 	depends on DMA_ENGINE
drivers/dma/Makefile +1 -0
index f5ce8665e944..fd7e11417b73 100644
@@ -75,6 +75,7 @@ obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
 obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
 obj-$(CONFIG_ZX_DMA) += zx_dma.o
 obj-$(CONFIG_ST_FDMA) += st_fdma.o
+obj-$(CONFIG_AVALON_DMA) += avalon/
 
 obj-y += mediatek/
 obj-y += qcom/
drivers/dma/avalon/Kconfig new file +14 -0
new file mode 100644
index 000000000000..c824f9fa281f
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Avalon DMA engine
+#
+# Author: Alexander Gordeev <[email protected]>
+#
+config AVALON_DMA
+	tristate "Intel Avalon-MM DMA Interface for PCIe"
+	depends on PCI
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  This selects a driver for Avalon-MM DMA Interface for PCIe
+	  hard IP block used in Intel Arria, Cyclone or Stratix FPGAs.
drivers/dma/avalon/Makefile new file +6 -0
new file mode 100644
index 000000000000..4b5278d12f86
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_AVALON_DMA)	+= avalon-dma.o
+
+avalon-dma-objs			:= avalon-hw.o \
+				   avalon-core.o \
+				   avalon-pci.o
drivers/dma/avalon/avalon-core.c new file +476 -0

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drivers/dma/avalon/avalon-core.h new file +92 -0

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drivers/dma/avalon/avalon-hw.c new file +186 -0

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drivers/dma/avalon/avalon-hw.h new file +85 -0

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drivers/dma/avalon/avalon-pci.c new file +144 -0

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Signature · 1 line
2.23.0