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Add LLCC support for SC7180 SoC

PATCH In review Sai Prakash Ranjan 4 participants 15 messages Oct 19, 2019 – Nov 15, 2019

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Sai Prakash Ranjan

author
#0 lore raw

v2 cover Add LLCC support for SC7180 SoC

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

v2:
* Convert bindings to YAML and add compatible for SC7180
* Address Stephen's comments on const

Sai Prakash Ranjan (2):
dt-bindings: msm: Convert LLCC bindings to YAML
dt-bindings: msm: Add LLCC for SC7180

Vivek Gautam (1):
soc: qcom: llcc: Add configuration data for SC7180

 .../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --------------
 .../bindings/arm/msm/qcom,llcc.yaml           | 55 +++++++++++++++++++
 drivers/soc/qcom/llcc-qcom.c                  | 15 ++++-
 3 files changed, 69 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
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author
#1 lore raw

PATCH v2 1/3 soc: qcom: llcc: Add configuration data for SC7180

From: Vivek Gautam <[email protected]>

Add LLCC configuration data for SC7180 SoC which controls LLCC behaviour.

Signed-off-by Vivek Gautam <[email protected]>
Signed-off-by Sai Prakash Ranjan <[email protected]>
---
 drivers/soc/qcom/llcc-qcom.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)
drivers/soc/qcom/llcc-qcom.c +14 -1
index 4bd982a294ce..429b5a60a1ba 100644
@@ -91,7 +91,14 @@ struct qcom_llcc_config {
 	int size;
 };
 
-static struct llcc_slice_config sdm845_data[] =  {
+static const struct llcc_slice_config sc7180_data[] =  {
+	{ LLCC_CPUSS,    1,  256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
+	{ LLCC_MDM,      8,  128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
+	{ LLCC_GPUHTW,   11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
+	{ LLCC_GPU,      12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
+};
+
+static const struct llcc_slice_config sdm845_data[] =  {
 	{ LLCC_CPUSS,    1,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 1 },
 	{ LLCC_VIDSC0,   2,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },
 	{ LLCC_VIDSC1,   3,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },

@@ -112,6 +119,11 @@ static struct llcc_slice_config sdm845_data[] =  {
 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xffc, 0x2,   0, 0, 1, 1, 0 },
 };
 
+static const struct qcom_llcc_config sc7180_cfg = {
+	.sct_data	= sc7180_data,
+	.size		= ARRAY_SIZE(sc7180_data),
+};
+
 static const struct qcom_llcc_config sdm845_cfg = {
 	.sct_data	= sdm845_data,
 	.size		= ARRAY_SIZE(sdm845_data),

@@ -485,6 +497,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
+	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
 	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
 	{ }
 };
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author
#3 lore raw

PATCH v2 2/3 dt-bindings: msm: Convert LLCC bindings to YAML

In reply to Sai Prakash Ranjan

Convert LLCC bindings to DT schema format using json-schema.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
 .../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --------------
 .../bindings/arm/msm/qcom,llcc.yaml           | 54 +++++++++++++++++++
 2 files changed, 54 insertions(+), 41 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt deleted +0 -41
deleted file mode 100644
index eaee06b2d8f2..000000000000
@@ -1,41 +0,0 @@
-== Introduction==
-
-LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
-that can be shared by multiple clients. Clients here are different cores in the
-SOC, the idea is to minimize the local caches at the clients and migrate to
-common pool of memory. Cache memory is divided into partitions called slices
-which are assigned to clients. Clients can query the slice details, activate
-and deactivate them.
-
-Properties:
-- compatible:
-	Usage: required
-	Value type: <string>
-	Definition: must be "qcom,sdm845-llcc"
-
-- reg:
-	Usage: required
-	Value Type: <prop-encoded-array>
-	Definition: The first element specifies the llcc base start address and
-		    the size of the register region. The second element specifies
-		    the llcc broadcast base address and size of the register region.
-
-- reg-names:
-        Usage: required
-        Value Type: <stringlist>
-        Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
-
-- interrupts:
-	Usage: required
-	Definition: The interrupt is associated with the llcc edac device.
-			It's used for llcc cache single and double bit error detection
-			and reporting.
-
-Example:
-
-	cache-controller@1100000 {
-		compatible = "qcom,sdm845-llcc";
-		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
-		reg-names = "llcc_base", "llcc_broadcast_base";
-		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
-	};
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml new file +54 -0

54 lines not on this page · raw message

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author
#5 lore raw

PATCH v2 3/3 dt-bindings: msm: Add LLCC for SC7180

In reply to Sai Prakash Ranjan

Add LLCC compatible for SC7180 SoC.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +1 -0
index 5ac90d101807..558749065b97 100644
@@ -21,6 +21,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,sc7180-llcc
       - qcom,sdm845-llcc
 
   reg:
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
#7 lore raw
In reply to Sai Prakash Ranjan
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Thanks for the patches and thanks for the review Stephen. Series applied

Regards,
Bjorn

Quoted 22 lines

v2:
* Convert bindings to YAML and add compatible for SC7180
* Address Stephen's comments on const

Sai Prakash Ranjan (2):
dt-bindings: msm: Convert LLCC bindings to YAML
dt-bindings: msm: Add LLCC for SC7180

Vivek Gautam (1):
soc: qcom: llcc: Add configuration data for SC7180

 .../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --------------
 .../bindings/arm/msm/qcom,llcc.yaml           | 55 +++++++++++++++++++
 drivers/soc/qcom/llcc-qcom.c                  | 15 ++++-
 3 files changed, 69 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
#8 lore raw
Quoted 10 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Thanks for the patches and thanks for the review Stephen. Series applied

And they break dt_binding_check. Please fix.

Rob

author
#9 lore raw

Hi Rob,

Quoted 11 lines · Rob Herring
Quoted 9 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Quoted 4 lines
Quoted 1 line

Thanks for the patches and thanks for the review Stephen. Series applied

And they break dt_binding_check. Please fix.

I did check this and think that the error log from dt_binding_check is not valid because it says cache-level is a required property [1], but there is no such property in LLCC bindings.

[1] - http://patchwork.ozlabs.org/patch/1179800/

-Sai

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
#10 lore raw
Quoted 18 lines · Sai Prakash Ranjan

Hi Rob,

Quoted 14 lines · Rob Herring
Quoted 11 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Thanks for the patches and thanks for the review Stephen. Series applied

Quoted 6 lines
Quoted 2 lines

And they break dt_binding_check. Please fix.

I did check this and think that the error log from dt_binding_check is not valid because it says cache-level is a required property [1], but there is no such property in LLCC bindings.

Then you should point out the issue and not just submit stuff ignoring it. It has to be resolved one way or another.

If you refer to the DT spec[1], cache-level is required. The schema is just enforcing that now. It's keying off the node name of 'cache-controller'.

Rob

[1] https://github.com/devicetree-org/devicetree-specification/blob/master/source/devicenodes.rst#multi-level-and-shared-cache-nodes-cpuscpul-cache

author
#11 lore raw
Quoted 23 lines · Rob Herring
Quoted 21 lines · Sai Prakash Ranjan

Hi Rob,

Quoted 16 lines · Rob Herring
Quoted 11 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Thanks for the patches and thanks for the review Stephen. Series applied

And they break dt_binding_check. Please fix.

Quoted 7 lines
Quoted 3 lines

I did check this and think that the error log from dt_binding_check is not valid because it says cache-level is a required property [1], but there is no such property in LLCC bindings.

Then you should point out the issue and not just submit stuff ignoring it. It has to be resolved one way or another.

I did not ignore it. When I ran the dt-binding check locally, it did not error out and just passed on [1] and it was my bad that I did not check the entire build logs to see if llcc dt binding check had some warning or not. But this is the usual case where most of us don't look at the entire build logs to check if there is a warning or not. We notice if there is an immediate exit/fail in case of some warning/error. So it would be good if we fail the dt-binding check build if there is some warning/error or atleast provide some option to strict build to fail on warning, maybe there is already a flag to do this?

After submitting the patch, I noticed this build failure on patchwork.ozlabs.org and was waiting for your reply.

[1] https://paste.ubuntu.com/p/jNK8yfVkMG/

Quoted 4 lines

If you refer to the DT spec[1], cache-level is required. The schema is just enforcing that now. It's keying off the node name of 'cache-controller'.

This is not L2 or L3 cache, this is a system cache (last level cache) shared by clients other than just CPU. So I don't know how do we specify cache-level for this, let me know if you have some pointers.

-Sai

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#12 lore raw

Hello Rob,

Quoted 47 lines · Sai Prakash Ranjan
Quoted 23 lines · Rob Herring
Quoted 21 lines · Sai Prakash Ranjan

Hi Rob,

Quoted 16 lines · Rob Herring
Quoted 11 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Thanks for the patches and thanks for the review Stephen. Series applied

And they break dt_binding_check. Please fix.

Quoted 7 lines
Quoted 3 lines

I did check this and think that the error log from dt_binding_check is not valid because it says cache-level is a required property [1], but there is no such property in LLCC bindings.

Then you should point out the issue and not just submit stuff ignoring it. It has to be resolved one way or another.

I did not ignore it. When I ran the dt-binding check locally, it did not error out and just passed on [1] and it was my bad that I did not check the entire build logs to see if llcc dt binding check had some warning or not. But this is the usual case where most of us don't look at the entire build logs to check if there is a warning or not. We notice if there is an immediate exit/fail in case of some warning/error. So it would be good if we fail the dt-binding check build if there is some warning/error or atleast provide some option to strict build to fail on warning, maybe there is already a flag to do this?

After submitting the patch, I noticed this build failure on patchwork.ozlabs.org and was waiting for your reply.

[1] https://paste.ubuntu.com/p/jNK8yfVkMG/

Quoted 9 lines
Quoted 4 lines

If you refer to the DT spec[1], cache-level is required. The schema is just enforcing that now. It's keying off the node name of 'cache-controller'.

This is not L2 or L3 cache, this is a system cache (last level cache) shared by clients other than just CPU. So I don't know how do we specify cache-level for this, let me know if you have some pointers.

Any ideas on specifying the cache-level for system cache? Does dt-binding-check needs to be updated for this case?

Thanks,
Sai

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
#13 lore raw

Quoting Sai Prakash Ranjan (2019-11-13 07:00:40)

Quoted 70 lines

Hello Rob,

Quoted 60 lines · Sai Prakash Ranjan
Quoted 23 lines · Rob Herring
Quoted 21 lines · Sai Prakash Ranjan

Hi Rob,

Quoted 16 lines · Rob Herring
Quoted 11 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Thanks for the patches and thanks for the review Stephen. Series applied

And they break dt_binding_check. Please fix.

Quoted 8 lines
Quoted 4 lines

I did check this and think that the error log from dt_binding_check is
not valid because it says cache-level is a required property [1], but there is no such property in LLCC bindings.

Then you should point out the issue and not just submit stuff ignoring it. It has to be resolved one way or another.

I did not ignore it. When I ran the dt-binding check locally, it did not
error out and just passed on [1] and it was my bad that I did not check the entire build logs to see if llcc dt binding check had some warning or
not. But this is the usual case where most of us don't look at the entire
build logs to check if there is a warning or not. We notice if there is an
immediate exit/fail in case of some warning/error. So it would be good if
we fail the dt-binding check build if there is some warning/error or atleast
provide some option to strict build to fail on warning, maybe there is already
a flag to do this?

After submitting the patch, I noticed this build failure on patchwork.ozlabs.org and was waiting for your reply.

[1] https://paste.ubuntu.com/p/jNK8yfVkMG/

Quoted 4 lines

If you refer to the DT spec[1], cache-level is required. The schema is just enforcing that now. It's keying off the node name of 'cache-controller'.

Quoted 6 lines

This is not L2 or L3 cache, this is a system cache (last level cache) shared by
clients other than just CPU. So I don't know how do we specify cache-level for
this, let me know if you have some pointers.

Quoted 4 lines

Any ideas on specifying the cache-level for system cache? Does dt-binding-check
needs to be updated for this case?

I don't see how 'cache-level' fits here. Maybe the node name should be changed to 'system-cache-controller' and then the schema checker can skip it?

author
#14 lore raw
Quoted 71 lines · Stephen Boyd

Quoting Sai Prakash Ranjan (2019-11-13 07:00:40)

Quoted 70 lines

Hello Rob,

Quoted 66 lines · Sai Prakash Ranjan
Quoted 23 lines · Rob Herring
Quoted 21 lines · Sai Prakash Ranjan

Hi Rob,

Quoted 16 lines · Rob Herring
Quoted 11 lines · Bjorn Andersson
Quoted 5 lines · Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set in the llcc-qcom driver, add the same for SC7180 SoC. Also convert the existing bindings to json-schema and add the compatible for SC7180 SoC.

Thanks for the patches and thanks for the review Stephen. Series applied

And they break dt_binding_check. Please fix.

Quoted 8 lines
Quoted 4 lines

I did check this and think that the error log from dt_binding_check is
not valid because it says cache-level is a required property [1], but there is no such property in LLCC bindings.

Then you should point out the issue and not just submit stuff ignoring it. It has to be resolved one way or another.

I did not ignore it. When I ran the dt-binding check locally, it did not
error out and just passed on [1] and it was my bad that I did not check the entire build logs to see if llcc dt binding check had some warning or
not. But this is the usual case where most of us don't look at the entire
build logs to check if there is a warning or not. We notice if there is an
immediate exit/fail in case of some warning/error. So it would be good if
we fail the dt-binding check build if there is some warning/error or atleast
provide some option to strict build to fail on warning, maybe there is already
a flag to do this?

After submitting the patch, I noticed this build failure on patchwork.ozlabs.org and was waiting for your reply.

[1] https://paste.ubuntu.com/p/jNK8yfVkMG/

Quoted 4 lines

If you refer to the DT spec[1], cache-level is required. The schema is just enforcing that now. It's keying off the node name of 'cache-controller'.

This is not L2 or L3 cache, this is a system cache (last level cache) shared by
clients other than just CPU. So I don't know how do we specify cache-level for
this, let me know if you have some pointers.

Quoted 8 lines
Quoted 4 lines

Any ideas on specifying the cache-level for system cache? Does dt-binding-check
needs to be updated for this case?

I don't see how 'cache-level' fits here. Maybe the node name should be changed to 'system-cache-controller' and then the schema checker can skip it?

Sounds good and correct. I made this change and ran the dt binding check and no warning was observed.

Sent a patch - https://lore.kernel.org/lkml/[email protected]/

-Sai

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of Code Aurora Forum, hosted by The Linux Foundation