PCI: Add Intel PCIe Driver and respective dt-binding yaml file
Subsystems (6)
v11 cover PCI: Add Intel PCIe Driver and respective dt-binding yaml file
Intel PCIe is Synopsys based controller. Intel PCIe driver uses DesignWare PCIe framework for host initialization and register configurations.
Changes on v11:
Patches rebase on kernel v5.5-rc1
Dilip Kota (3):
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
PCI: dwc: intel: PCIe RC controller driver
PCI: artpec6: Configure FTS with dwc helper function
.../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++ drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec6.c | 8 +- drivers/pci/controller/dwc/pcie-designware.c | 57 +++ drivers/pci/controller/dwc/pcie-designware.h | 12 + drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++ include/uapi/linux/pci_regs.h | 1 + 8 files changed, 766 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
Signature · 1 line
2.11.0
PATCH v11 1/3 dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
Add YAML schemas for PCIe RC controller on Intel Gateway SoCs which is Synopsys DesignWare based PCIe core.
Signed-off-by Dilip Kota <[email protected]>
Signed-off-by Lorenzo Pieralisi <[email protected]>
Reviewed-by Andrew Murray <[email protected]>
Reviewed-by Rob Herring <[email protected]>
--- .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file +138 -0
@@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe RC controller on Intel Gateway SoCs + +maintainers: + - Dilip Kota <[email protected]> + +properties: + compatible: + items: + - const: intel,lgm-pcie + - const: snps,dw-pcie + + device_type: + const: pci + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Controller application registers. + + reg-names: + items: + - const: dbi + - const: config + - const: app + + ranges: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + + reset-gpios: + maxItems: 1 + + linux,pci-domain: true + + num-lanes: + maximum: 2 + description: Number of lanes to use for this port. + + '#interrupt-cells': + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + max-link-speed: + description: Specify PCI Gen for link capability. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 1, 2, 3, 4 ] + - default: 1 + + bus-range: + description: Range of bus numbers associated with this controller. + + reset-assert-ms: + description: | + Delay after asserting reset to the PCIe device. + maximum: 500 + default: 100 + +required: + - compatible + - device_type + - "#address-cells" + - "#size-cells" + - reg + - reg-names + - ranges + - resets + - clocks + - phys + - phy-names + - reset-gpios + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/intel,lgm-clk.h> + pcie10: pcie@d0e00000 { + compatible = "intel,lgm-pcie", "snps,dw-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0xd0e00000 0x1000>, + <0xd2000000 0x800000>, + <0xd0a41000 0x1000>; + reg-names = "dbi", "config", "app"; + linux,pci-domain = <0>; + max-link-speed = <4>; + bus-range = <0x00 0x08>; + interrupt-parent = <&ioapic1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &ioapic1 27 1>, + <0 0 0 2 &ioapic1 28 1>, + <0 0 0 3 &ioapic1 29 1>, + <0 0 0 4 &ioapic1 30 1>; + ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>; + resets = <&rcu0 0x50 0>; + clocks = <&cgu0 LGM_GCLK_PCIE10>; + phys = <&cb0phy0>; + phy-names = "pcie"; + reset-assert-ms = <500>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + num-lanes = <2>; + };
Signature · 1 line
2.11.0
Rob Herring
maintainerRe: [PATCH v11 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
Quoted 119 lines · Dilip Kota
Add YAML schemas for PCIe RC controller on Intel Gateway SoCs which is Synopsys DesignWare based PCIe core.
Signed-off-by Dilip Kota <[email protected]>Signed-off-by Lorenzo Pieralisi <[email protected]>Reviewed-by Andrew Murray <[email protected]>Reviewed-by Rob Herring <[email protected]>--- .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yamlDocumentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file +100
-0@@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe RC controller on Intel Gateway SoCs + +maintainers: + - Dilip Kota <[email protected]> + +properties: + compatible: + items: + - const: intel,lgm-pcie + - const: snps,dw-pcie + + device_type: + const: pci + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Controller application registers. + + reg-names: + items: + - const: dbi + - const: config + - const: app + + ranges: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + + reset-gpios: + maxItems: 1 + + linux,pci-domain: true + + num-lanes: + maximum: 2 + description: Number of lanes to use for this port. + + '#interrupt-cells': + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + max-link-speed: + description: Specify PCI Gen for link capability. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 1, 2, 3, 4 ] + - default: 1 + + bus-range: + description: Range of bus numbers associated with this controller. + + reset-assert-ms: + description: | + Delay after asserting reset to the PCIe device. + maximum: 500 + default: 100 + +required: + - compatible + - device_type + - "#address-cells" + - "#size-cells" + - reg + - reg-names + - ranges + - resets + - clocks + - phys + - phy-names + - reset-gpios
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml line 110
Quoted 10 lines
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file +10
-0+ - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/intel,lgm-clk.h>
I guess this is applied now as the example fails to build in linux-next as this header is missing.
At this point I'd settle for just 'make dt_binding_check' passing on linux-next even though it should pass on maintainer trees too. However, it doesn't appear the clock driver with this header is close to being merged. The binding was sent on Aug 28 and not to the DT list so I hadn't seen it. Given that, I'd suggest a follow-up patch to remove the header dependency here. Just change LGM_GCLK_PCIE10 to the value.
Quoted 31 lines
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file +28
-1+ pcie10: pcie@d0e00000 { + compatible = "intel,lgm-pcie", "snps,dw-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0xd0e00000 0x1000>, + <0xd2000000 0x800000>, + <0xd0a41000 0x1000>; + reg-names = "dbi", "config", "app"; + linux,pci-domain = <0>; + max-link-speed = <4>; + bus-range = <0x00 0x08>; + interrupt-parent = <&ioapic1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &ioapic1 27 1>, + <0 0 0 2 &ioapic1 28 1>, + <0 0 0 3 &ioapic1 29 1>, + <0 0 0 4 &ioapic1 30 1>; + ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>; + resets = <&rcu0 0x50 0>; + clocks = <&cgu0 LGM_GCLK_PCIE10>; + phys = <&cb0phy0>; + phy-names = "pcie"; + reset-assert-ms = <500>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + num-lanes = <2>; + }; --2.11.0
Re: [PATCH v11 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
Quoted 132 lines · Rob Herring
Quoted 118 lines · Dilip Kota
Add YAML schemas for PCIe RC controller on Intel Gateway SoCs which is Synopsys DesignWare based PCIe core.
Signed-off-by Dilip Kota <[email protected]>Signed-off-by Lorenzo Pieralisi <[email protected]>Reviewed-by Andrew Murray <[email protected]>Reviewed-by Rob Herring <[email protected]>--- .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+)create mode 100644
Documentation/devicetree/bindings/pci/intel-gw-pcie.yamlDocumentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file +100
-0@@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe RC controller on Intel Gateway SoCs + +maintainers: + - Dilip Kota <[email protected]> + +properties: + compatible: + items: + - const: intel,lgm-pcie + - const: snps,dw-pcie + + device_type: + const: pci + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Controller control and status registers. + - description: PCIe configuration registers. + - description: Controller application registers. + + reg-names: + items: + - const: dbi + - const: config + - const: app + + ranges: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + + reset-gpios: + maxItems: 1 + + linux,pci-domain: true + + num-lanes: + maximum: 2 + description: Number of lanes to use for this port. + + '#interrupt-cells': + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + max-link-speed: + description: Specify PCI Gen for link capability. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 1, 2, 3, 4 ] + - default: 1 + + bus-range: + description: Range of bus numbers associated with this controller. + + reset-assert-ms: + description: | + Delay after asserting reset to the PCIe device. + maximum: 500 + default: 100 + +required: + - compatible + - device_type + - "#address-cells" + - "#size-cells" + - reg + - reg-names + - ranges + - resets + - clocks + - phys + - phy-names + - reset-gpiosDocumentation/devicetree/bindings/pci/intel-gw-pcie.yaml line 110
Quoted 10 lines
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file +10
-0+ - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/intel,lgm-clk.h>I guess this is applied now as the example fails to build in linux-next as this header is missing.
Quoted 7 lines
At this point I'd settle for just 'make
dt_binding_check' passing on linux-next even though it should pass on maintainer trees too. However, it doesn't appear the clock driver with this header is close to being merged. The binding was sent on Aug 28 and not to the DT list so I hadn't seen it. Given that, I'd suggest a follow-up patch to remove the header dependency here. Just changeLGM_GCLK_PCIE10to the value.
Sure, i will send the patch.
Regards,
Dilip
Quoted 31 lines
Quoted 31 lines
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml new file +28
-1+ pcie10: pcie@d0e00000 { + compatible = "intel,lgm-pcie", "snps,dw-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0xd0e00000 0x1000>, + <0xd2000000 0x800000>, + <0xd0a41000 0x1000>; + reg-names = "dbi", "config", "app"; + linux,pci-domain = <0>; + max-link-speed = <4>; + bus-range = <0x00 0x08>; + interrupt-parent = <&ioapic1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &ioapic1 27 1>, + <0 0 0 2 &ioapic1 28 1>, + <0 0 0 3 &ioapic1 29 1>, + <0 0 0 4 &ioapic1 30 1>; + ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>; + resets = <&rcu0 0x50 0>; + clocks = <&cgu0 LGM_GCLK_PCIE10>; + phys = <&cb0phy0>; + phy-names = "pcie"; + reset-assert-ms = <500>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + num-lanes = <2>; + }; --2.11.0
PATCH v11 2/3 PCI: dwc: intel: PCIe RC controller driver
In reply to Dilip KotaAdd support to PCIe RC controller on Intel Gateway SoCs. PCIe controller is based of Synopsys DesignWare PCIe core.
Intel PCIe driver requires Upconfigure support, Fast Training Sequence and link speed configurations. So adding the respective helper functions in the PCIe DesignWare framework.
It also programs hardware autonomous speed during speed configuration so defining it in pci_regs.h.
Also, mark Intel PCIe driver depends on MSI IRQ Domain as Synopsys DesignWare framework depends on the PCI_MSI_IRQ_DOMAIN.
Signed-off-by Dilip Kota <[email protected]>
Signed-off-by Lorenzo Pieralisi <[email protected]>
Reviewed-by Andrew Murray <[email protected]>
Reviewed-by Andy Shevchenko <[email protected]>
Acked-by Gustavo Pimentel <[email protected]>
--- drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-designware.c | 57 +++ drivers/pci/controller/dwc/pcie-designware.h | 12 + drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++++++++ include/uapi/linux/pci_regs.h | 1 + 6 files changed, 627 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
drivers/pci/controller/dwc/Kconfig +11 -0
@@ -209,6 +209,17 @@ config PCIE_ARTPEC6_EP Enables support for the PCIe controller in the ARTPEC-6 SoC to work in endpoint mode. This uses the DesignWare core. +config PCIE_INTEL_GW + bool "Intel Gateway PCIe host controller support" + depends on OF && (X86 || COMPILE_TEST) + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say 'Y' here to enable PCIe Host controller support on Intel + Gateway SoCs. + The PCIe controller uses the DesignWare core plus Intel-specific + hardware wrappers. + config PCIE_KIRIN depends on OF && (ARM64 || COMPILE_TEST) bool "HiSilicon Kirin series SoCs PCIe controllers"
drivers/pci/controller/dwc/Makefile +1 -0
@@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o +obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o obj-$(CONFIG_PCI_MESON) += pci-meson.o
drivers/pci/controller/dwc/pcie-designware.c +57 -0
69 lines not on this page · raw message
drivers/pci/controller/dwc/pcie-designware.h +12 -0
@@ -30,7 +30,12 @@#define LINK_WAIT_IATU 9/* Synopsys-specific PCIe configuration registers */ +#define PCIE_PORT_AFR 0x70C +#define PORT_AFR_N_FTS_MASK GENMASK(15, 8) +#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16) +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_DLL_LINK_EN BIT(5)#define PORT_LINK_MODE_MASK GENMASK(21, 16)#define PORT_LINK_MODE (n) FIELD_PREP(PORT_LINK_MODE_MASK, n)#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
@@ -46,6 +51,7 @@#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)#define PORT_LOGIC_SPEED_CHANGE BIT(17)#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)#define PORT_LOGIC_LINK_WIDTH (n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
@@ -60,6 +66,9 @@#define PCIE_MSI_INTR0_MASK 0x82C#define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 +#define PORT_MLTI_UPCFG_SUPPORT BIT(7) +#define PCIE_ATU_VIEWPORT 0x900#define PCIE_ATU_REGION_INBOUND BIT(31)#define PCIE_ATU_REGION_OUTBOUND 0
@@ -273,6 +282,9 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);u32 dw_pcie_read_atu (struct dw_pcie *pci,u32 reg,size_t size);void dw_pcie_write_atu (struct dw_pcie *pci,u32 reg,size_t size,u32 val);int dw_pcie_link_up (struct dw_pcie *pci); +void dw_pcie_upconfig_setup (struct dw_pcie *pci); +void dw_pcie_link_set_max_speed (struct dw_pcie *pci,u32 link_gen); +void dw_pcie_link_set_n_fts (struct dw_pcie *pci,u32 n_fts);int dw_pcie_wait_for_link (struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr,
drivers/pci/controller/dwc/pcie-intel-gw.c new file +545 -0
545 lines not on this page · raw message
include/uapi/linux/pci_regs.h +1 -0
@@ -676,6 +676,7 @@#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005/* Supported Speed 32GT/s */ #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010/* Enter Compliance */ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380/* Transmit Margin */ +#define PCI_EXP_LNKCTL2_HASD 0x0020/* HW Autonomous Speed Disable */ #define PCI_EXP_LNKSTA2 50/* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52/* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52/* Slot Capabilities 2 */
Signature · 1 line
2.11.0
PATCH v11 3/3 PCI: artpec6: Configure FTS with dwc helper function
In reply to Dilip KotaUse DesignWare helper functions to configure Fast Training Sequence. Drop the respective code in the driver.
Signed-off-by Dilip Kota <[email protected]>
Signed-off-by Lorenzo Pieralisi <[email protected]>
Reviewed-by Andrew Murray <[email protected]>
--- drivers/pci/controller/dwc/pcie-artpec6.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)
drivers/pci/controller/dwc/pcie-artpec6.c +1 -7
@@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[];#define ACK_N_FTS_MASK GENMASK(15, 8)#define ACK_N_FTS (x) (((x) << 8) & ACK_N_FTS_MASK) -#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0) -#define FAST_TRAINING_SEQ (x) (((x) << 0) & FAST_TRAINING_SEQ_MASK) -/* ARTPEC-6 specific registers */ #define PCIECFG 0x18#define PCIECFG_DBG_OEN BIT(24)
@@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)* Set the Number of Fast Training Sequences that the core * advertises as its N_FTS during Gen2 or Gen3 link training. */ - val =dw_pcie_readl_dbi (pci,PCIE_LINK_WIDTH_SPEED_CONTROL ); - val &= ~FAST_TRAINING_SEQ_MASK ; - val |=FAST_TRAINING_SEQ (180 ); -dw_pcie_writel_dbi (pci,PCIE_LINK_WIDTH_SPEED_CONTROL , val); +dw_pcie_link_set_n_fts (pci,180 ); }static void artpec6_pcie_assert_core_reset (struct artpec6_pcie *artpec6_pcie)
Signature · 1 line
2.11.0
Quoted 6 lines · Dilip Kota
Intel PCIe is Synopsys based controller. Intel PCIe driver uses DesignWare PCIe framework for host initialization and register configurations.
Changes on v11:
Patches rebase on kernel v5.5-rc1
Thanks for this. Looks OK to me.
Andrew Murray
Quoted 21 lines
Dilip Kota (3):
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
PCI: dwc: intel: PCIe RC controller driver
PCI: artpec6: Configure FTS with dwc helper function.../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++ drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec6.c | 8 +- drivers/pci/controller/dwc/pcie-designware.c | 57 +++ drivers/pci/controller/dwc/pcie-designware.h | 12 + drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++ include/uapi/linux/pci_regs.h | 1 + 8 files changed, 766 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.cSignature · 1 line
2.11.0
Lorenzo Pieralisi
AppliedQuoted 12 lines · Dilip Kota
Intel PCIe is Synopsys based controller. Intel PCIe driver uses DesignWare PCIe framework for host initialization and register configurations.
Changes on v11:
Patches rebase on kernel v5.5-rc1Dilip Kota (3):
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
PCI: dwc: intel: PCIe RC controller driver
PCI: artpec6: Configure FTS with dwc helper function
Quoted 11 lines
.../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++ drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec6.c | 8 +- drivers/pci/controller/dwc/pcie-designware.c | 57 +++ drivers/pci/controller/dwc/pcie-designware.h | 12 + drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++ include/uapi/linux/pci_regs.h | 1 + 8 files changed, 766 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
Applied to pci/dwc, thanks.
Lorenzo