drm/tidss: New driver for TI Keystone platform Display SubSystem
Subsystems (5)
v4 cover drm/tidss: New driver for TI Keystone platform Display SubSystem
Changes sice v3:
- Add descriptions some yaml binding properites
- Remove redundant minItems directives from yaml bindings
- Remove ports node from ti,k2g-dss yaml binding
- no change to MAINTAINERS or to the driver code
Changes since v2:
- Add version history to commit messages
- Fix yaml bindings now that got dt_binding_check dtbs_check working propery
- Move tidss entry in MAINTAINERS after omapdrm and add "T: git
git://anongit.freedesktop.org/drm/drm-misc"
- no change to driver code
Changes since the first version of the patch series [2]:
- "drm/tidss: New driver for TI Keystone platform Display SubSystem"
- rebased on top of drm-next-2019-11-27
- sort all include lines in all files
- remove all include <drm/drmP.h>
- remove select "select VIDEOMODE_HELPERS"
- call dispc_vp_setup() later in tidss_crtc_atomic_flush() (there is no to call it in new modeset case as it is also called in vp_enable())
- change probe sequence and drm_device allocation (follow example in drm_drv.c)
- use __maybe_unused instead of #ifdef for pm functions
- remove "struct drm_fbdev_cma *fbdev;" from driver data
- check panel connector type before connecting it
- No change to binding or MAINTAINERS patches
There was couple of attempts upstream an earlier version of this driver about a year ago [1]. Back then I needed to stop my efforts to implement support for next Keystone DSS version, so now the driver supports three different Keystone DSS version on three different SoCs.
I am starting the patch series versioning from the beginning because it has been over a year since the previous patch set and the structure of the driver has evolved quite a bit. However, all the earlier comments should be addressed in this series.
[1] https://patchwork.freedesktop.org/series/44947/
[2] https://lists.freedesktop.org/archives/dri-devel/2019-November/246542.html
Jyri Sarha (5):
dt-bindings: display: ti,k2g-dss: Add dt-schema yaml binding
dt-bindings: display: ti,am65x-dss: Add dt-schema yaml binding
dt-bindings: display: ti,j721e-dss: Add dt-schema yaml binding drm/tidss: New driver for TI Keystone platform Display SubSystem
MAINTAINERS: add entry for tidss
.../bindings/display/ti/ti,am65x-dss.yaml | 154 + .../bindings/display/ti/ti,j721e-dss.yaml | 209 ++ .../bindings/display/ti/ti,k2g-dss.yaml | 114 + MAINTAINERS | 11 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/tidss/Kconfig | 14 + drivers/gpu/drm/tidss/Makefile | 12 + drivers/gpu/drm/tidss/tidss_crtc.c | 376 +++ drivers/gpu/drm/tidss/tidss_crtc.h | 46 + drivers/gpu/drm/tidss/tidss_dispc.c | 2643 +++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 132 + drivers/gpu/drm/tidss/tidss_dispc_regs.h | 243 ++ drivers/gpu/drm/tidss/tidss_drv.c | 285 ++ drivers/gpu/drm/tidss/tidss_drv.h | 40 + drivers/gpu/drm/tidss/tidss_encoder.c | 88 + drivers/gpu/drm/tidss/tidss_encoder.h | 17 + drivers/gpu/drm/tidss/tidss_irq.c | 185 ++ drivers/gpu/drm/tidss/tidss_irq.h | 72 + drivers/gpu/drm/tidss/tidss_kms.c | 248 ++ drivers/gpu/drm/tidss/tidss_kms.h | 15 + drivers/gpu/drm/tidss/tidss_plane.c | 217 ++ drivers/gpu/drm/tidss/tidss_plane.h | 25 + drivers/gpu/drm/tidss/tidss_scale_coefs.c | 202 ++ drivers/gpu/drm/tidss/tidss_scale_coefs.h | 22 + 25 files changed, 5373 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml create mode 100644 Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml create mode 100644 Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml create mode 100644 drivers/gpu/drm/tidss/Kconfig create mode 100644 drivers/gpu/drm/tidss/Makefile create mode 100644 drivers/gpu/drm/tidss/tidss_crtc.c create mode 100644 drivers/gpu/drm/tidss/tidss_crtc.h create mode 100644 drivers/gpu/drm/tidss/tidss_dispc.c create mode 100644 drivers/gpu/drm/tidss/tidss_dispc.h create mode 100644 drivers/gpu/drm/tidss/tidss_dispc_regs.h create mode 100644 drivers/gpu/drm/tidss/tidss_drv.c create mode 100644 drivers/gpu/drm/tidss/tidss_drv.h create mode 100644 drivers/gpu/drm/tidss/tidss_encoder.c create mode 100644 drivers/gpu/drm/tidss/tidss_encoder.h create mode 100644 drivers/gpu/drm/tidss/tidss_irq.c create mode 100644 drivers/gpu/drm/tidss/tidss_irq.h create mode 100644 drivers/gpu/drm/tidss/tidss_kms.c create mode 100644 drivers/gpu/drm/tidss/tidss_kms.h create mode 100644 drivers/gpu/drm/tidss/tidss_plane.c create mode 100644 drivers/gpu/drm/tidss/tidss_plane.h create mode 100644 drivers/gpu/drm/tidss/tidss_scale_coefs.c create mode 100644 drivers/gpu/drm/tidss/tidss_scale_coefs.h
Signature · 6 lines
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 1/5 dt-bindings: display: ti, k2g-dss: Add dt-schema yaml binding
Add dt-schema yaml bindig for K2G DSS, an ultra-light version of TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - Add ports node
- Add includes to dts example
- reindent dts example
v4: - Add descriptions to reg and clocks properties
- Remove minItems when its value is the same as maxItems value
- Remove ports node
--- .../bindings/display/ti/ti,k2g-dss.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml
Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml new file +114 -0
@@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments K2G Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The K2G DSS is an ultra-light version of TI Keystone Display + SubSystem. It has only one output port and video plane. The + output is DPI. + +properties: + compatible: + const: ti,k2g-dss + + reg: + maxItems: 5 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + cfg DSSUL_0_CFG DSS top level + common DISPC_COMMON DISPC common + vid1 DISPC_VID1 VID1 video plane + ovr1 DISPC_OVR1 OVR1 overlay manager for vp1 + vp1 DISPC_VP1 VP1 video port 1 + + reg-names: + items: + - const: cfg + - const: common + - const: vid1 + - const: ovr1 + - const: vp1 + + clocks: + maxItems: 2 + description: + phandles to clock nodes for DSS functional clock (fck) and video + port 1 pixel clock (vp1). + + clock-names: + items: + - const: fck + - const: vp1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + description: phandle to the associated power domain + + port: + type: object + description: + Port as described in Documentation/devictree/bindings/graph.txt. + The DSS DPI output port node + + max-memory-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input memory (from main memory to dispc) bandwidth limit in + bytes per second + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + dss: dss@02540000 { + compatible = "ti,k2g-dss"; + reg = <0x02540000 0x400>, + <0x02550000 0x1000>, + <0x02557000 0x1000>, + <0x0255a800 0x100>, + <0x0255ac00 0x100>; + reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; + clocks = <&k2g_clks 0x2 0>, + <&k2g_clks 0x2 1>; + clock-names = "fck", "vp1"; + interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; + + power-domains = <&k2g_pds 0x2>; + + max-memory-bandwidth = <230000000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; + }; + };
Signature · 1 line
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
PATCH v4 2/5 dt-bindings: display: ti, am65x-dss: Add dt-schema yaml binding
In reply to Jyri SarhaAdd dt-schema yaml bindig for AM65x DSS, AM65x version TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - Add ports node
- use allOf in ti,am65x-oldi-io-ctrl to add both $ref and maxItems
- Add includes to dts example
- reindent dts example
v4: - Add descriptions to reg and clocks properties
- Remove minItems when its value is the same as maxItems value
--- .../bindings/display/ti/ti,am65x-dss.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml new file +154 -0
@@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments AM65x Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The AM65x TI Keystone Display SubSystem with two output ports and + two video planes. The first video port supports OLDI and the second + supports DPI format. The fist plane is full video plane with all + features and the second is a "lite plane" without scaling support. + +properties: + compatible: + const: ti,am65x-dss + + reg: + maxItems: 7 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common DSS0_COMMON DSS common register area + vidl1 DSS0_VIDL1 VIDL1 light video plane + vid DSS0_VID VID video plane + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + + reg-names: + items: + - const: common + - const: vidl1 + - const: vid + - const: ovr1 + - const: ovr2 + - const: vp1 + - const: vp2 + + clocks: + maxItems: 3 + description: + phandles to clock nodes for DSS functional clock (fck) and video + port 1 and 2 pixel clocks (vp1, vp2). + + clock-names: + items: + - const: fck + - const: vp1 + - const: vp2 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + description: phandle to the associated power domain + + ports: + type: object + description: + Ports as described in Documentation/devictree/bindings/graph.txt + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: + The DSS OLDI output port node form video port 1 + + port@1: + type: object + description: + The DSS DPI output port node from video port 2 + + required: + - "#address-cells" + - "#size-cells" + + ti,am65x-oldi-io-ctrl: + allOf: + - $ref: "/schemas/types.yaml#/definitions/phandle-array" + - maxItems: 1 + description: + phandle to syscon device node mapping OLDI IO_CTRL registers. + The mapped range should point to OLDI_DAT0_IO_CTRL, map it and + following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL, + and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI + interface to work. + + max-memory-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input memory (from main memory to dispc) bandwidth limit in + bytes per second + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + dss: dss@04a00000 { + compatible = "ti,am65x-dss"; + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ + <0x0 0x04a06000 0x0 0x1000>, /* vid */ + <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ + <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ + <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ + <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 67 1>, + <&k3_clks 216 1>, + <&k3_clks 67 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + }; + };
Signature · 6 lines
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 3/5 dt-bindings: display: ti, j721e-dss: Add dt-schema yaml binding
In reply to Jyri SarhaAdd dt-schema yaml bindig for J721E DSS, J721E version TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - reg-names: "wp" -> "wb"
- Add ports node
- Add includes to dts example
- reindent dts example
v4: - Add descriptions to reg, clocks, and interrups properties
- Remove minItems when its value is the same as maxItems value
--- .../bindings/display/ti/ti,j721e-dss.yaml | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +209 -0
@@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments J721E Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The J721E TI Keystone Display SubSystem with four output ports and + four video planes. There is two full video planes and two "lite + planes" without scaling support. The video ports can be connected to + the SoC's DPI pins or to integrated display bridges on the SoC. + +properties: + compatible: + const: ti,j721e-dss + + reg: + maxItems: 17 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common_m DSS0_DISPC_0_COMMON_M DSS Master common register area + common_s0 DSS0_DISPC_0_COMMON_SO DSS Shared common register area 0 + common_s1 DSS0_DISPC_0_COMMON_S1 DSS Shared common register area 1 + common_s2 DSS0_DISPC_0_COMMON_S2 DSS Shared common register area 2 + vidl1 DSS0_VIDL1 VIDL1 light video plane 1 + vidl2 DSS0_VIDL2 VIDL2 light video plane 2 + vid1 DSS0_VID1 VID1 video plane 1 + vid2 DSS0_VID2 VID1 video plane 2 + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + ovr3 DSS0_OVR3 OVR1 overlay manager for vp3 + ovr4 DSS0_OVR4 OVR2 overlay manager for vp4 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + vp3 DSS0_VP3 VP1 video port 3 + vp4 DSS0_VP4 VP1 video port 4 + wp DSS0_WB Write Back registers + + reg-names: + items: + - const: common_m + - const: common_s0 + - const: common_s1 + - const: common_s2 + - const: vidl1 + - const: vidl2 + - const: vid1 + - const: vid2 + - const: ovr1 + - const: ovr2 + - const: ovr3 + - const: ovr4 + - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4 + - const: wb + + clocks: + maxItems: 5 + description: + phandles to clock nodes for DSS functional clock (fck) and video + port 1, 2, 3 and 4 pixel clocks (vp1, vp2, vp3, vp4). + + clock-names: + items: + - const: fck + - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4 + + interrupts: + maxItems: 4 + description: + Interrupt descriptions for common irq registers in common_m, + common_m0, common_m1, and common_m2, sections. + + interrupt-names: + items: + - const: common_m + - const: common_s0 + - const: common_s1 + - const: common_s2 + + power-domains: + maxItems: 1 + description: phandle to the associated power domain + + ports: + type: object + description: + Ports as described in Documentation/devictree/bindings/graph.txt + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: + The output port node form video port 1 + + port@1: + type: object + description: + The output port node from video port 2 + + port@2: + type: object + description: + The output port node from video port 3 + + port@3: + type: object + description: + The output port node from video port 4 + + required: + - "#address-cells" + - "#size-cells" + + max-memory-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input memory (from main memory to dispc) bandwidth limit in + bytes per second + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + dss: dss@04a00000 { + compatible = "ti,j721e-dss"; + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks = <&k3_clks 152 0>, + <&k3_clks 152 1>, + <&k3_clks 152 4>, + <&k3_clks 152 9>, + <&k3_clks 152 13>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + dpi_out_0: endpoint { + remote-endpoint = <&dp_bridge_input>; + }; + }; + }; + };
Signature · 1 line
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Re: [PATCH v4 3/5] dt-bindings: display: ti, j721e-dss: Add dt-schema yaml binding
Hi,
Quoted 63 lines · Jyri Sarha
Add dt-schema yaml bindig for J721E DSS, J721E version TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - reg-names: "wp" -> "wb"
- Add ports node
- Add includes to dts example
- reindent dts examplev4: - Add descriptions to reg, clocks, and interrups properties
- Remove minItems when its value is the same as maxItems valueSigned-off-by Jyri Sarha <[email protected]>--- .../bindings/display/ti/ti,j721e-dss.yaml | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yamlDocumentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +36
-0@@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments J721E Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The J721E TI Keystone Display SubSystem with four output ports and + four video planes. There is two full video planes and two "lite + planes" without scaling support. The video ports can be connected to + the SoC's DPI pins or to integrated display bridges on the SoC. + +properties: + compatible: + const: ti,j721e-dss + + reg: + maxItems: 17 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common_m DSS0_DISPC_0_COMMON_M DSS Master common register area + common_s0 DSS0_DISPC_0_COMMON_SO DSS Shared common register area 0 + common_s1 DSS0_DISPC_0_COMMON_S1 DSS Shared common register area 1 + common_s2 DSS0_DISPC_0_COMMON_S2 DSS Shared common register area 2 + vidl1 DSS0_VIDL1 VIDL1 light video plane 1 + vidl2 DSS0_VIDL2 VIDL2 light video plane 2 + vid1 DSS0_VID1 VID1 video plane 1
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 46
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ vid2 DSS0_VID2 VID1 video plane 2 + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + ovr3 DSS0_OVR3 OVR1 overlay manager for vp3 + ovr4 DSS0_OVR4 OVR2 overlay manager for vp4 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + vp3 DSS0_VP3 VP1 video port 3 + vp4 DSS0_VP4 VP1 video port 4 + wp DSS0_WB Write Back registers
I guess it applies to all your schemas in that patch series, but you could just do something like
reg:
items:
- description: DSS Master common register area
- description: DSS Shared common register area 0
- description: DSS Shared common register area 1
...
That way, you wouldn't have to worry about the maxItems, and you end up doing pretty much that already in the description
Quoted 29 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +29
-0+ reg-names: + items: + - const: common_m + - const: common_s0 + - const: common_s1 + - const: common_s2 + - const: vidl1 + - const: vidl2 + - const: vid1 + - const: vid2 + - const: ovr1 + - const: ovr2 + - const: ovr3 + - const: ovr4 + - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4 + - const: wb + + clocks: + maxItems: 5 + description: + phandles to clock nodes for DSS functional clock (fck) and video + port 1, 2, 3 and 4 pixel clocks (vp1, vp2, vp3, vp4). + + clock-names: + items: + - const: fck
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 86
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4 + + interrupts: + maxItems: 4 + description: + Interrupt descriptions for common irq registers in common_m, + common_m0, common_m1, and common_m2, sections.
Same story here, but the names don't match interrupt-names. I guess describing what those interrupts actually are would be great: you just define how the driver calls them, but not what they are actually doing or representing.
I'm guessing that would end up in something like that:
interrupts:
items:
- description: DSS Master interrupt
- description: DSS Shared 0 interrupt
- description: DSS Shared 1 interrupt
- description: DSS Shared 2 interrupt
Maxime
Re: [PATCH v4 3/5] dt-bindings: display: ti, j721e-dss: Add dt-schema yaml binding
Quoted 80 lines · Maxime Ripard
Hi,
Quoted 63 lines · Jyri Sarha
Add dt-schema yaml bindig for J721E DSS, J721E version TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - reg-names: "wp" -> "wb"
- Add ports node
- Add includes to dts example
- reindent dts examplev4: - Add descriptions to reg, clocks, and interrups properties
- Remove minItems when its value is the same as maxItems valueSigned-off-by Jyri Sarha <[email protected]>--- .../bindings/display/ti/ti,j721e-dss.yaml | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yamlDocumentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +36
-0@@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments J721E Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The J721E TI Keystone Display SubSystem with four output ports and + four video planes. There is two full video planes and two "lite + planes" without scaling support. The video ports can be connected to + the SoC's DPI pins or to integrated display bridges on the SoC. + +properties: + compatible: + const: ti,j721e-dss + + reg: + maxItems: 17 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common_m DSS0_DISPC_0_COMMON_M DSS Master common register area + common_s0 DSS0_DISPC_0_COMMON_SO DSS Shared common register area 0 + common_s1 DSS0_DISPC_0_COMMON_S1 DSS Shared common register area 1 + common_s2 DSS0_DISPC_0_COMMON_S2 DSS Shared common register area 2 + vidl1 DSS0_VIDL1 VIDL1 light video plane 1 + vidl2 DSS0_VIDL2 VIDL2 light video plane 2 + vid1 DSS0_VID1 VID1 video plane 1Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 46
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ vid2 DSS0_VID2 VID1 video plane 2 + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + ovr3 DSS0_OVR3 OVR1 overlay manager for vp3 + ovr4 DSS0_OVR4 OVR2 overlay manager for vp4 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + vp3 DSS0_VP3 VP1 video port 3 + vp4 DSS0_VP4 VP1 video port 4 + wp DSS0_WB Write Back registersI guess it applies to all your schemas in that patch series, but you could just do something like
Quoted 6 lines
reg:
items:
- description: DSS Master common register area
- description: DSS Shared common register area 0
- description: DSS Shared common register area 1
Ok, thanks. I was not sure if you can do that (still a newbie with yaml). What do you think about Peter Ujfalusi's suggestion of putting the descriptions to reg-names (and clock-names and interrupt-names)? e.g. something like this:
reg-names:
items:
- const: common_m
- description: DSS Master common register area
- const: common_s0
- description: DSS Master common register area
...
Or is that even allowed?
Quoted 61 lines
...
That way, you wouldn't have to worry about the maxItems, and you end up doing pretty much that already in the description
Quoted 29 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +29
-0+ reg-names: + items: + - const: common_m + - const: common_s0 + - const: common_s1 + - const: common_s2 + - const: vidl1 + - const: vidl2 + - const: vid1 + - const: vid2 + - const: ovr1 + - const: ovr2 + - const: ovr3 + - const: ovr4 + - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4 + - const: wb + + clocks: + maxItems: 5 + description: + phandles to clock nodes for DSS functional clock (fck) and video + port 1, 2, 3 and 4 pixel clocks (vp1, vp2, vp3, vp4). + + clock-names: + items: + - const: fckDocumentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 86
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4 + + interrupts: + maxItems: 4 + description: + Interrupt descriptions for common irq registers in common_m, + common_m0, common_m1, and common_m2, sections.Same story here, but the names don't match interrupt-names. I guess describing what those interrupts actually are would be great: you just define how the driver calls them, but not what they are actually doing or representing.
I'm guessing that would end up in something like that:
interrupts:
items:
- description: DSS Master interrupt
- description: DSS Shared 0 interrupt
- description: DSS Shared 1 interrupt
- description: DSS Shared 2 interruptMaxime
Signature · 2 lines
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_______________________________________________
dri-devel mailing list
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Re: [PATCH v4 3/5] dt-bindings: display: ti, j721e-dss: Add dt-schema yaml binding
Quoted 99 lines · Jyri Sarha
Quoted 79 lines · Maxime Ripard
Hi,
Quoted 63 lines · Jyri Sarha
Add dt-schema yaml bindig for J721E DSS, J721E version TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - reg-names: "wp" -> "wb"
- Add ports node
- Add includes to dts example
- reindent dts examplev4: - Add descriptions to reg, clocks, and interrups properties
- Remove minItems when its value is the same as maxItems valueSigned-off-by Jyri Sarha <[email protected]>--- .../bindings/display/ti/ti,j721e-dss.yaml | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yamlDocumentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +36
-0@@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments J721E Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The J721E TI Keystone Display SubSystem with four output ports and + four video planes. There is two full video planes and two "lite + planes" without scaling support. The video ports can be connected to + the SoC's DPI pins or to integrated display bridges on the SoC. + +properties: + compatible: + const: ti,j721e-dss + + reg: + maxItems: 17 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common_m DSS0_DISPC_0_COMMON_M DSS Master common register area + common_s0 DSS0_DISPC_0_COMMON_SO DSS Shared common register area 0 + common_s1 DSS0_DISPC_0_COMMON_S1 DSS Shared common register area 1 + common_s2 DSS0_DISPC_0_COMMON_S2 DSS Shared common register area 2 + vidl1 DSS0_VIDL1 VIDL1 light video plane 1 + vidl2 DSS0_VIDL2 VIDL2 light video plane 2 + vid1 DSS0_VID1 VID1 video plane 1Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 46
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ vid2 DSS0_VID2 VID1 video plane 2 + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + ovr3 DSS0_OVR3 OVR1 overlay manager for vp3 + ovr4 DSS0_OVR4 OVR2 overlay manager for vp4 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + vp3 DSS0_VP3 VP1 video port 3 + vp4 DSS0_VP4 VP1 video port 4 + wp DSS0_WB Write Back registersI guess it applies to all your schemas in that patch series, but you could just do something like
Quoted 6 lines
reg:
items:
- description: DSS Master common register area
- description: DSS Shared common register area 0
- description: DSS Shared common register area 1Ok, thanks. I was not sure if you can do that (still a newbie with yaml). What do you think about Peter Ujfalusi's suggestion of putting the descriptions to reg-names (and clock-names and interrupt-names)? e.g. something like this:
reg-names:
items:
- const:common_m
- description: DSS Master common register area
- const:common_s0
- description: DSS Master common register area
...
Quoted 2 lines
Or is that even allowed?
Hmmm, it looks like make dt_binding_check does not like that. I guess I go with your suggestion, but with reg-name reference in the description.
Best regards,
Jyri
Signature · 6 lines
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 3/5] dt-bindings: display: ti, j721e-dss: Add dt-schema yaml binding
In reply to Jyri SarhaHi,
Quoted 91 lines · Jyri Sarha
Quoted 78 lines · Maxime Ripard
Quoted 63 lines · Jyri Sarha
Add dt-schema yaml bindig for J721E DSS, J721E version TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - reg-names: "wp" -> "wb"
- Add ports node
- Add includes to dts example
- reindent dts examplev4: - Add descriptions to reg, clocks, and interrups properties
- Remove minItems when its value is the same as maxItems valueSigned-off-by Jyri Sarha <[email protected]>--- .../bindings/display/ti/ti,j721e-dss.yaml | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yamlDocumentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +36
-0@@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments J721E Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The J721E TI Keystone Display SubSystem with four output ports and + four video planes. There is two full video planes and two "lite + planes" without scaling support. The video ports can be connected to + the SoC's DPI pins or to integrated display bridges on the SoC. + +properties: + compatible: + const: ti,j721e-dss + + reg: + maxItems: 17 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common_m DSS0_DISPC_0_COMMON_M DSS Master common register area + common_s0 DSS0_DISPC_0_COMMON_SO DSS Shared common register area 0 + common_s1 DSS0_DISPC_0_COMMON_S1 DSS Shared common register area 1 + common_s2 DSS0_DISPC_0_COMMON_S2 DSS Shared common register area 2 + vidl1 DSS0_VIDL1 VIDL1 light video plane 1 + vidl2 DSS0_VIDL2 VIDL2 light video plane 2 + vid1 DSS0_VID1 VID1 video plane 1Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 46
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ vid2 DSS0_VID2 VID1 video plane 2 + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + ovr3 DSS0_OVR3 OVR1 overlay manager for vp3 + ovr4 DSS0_OVR4 OVR2 overlay manager for vp4 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + vp3 DSS0_VP3 VP1 video port 3 + vp4 DSS0_VP4 VP1 video port 4 + wp DSS0_WB Write Back registersI guess it applies to all your schemas in that patch series, but you could just do something like
Quoted 6 lines
reg:
items:
- description: DSS Master common register area
- description: DSS Shared common register area 0
- description: DSS Shared common register area 1Ok, thanks. I was not sure if you can do that (still a newbie with yaml). What do you think about Peter Ujfalusi's suggestion of putting the descriptions to reg-names (and clock-names and interrupt-names)? e.g. something like this:
Quoted 6 lines
reg-names:
items:
- const:common_m
- description: DSS Master common register area
- const:common_s0
- description: DSS Master common register area
No, you can't really intertwin them like this, this would mean that you would expect twice the number of items.
You could do something like this:
reg-names:
items:
- const: common_m
description: DSS Master common register area
- const: common_s0
description: DSS Master common register area
But on a more fundamental level, the register area is stored under regs, while reg-names is just a label for that area, so having the description under reg, and the labels under reg-names makes more sense (well, to me at least :))
Maxiem
Re: [PATCH v4 3/5] dt-bindings: display: ti, j721e-dss: Add dt-schema yaml binding
In reply to Jyri SarhaHi Jyri,
Quoted 63 lines · Jyri Sarha
Add dt-schema yaml bindig for J721E DSS, J721E version TI Keystone Display SubSystem.
Version history:
v2: no change
v3: - reg-names: "wp" -> "wb"
- Add ports node
- Add includes to dts example
- reindent dts examplev4: - Add descriptions to reg, clocks, and interrups properties
- Remove minItems when its value is the same as maxItems valueSigned-off-by Jyri Sarha <[email protected]>--- .../bindings/display/ti/ti,j721e-dss.yaml | 209 ++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yamlDocumentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +36
-0@@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments J721E Display Subsystem + +maintainers: + - Jyri Sarha <[email protected]> + - Tomi Valkeinen <[email protected]> + +description: | + The J721E TI Keystone Display SubSystem with four output ports and + four video planes. There is two full video planes and two "lite + planes" without scaling support. The video ports can be connected to + the SoC's DPI pins or to integrated display bridges on the SoC. + +properties: + compatible: + const: ti,j721e-dss + + reg: + maxItems: 17 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common_m DSS0_DISPC_0_COMMON_M DSS Master common register area + common_s0 DSS0_DISPC_0_COMMON_SO DSS Shared common register area 0 + common_s1 DSS0_DISPC_0_COMMON_S1 DSS Shared common register area 1 + common_s2 DSS0_DISPC_0_COMMON_S2 DSS Shared common register area 2 + vidl1 DSS0_VIDL1 VIDL1 light video plane 1 + vidl2 DSS0_VIDL2 VIDL2 light video plane 2 + vid1 DSS0_VID1 VID1 video plane 1
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 46
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ vid2 DSS0_VID2 VID1 video plane 2 + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + ovr3 DSS0_OVR3 OVR1 overlay manager for vp3 + ovr4 DSS0_OVR4 OVR2 overlay manager for vp4 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + vp3 DSS0_VP3 VP1 video port 3 + vp4 DSS0_VP4 VP1 video port 4 + wp DSS0_WB Write Back registers
'wp' is back ;)
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ + reg-names: + items: + - const: common_m + - const: common_s0 + - const: common_s1 + - const: common_s2 + - const: vidl1 + - const: vidl2 + - const: vid1
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 66
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ - const: vid2 + - const: ovr1 + - const: ovr2 + - const: ovr3 + - const: ovr4 + - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4 + - const: wb
imho the description you put under the 'reg' would be more natural here, where you actually specifying the names of the register ranges.
Quoted 4 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +4
-0+ + clocks: + maxItems: 5 + description:
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 80
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ phandles to clock nodes for DSS functional clock (fck) and video + port 1, 2, 3 and 4 pixel clocks (vp1, vp2, vp3, vp4). + + clock-names: + items: + - const: fck + - const: vp1 + - const: vp2 + - const: vp3 + - const: vp4
Same comment, it is more natural to have the description coupled with what you are describing.
Quoted 120 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +119
-0+ + interrupts: + maxItems: 4 + description: + Interrupt descriptions for common irq registers in common_m, + common_m0, common_m1, and common_m2, sections. + + interrupt-names: + items: + - const: common_m + - const: common_s0 + - const: common_s1 + - const: common_s2 + + power-domains: + maxItems: 1 + description: phandle to the associated power domain + + ports: + type: object + description: + Ports as described in Documentation/devictree/bindings/graph.txt + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: + The output port node form video port 1 + + port@1: + type: object + description: + The output port node from video port 2 + + port@2: + type: object + description: + The output port node from video port 3 + + port@3: + type: object + description: + The output port node from video port 4 + + required: + - "#address-cells" + - "#size-cells" + + max-memory-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input memory (from main memory to dispc) bandwidth limit in + bytes per second + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + dss: dss@04a00000 { + compatible = "ti,j721e-dss"; + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks = <&k3_clks 152 0>, + <&k3_clks 152 1>, + <&k3_clks 152 4>, + <&k3_clks 152 9>, + <&k3_clks 152 13>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + ports { + #address-cells = <1>;
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml line 209
Quoted 10 lines
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml new file +10
-0+ #size-cells = <0>; + port@0 { + reg = <0>; + + dpi_out_0: endpoint { + remote-endpoint = <&dp_bridge_input>; + }; + }; + }; + };
- Péter
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PATCH v4 4/5 drm/tidss: New driver for TI Keystone platform Display SubSystem
In reply to Jyri SarhaThis patch adds a new DRM driver for Texas Instruments DSS IPs used on Texas Instruments Keystone K2G, AM65x, and J721e SoCs. The new DSS IP is a major change to the older DSS IP versions, which are supported by the omapdrm driver. While on higher level the Keystone DSS resembles the older DSS versions, the registers are completely different and the internal pipelines differ a lot.
DSS IP found on K2G is an "ultra-light" version, and has only a single plane and a single output. The Keystone 3 DSS IPs are found on AM65x and J721E SoCs. AM65x DSS has two video ports, one full video plane, and another "lite" plane without scaling support. J721E has 4 video ports, 2 video planes and 2 lite planes. AM65x DSS has also integrated OLDI (LVDS) output.
Version history:
v2: - rebased on top of drm-next-2019-11-27
- sort all include lines in all files
- remove all include <drm/drmP.h>
- remove select "select VIDEOMODE_HELPERS"
- call dispc_vp_setup() later in tidss_crtc_atomic_flush() (there is no to call it in new modeset case as it is also called in vp_enable())
- change probe sequence and drm_device allocation (follow example in drm_drv.c)
- use __maybe_unused instead of #ifdef for pm functions
- remove "struct drm_fbdev_cma *fbdev;" from driver data
- check panel connector type before connecting it
v3: no change
v4: no change
--- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/tidss/Kconfig | 14 + drivers/gpu/drm/tidss/Makefile | 12 + drivers/gpu/drm/tidss/tidss_crtc.c | 376 +++ drivers/gpu/drm/tidss/tidss_crtc.h | 46 + drivers/gpu/drm/tidss/tidss_dispc.c | 2643 +++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 132 + drivers/gpu/drm/tidss/tidss_dispc_regs.h | 243 ++ drivers/gpu/drm/tidss/tidss_drv.c | 285 +++ drivers/gpu/drm/tidss/tidss_drv.h | 40 + drivers/gpu/drm/tidss/tidss_encoder.c | 88 + drivers/gpu/drm/tidss/tidss_encoder.h | 17 + drivers/gpu/drm/tidss/tidss_irq.c | 185 ++ drivers/gpu/drm/tidss/tidss_irq.h | 72 + drivers/gpu/drm/tidss/tidss_kms.c | 248 ++ drivers/gpu/drm/tidss/tidss_kms.h | 15 + drivers/gpu/drm/tidss/tidss_plane.c | 217 ++ drivers/gpu/drm/tidss/tidss_plane.h | 25 + drivers/gpu/drm/tidss/tidss_scale_coefs.c | 202 ++ drivers/gpu/drm/tidss/tidss_scale_coefs.h | 22 + 21 files changed, 4885 insertions(+) create mode 100644 drivers/gpu/drm/tidss/Kconfig create mode 100644 drivers/gpu/drm/tidss/Makefile create mode 100644 drivers/gpu/drm/tidss/tidss_crtc.c create mode 100644 drivers/gpu/drm/tidss/tidss_crtc.h create mode 100644 drivers/gpu/drm/tidss/tidss_dispc.c create mode 100644 drivers/gpu/drm/tidss/tidss_dispc.h create mode 100644 drivers/gpu/drm/tidss/tidss_dispc_regs.h create mode 100644 drivers/gpu/drm/tidss/tidss_drv.c create mode 100644 drivers/gpu/drm/tidss/tidss_drv.h create mode 100644 drivers/gpu/drm/tidss/tidss_encoder.c create mode 100644 drivers/gpu/drm/tidss/tidss_encoder.h create mode 100644 drivers/gpu/drm/tidss/tidss_irq.c create mode 100644 drivers/gpu/drm/tidss/tidss_irq.h create mode 100644 drivers/gpu/drm/tidss/tidss_kms.c create mode 100644 drivers/gpu/drm/tidss/tidss_kms.h create mode 100644 drivers/gpu/drm/tidss/tidss_plane.c create mode 100644 drivers/gpu/drm/tidss/tidss_plane.h create mode 100644 drivers/gpu/drm/tidss/tidss_scale_coefs.c create mode 100644 drivers/gpu/drm/tidss/tidss_scale_coefs.h
drivers/gpu/drm/Kconfig +2 -0
@@ -386,6 +386,8 @@ source "drivers/gpu/drm/aspeed/Kconfig" source "drivers/gpu/drm/mcde/Kconfig" +source "drivers/gpu/drm/tidss/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY
drivers/gpu/drm/Makefile +1 -0
@@ -122,3 +122,4 @@ obj-$(CONFIG_DRM_LIMA) += lima/ obj-$(CONFIG_DRM_PANFROST) += panfrost/ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ obj-$(CONFIG_DRM_MCDE) += mcde/ +obj-$(CONFIG_DRM_TIDSS) += tidss/
drivers/gpu/drm/tidss/Kconfig new file +14 -0
@@ -0,0 +1,14 @@ +config DRM_TIDSS + tristate "DRM Support for TI Keystone" + depends on DRM && OF + depends on ARM || ARM64 || COMPILE_TEST + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + help + The TI Keystone family SoCs introduced a new generation of + Display SubSystem. There is currently three Keystone family + SoCs released with DSS. Each with somewhat different version + of it. The SoCs are 66AK2Gx, AM65x, and J721E. Set this to Y + or M to add display support for TI Keystone family + platforms.
drivers/gpu/drm/tidss/Makefile new file +12 -0
@@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 + +tidss-y := tidss_crtc.o \ + tidss_drv.o \ + tidss_encoder.o \ + tidss_kms.o \ + tidss_irq.o \ + tidss_plane.o \ + tidss_scale_coefs.o \ + tidss_dispc.o + +obj-$(CONFIG_DRM_TIDSS) += tidss.o
drivers/gpu/drm/tidss/tidss_crtc.c new file +376 -0
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drivers/gpu/drm/tidss/tidss_crtc.h new file +46 -0
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drivers/gpu/drm/tidss/tidss_dispc.c new file +2643 -0
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drivers/gpu/drm/tidss/tidss_dispc.h new file +132 -0
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drivers/gpu/drm/tidss/tidss_dispc_regs.h new file +243 -0
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drivers/gpu/drm/tidss/tidss_drv.c new file +285 -0
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drivers/gpu/drm/tidss/tidss_drv.h new file +40 -0
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drivers/gpu/drm/tidss/tidss_encoder.c new file +88 -0
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drivers/gpu/drm/tidss/tidss_encoder.h new file +17 -0
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drivers/gpu/drm/tidss/tidss_irq.c new file +185 -0
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drivers/gpu/drm/tidss/tidss_irq.h new file +72 -0
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drivers/gpu/drm/tidss/tidss_kms.c new file +248 -0
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drivers/gpu/drm/tidss/tidss_kms.h new file +15 -0
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drivers/gpu/drm/tidss/tidss_plane.c new file +217 -0
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drivers/gpu/drm/tidss/tidss_plane.h new file +25 -0
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drivers/gpu/drm/tidss/tidss_scale_coefs.c new file +202 -0
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drivers/gpu/drm/tidss/tidss_scale_coefs.h new file +22 -0
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Signature · 6 lines
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
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PATCH v4 5/5 MAINTAINERS: add entry for tidss
In reply to Jyri SarhaAdd entry for tidss DRM driver.
Version history:
v2: no change
v3: - Move tidss entry after omapdrm
- Add "T: git git://anongit.freedesktop.org/drm/drm-misc"
v4: no change
--- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+)
MAINTAINERS +11 -0
@@ -5559,6 +5559,17 @@ S: Maintained F: drivers/gpu/drm/omapdrm/ F: Documentation/devicetree/bindings/display/ti/ +DRM DRIVERS FOR TI KEYSTONE +M: Jyri Sarha <[email protected]> +M: Tomi Valkeinen <[email protected]> +L: [email protected] +S: Maintained +F: drivers/gpu/drm/tidss/ +F: Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml +F: Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +F: Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml +T: git git://anongit.freedesktop.org/drm/drm-misc + DRM DRIVERS FOR V3D M: Eric Anholt <[email protected]> S: Supported
Signature · 1 line
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki