arm64 CPU DT binding updates
Subsystems (4)
cover arm64 CPU DT binding updates
Hi all,
Since A55 and others are now starting to show up in upstream DT postings, it seems high time to get these updated.
I haven't yet found the chance to sit down and go through the time-consuming part of cross-referencing TRMs to fill out the event maps, but it seems worth getting the fundamental definitions in sooner rather than later to at least un-block DT authors.
Thanks,
Robin.
Robin Murphy (3):
dt-bindings: ARM: Add recent Cortex/Neoverse CPUs
dt-bindings: ARM: Add recent Cortex/Neoverse PMUs
arm64: perf: Support new DT compatibles
Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++ Documentation/devicetree/bindings/arm/pmu.yaml | 9 +++++++++ arch/arm64/kernel/perf_event.c | 8 ++++++++ 3 files changed, 26 insertions(+)
Signature · 1 line
2.23.0.dirty
PATCH 1/3 dt-bindings: ARM: Add recent Cortex/Neoverse CPUs
The CPU group has been busy since we last updated these bindings... Add definitions for all the new Cortex-A and Neoverse cores now available.
--- Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++ 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/arm/cpus.yaml +9 -0
@@ -123,11 +123,18 @@ properties: - arm,cortex-a12 - arm,cortex-a15 - arm,cortex-a17 + - arm,cortex-a32 + - arm,cortex-a34 + - arm,cortex-a35 - arm,cortex-a53 - arm,cortex-a55 - arm,cortex-a57 + - arm,cortex-a65 - arm,cortex-a72 - arm,cortex-a73 + - arm,cortex-a75 + - arm,cortex-a76 + - arm,cortex-a77 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1
@@ -136,6 +143,8 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,neoverse-e1 + - arm,neoverse-n1 - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan
Signature · 1 line
2.23.0.dirty
PATCH 2/3 dt-bindings: ARM: Add recent Cortex/Neoverse PMUs
In reply to Robin MurphyAdd new PMU definitions to correspond with the CPU bindings.
--- Documentation/devicetree/bindings/arm/pmu.yaml | 9 +++++++++ 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/arm/pmu.yaml +9 -0
@@ -21,11 +21,20 @@ properties: - enum: - apm,potenza-pmu - arm,armv8-pmuv3 + - arm,neoverse-n1-pmu + - arm,neoverse-e1-pmu + - arm,cortex-a77-pmu + - arm,cortex-a76-pmu + - arm,cortex-a75-pmu - arm,cortex-a73-pmu - arm,cortex-a72-pmu + - arm,cortex-a65-pmu - arm,cortex-a57-pmu + - arm,cortex-a55-pmu - arm,cortex-a53-pmu - arm,cortex-a35-pmu + - arm,cortex-a34-pmu + - arm,cortex-a32-pmu - arm,cortex-a17-pmu - arm,cortex-a15-pmu - arm,cortex-a12-pmu
Signature · 1 line
2.23.0.dirty
Rob Herring
maintainerRe: [PATCH 2/3] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs
Quoted 13 lines · Robin Murphy
Add new PMU definitions to correspond with the CPU bindings.
Signed-off-by Robin Murphy <[email protected]>--- Documentation/devicetree/bindings/arm/pmu.yaml | 9 +++++++++ 1 file changed, 9 insertions(+)Documentation/devicetree/bindings/arm/pmu.yaml +0
-0
Documentation/devicetree/bindings/arm/pmu.yaml properties: · line 25
Quoted 5 lines
Documentation/devicetree/bindings/arm/pmu.yaml +2
-0@@ -21,11 +21,20 @@ properties: - enum: - apm,potenza-pmu - arm,armv8-pmuv3 + - arm,neoverse-n1-pmu + - arm,neoverse-e1-pmu
We've managed to do some interesting sorting here. Oh well.
I'll take patches 1 and 2.
Quoted 18 lines
Documentation/devicetree/bindings/arm/pmu.yaml +7
-1+ - arm,cortex-a77-pmu + - arm,cortex-a76-pmu + - arm,cortex-a75-pmu - arm,cortex-a73-pmu - arm,cortex-a72-pmu + - arm,cortex-a65-pmu - arm,cortex-a57-pmu + - arm,cortex-a55-pmu - arm,cortex-a53-pmu - arm,cortex-a35-pmu + - arm,cortex-a34-pmu + - arm,cortex-a32-pmu - arm,cortex-a17-pmu - arm,cortex-a15-pmu - arm,cortex-a12-pmu --2.23.0.dirty
Re: [PATCH 2/3] dt-bindings: ARM: Add recent Cortex/Neoverse PMUs
Quoted 9 lines · Rob Herring
Quoted 8 lines · Robin Murphy
Add new PMU definitions to correspond with the CPU bindings.
Signed-off-by Robin Murphy <[email protected]>--- Documentation/devicetree/bindings/arm/pmu.yaml | 9 +++++++++ 1 file changed, 9 insertions(+)
Quoted 12 lines
Documentation/devicetree/bindings/arm/pmu.yaml properties: · line 25
Quoted 10 lines
Documentation/devicetree/bindings/arm/pmu.yaml +2
-0@@ -21,11 +21,20 @@ properties: - enum: - apm,potenza-pmu - arm,armv8-pmuv3 + - arm,neoverse-n1-pmu + - arm,neoverse-e1-pmuWe've managed to do some interesting sorting here. Oh well.
Indeed; it appeared to be some sort of overlap between reverse-alpha and "big-to-little", so I just picked that up and ran with it :)
Thanks,
Robin.
Quoted 20 lines
I'll take patches 1 and 2.
Quoted 18 lines
Documentation/devicetree/bindings/arm/pmu.yaml +7
-1+ - arm,cortex-a77-pmu + - arm,cortex-a76-pmu + - arm,cortex-a75-pmu - arm,cortex-a73-pmu - arm,cortex-a72-pmu + - arm,cortex-a65-pmu - arm,cortex-a57-pmu + - arm,cortex-a55-pmu - arm,cortex-a53-pmu - arm,cortex-a35-pmu + - arm,cortex-a34-pmu + - arm,cortex-a32-pmu - arm,cortex-a17-pmu - arm,cortex-a15-pmu - arm,cortex-a12-pmu --2.23.0.dirty
PATCH 3/3 arm64: perf: Support new DT compatibles
In reply to Robin MurphyAdd support for matching the new PMUs. For now, this just wires them up as generic PMUv3 such that people writing DTs for new SoCs can do the right thing, and at least have architectural and raw events be usable. We can come back and fill in event maps for sysfs and/or perf tools at a later date.
--- arch/arm64/kernel/perf_event.c | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm64/kernel/perf_event.c +8 -0
@@ -1105,11 +1105,19 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible ="arm,armv8-pmuv3" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a34-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a35-pmu" , .data = armv8_a35_pmu_init}, {.compatible ="arm,cortex-a53-pmu" , .data = armv8_a53_pmu_init}, + {.compatible ="arm,cortex-a55-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a57-pmu" , .data = armv8_a57_pmu_init}, + {.compatible ="arm,cortex-a65-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a72-pmu" , .data = armv8_a72_pmu_init}, {.compatible ="arm,cortex-a73-pmu" , .data = armv8_a73_pmu_init}, + {.compatible ="arm,cortex-a75-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a76-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a77-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-e1-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-n1-pmu" , .data = armv8_pmuv3_init}, {.compatible ="cavium,thunder-pmu" , .data = armv8_thunder_pmu_init}, {.compatible ="brcm,vulcan-pmu" , .data = armv8_vulcan_pmu_init}, {},
Signature · 1 line
2.23.0.dirty
Re: [PATCH 3/3] arm64: perf: Support new DT compatibles
Quoted 7 lines · Robin Murphy
Add support for matching the new PMUs. For now, this just wires them up as generic PMUv3 such that people writing DTs for new SoCs can do the right thing, and at least have architectural and raw events be usable. We can come back and fill in event maps for sysfs and/or perf tools at a later date.
Signed-off-by Robin Murphy <[email protected]>
Thanks for this, it looks fine to me:
Mark.
Quoted 31 lines
--- arch/arm64/kernel/perf_event.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm64/kernel/perf_event.c +8
-0@@ -1105,11 +1105,19 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible ="arm,armv8-pmuv3" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a34-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a35-pmu" , .data = armv8_a35_pmu_init}, {.compatible ="arm,cortex-a53-pmu" , .data = armv8_a53_pmu_init}, + {.compatible ="arm,cortex-a55-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a57-pmu" , .data = armv8_a57_pmu_init}, + {.compatible ="arm,cortex-a65-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a72-pmu" , .data = armv8_a72_pmu_init}, {.compatible ="arm,cortex-a73-pmu" , .data = armv8_a73_pmu_init}, + {.compatible ="arm,cortex-a75-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a76-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a77-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-e1-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-n1-pmu" , .data = armv8_pmuv3_init}, {.compatible ="cavium,thunder-pmu" , .data = armv8_thunder_pmu_init}, {.compatible ="brcm,vulcan-pmu" , .data = armv8_vulcan_pmu_init}, {},Signature · 1 line
2.23.0.dirty
Mark Rutland
maintainerRe: [PATCH 3/3] arm64: perf: Support new DT compatibles
Quoted 7 lines · Mark Rutland
Quoted 6 lines · Robin Murphy
Add support for matching the new PMUs. For now, this just wires them up as generic PMUv3 such that people writing DTs for new SoCs can do the right thing, and at least have architectural and raw events be usable. We can come back and fill in event maps for sysfs and/or perf tools at a later date.
Quoted 5 lines
Quoted 1 line
Signed-off-by Robin Murphy <[email protected]>Thanks for this, it looks fine to me:
Acked-by Mark Rutland <[email protected]>
Argh, this isn't quite right, sorry. :/
Quoted 10 lines
Quoted 10 lines
--- arch/arm64/kernel/perf_event.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm64/kernel/perf_event.c +0
-0@@ -1105,11 +1105,19 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
Quoted 3 lines
arch/arm64/kernel/perf_event.c static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) · line 1108
Quoted 3 lines
arch/arm64/kernel/perf_event.c +1
-0static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible ="arm,armv8-pmuv3" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a34-pmu" , .data = armv8_pmuv3_init},
Unfortunately, these need their own .data so that they can be given appropriate names under sysfs.
We're stuck doing that forever for DT, though at least we learned for ACPI...
Mark.
Quoted 18 lines
Quoted 18 lines
arch/arm64/kernel/perf_event.c +7
-0{.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init}, {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init}, + {.compatible = "arm,cortex-a55-pmu", .data = armv8_pmuv3_init}, {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init}, + {.compatible = "arm,cortex-a65-pmu", .data = armv8_pmuv3_init}, {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init}, {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init}, + {.compatible = "arm,cortex-a75-pmu", .data = armv8_pmuv3_init}, + {.compatible = "arm,cortex-a76-pmu", .data = armv8_pmuv3_init}, + {.compatible = "arm,cortex-a77-pmu", .data = armv8_pmuv3_init}, + {.compatible = "arm,neoverse-e1-pmu", .data = armv8_pmuv3_init}, + {.compatible = "arm,neoverse-n1-pmu", .data = armv8_pmuv3_init}, {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, {},Signature · 1 line
2.23.0.dirty
Re: [PATCH 3/3] arm64: perf: Support new DT compatibles
In reply to Robin MurphyOn Fri, 21 Feb 2020 16:04:58 +0000
Robin Murphy <[email protected]> wrote:
Hi,
Quoted 5 lines
Add support for matching the new PMUs. For now, this just wires them up as generic PMUv3 such that people writing DTs for new SoCs can do the right thing, and at least have architectural and raw events be usable. We can come back and fill in event maps for sysfs and/or perf tools at a later date.
as mentioned already in a reply to another patch:
Is that really the right way? Isn't that calling for the intended usage of a compatible fall-back string? So that a machine can just ship DTBs with for instance:
"arm,neoverse-n1-pmu", "arm,armv8-pmuv3";
and that would magically work with all older and newer kernels already, without any patch?
As it stands right now (with a single compatible), only newer kernels could use the PMU on those SoCs (ignoring tedious backports not reaching every user).
All that would be needed for that is to officially allow two compatible strings in the binding.
Cheers,
Andre.
P.S. Still thinking about dropping those compatible strings at all and using the MIDR somehow, because then also ACPI users would benefit from core specific events.
Quoted 29 lines
Signed-off-by Robin Murphy <[email protected]>--- arch/arm64/kernel/perf_event.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm64/kernel/perf_event.c +8
-0@@ -1105,11 +1105,19 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible ="arm,armv8-pmuv3" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a34-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a35-pmu" , .data = armv8_a35_pmu_init}, {.compatible ="arm,cortex-a53-pmu" , .data = armv8_a53_pmu_init}, + {.compatible ="arm,cortex-a55-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a57-pmu" , .data = armv8_a57_pmu_init}, + {.compatible ="arm,cortex-a65-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a72-pmu" , .data = armv8_a72_pmu_init}, {.compatible ="arm,cortex-a73-pmu" , .data = armv8_a73_pmu_init}, + {.compatible ="arm,cortex-a75-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a76-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a77-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-e1-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-n1-pmu" , .data = armv8_pmuv3_init}, {.compatible ="cavium,thunder-pmu" , .data = armv8_thunder_pmu_init}, {.compatible ="brcm,vulcan-pmu" , .data = armv8_vulcan_pmu_init}, {},
Mark Rutland
maintainerRe: [PATCH 3/3] arm64: perf: Support new DT compatibles
Quoted 18 lines · Andre Przywara
On Fri, 21 Feb 2020 16:04:58 +0000
Robin Murphy <[email protected]> wrote:Hi,
Quoted 5 lines
Add support for matching the new PMUs. For now, this just wires them up as generic PMUv3 such that people writing DTs for new SoCs can do the right thing, and at least have architectural and raw events be usable. We can come back and fill in event maps for sysfs and/or perf tools at a later date.
as mentioned already in a reply to another patch:
Is that really the right way? Isn't that calling for the intended usage of a compatible fall-back string? So that a machine can just ship DTBs with for instance:
"arm,neoverse-n1-pmu", "arm,armv8-pmuv3";and that would magically work with all older and newer kernels already, without any patch?
Quoted 8 lines
As it stands right now (with a single compatible), only newer kernels could use the PMU on those SoCs (ignoring tedious backports not reaching every user).
All that would be needed for that is to officially allow two compatible strings in the binding.
Cheers,
Andre.
P.S. Still thinking about dropping those compatible strings at all and using the MIDR somehow, because then also ACPI users would benefit from core specific events.
For ACPI we've said that the way forward is the userspace mappings, so that's already solved (and to a much greater degree than we could do within the kernel).
The names for DT are an unfortunate legacy thing that we simply have to carry on with going forward in for the UAPI under sysfs.
I don't want to go mapping MIDRs to names, and open other worm cans.
Thanksm
Mark.
Quoted 31 lines
Quoted 30 lines
Signed-off-by Robin Murphy <[email protected]>--- arch/arm64/kernel/perf_event.c | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm64/kernel/perf_event.c +8
-0@@ -1105,11 +1105,19 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible ="arm,armv8-pmuv3" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a34-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a35-pmu" , .data = armv8_a35_pmu_init}, {.compatible ="arm,cortex-a53-pmu" , .data = armv8_a53_pmu_init}, + {.compatible ="arm,cortex-a55-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a57-pmu" , .data = armv8_a57_pmu_init}, + {.compatible ="arm,cortex-a65-pmu" , .data = armv8_pmuv3_init}, {.compatible ="arm,cortex-a72-pmu" , .data = armv8_a72_pmu_init}, {.compatible ="arm,cortex-a73-pmu" , .data = armv8_a73_pmu_init}, + {.compatible ="arm,cortex-a75-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a76-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,cortex-a77-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-e1-pmu" , .data = armv8_pmuv3_init}, + {.compatible ="arm,neoverse-n1-pmu" , .data = armv8_pmuv3_init}, {.compatible ="cavium,thunder-pmu" , .data = armv8_thunder_pmu_init}, {.compatible ="brcm,vulcan-pmu" , .data = armv8_vulcan_pmu_init}, {},