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MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses

PATCH Superseded H. Nikolaus Schaller 2 participants 15 messages Feb 26, 2020 – Feb 28, 2020

Subsystems (4)
Device tree bindings MIPS NVMEM framework Ingenic JZ47xx SoCs

v6 of 8 Superseded Latest is v8 →

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H. Nikolaus Schaller

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#0 lore raw

v6 cover MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses

* add dependency on CONFIG_OF and select REGMAP_MMIO (suggested by Paul Cercueil <[email protected]>)
* add clk_prepare_enable() (suggested by Paul Cercueil <[email protected]>)
* inline jz4780_efuse_read_32bytes() since it is only used once
* remove read optimization for full block (suggested by Paul Cercueil <[email protected]>)
* simplify calculations for rd_adj and rd_strobe (suggested by Paul Cercueil <[email protected]>)
* do calculations for rd_adj and rd_strobe in local variables
* fix overflow check (did allow for 5 bit values although register is 4 bit wide)
* fixes for yaml (sugested by Andreas Kemnade <[email protected]>)

PATCH V5 2020-02-22 11:25:35:
* no longer RFC but PATCH
* add yaml bindings (by Andreas Kemnade <[email protected]>)
* fixes to yaml (suggested by Rob Herring <[email protected]>)

RFC V4 2020-02-17 17:55:35:
* removed read_only for nvmem config because there is no write method
* Kconfig: replaced depends MACH_JZ4780 with MACH_INGENIC
* run through checkpatch and fixed issues
* made use of devm_nvram_register() and get rid of jz4780_efuse_remove() (suggested by Srinivas Kandagatla <[email protected]>)
* squashed previous patch 1/9 and 2/9 into single (regmap based) driver

RFC V3 2020-02-16 20:20:59:

This series is based on and a follow up for

https://lore.kernel.org/patchwork/cover/868157/

("[v2,0/2] Add efuse driver for Ingenic JZ4780 SoC")

Original authors were
PrasannaKumar Muralidharan <[email protected]> Mathieu Malaterre <[email protected]>

and there are additions / code improvements by
H. Nikolaus Schaller <[email protected]>
Paul Cercueil <[email protected]>

This setup works, if the dm9000 driver is compiled as a module.

Therefore it is all RFC level. It is also not completely checkpatched.

H. Nikolaus Schaller (1):
MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the
default MAC address

PrasannaKumar Muralidharan (5):
nvmem: add driver for JZ4780 efuse
Bindings: nvmem: add bindings for JZ4780 efuse
Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI
nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver
MIPS: DTS: JZ4780: define node for JZ4780 efuse

 .../ABI/testing/sysfs-driver-jz4780-efuse     |  16 ++
 .../bindings/nvmem/ingenic,jz4780-efuse.yaml  |  50 ++++
 MAINTAINERS                                   |   5 +
 arch/mips/boot/dts/ingenic/ci20.dts           |   3 +
 arch/mips/boot/dts/ingenic/jz4780.dtsi        |  17 +-
 drivers/nvmem/Kconfig                         |  12 +
 drivers/nvmem/Makefile                        |   2 +
 drivers/nvmem/jz4780-efuse.c                  | 239 ++++++++++++++++++
 8 files changed, 343 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse
 create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
 create mode 100644 drivers/nvmem/jz4780-efuse.c
Signature · 1 line
2.23.0
author
#1 lore raw

PATCH v6 1/6 nvmem: add driver for JZ4780 efuse

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells.

To fetch for example the MAC address:

dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
Signed-off-by Paul Cercueil <[email protected]>
---
 drivers/nvmem/Kconfig        |  12 ++
 drivers/nvmem/Makefile       |   2 +
 drivers/nvmem/jz4780-efuse.c | 239 +++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+)
 create mode 100644 drivers/nvmem/jz4780-efuse.c
drivers/nvmem/Kconfig +12 -0
index 35efab1ba8d9..d7b7f6d688e7 100644
@@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU
 	  This is a driver for the SCU On-Chip OTP Controller (OCOTP)
 	  available on i.MX8 SoCs.
 
+config JZ4780_EFUSE
+	tristate "JZ4780 EFUSE Memory Support"
+	depends on MACH_INGENIC || COMPILE_TEST
+	depends on HAS_IOMEM
+	depends on OF
+	select REGMAP_MMIO
+	help
+	  Say Y here to include support for JZ4780 efuse memory found on
+	  all JZ4780 SoC based devices.
+	  To compile this driver as a module, choose M here: the module
+	  will be called nvmem_jz4780_efuse.
+
 config NVMEM_LPC18XX_EEPROM
 	tristate "NXP LPC18XX EEPROM Memory Support"
 	depends on ARCH_LPC18XX || COMPILE_TEST
drivers/nvmem/Makefile +2 -0
index 6b466cd1427b..65a268d17807 100644
@@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP)	+= nvmem-imx-ocotp.o
 nvmem-imx-ocotp-y		:= imx-ocotp.o
 obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU)	+= nvmem-imx-ocotp-scu.o
 nvmem-imx-ocotp-scu-y		:= imx-ocotp-scu.o
+obj-$(CONFIG_JZ4780_EFUSE)		+= nvmem_jz4780_efuse.o
+nvmem_jz4780_efuse-y		:= jz4780-efuse.o
 obj-$(CONFIG_NVMEM_LPC18XX_EEPROM)	+= nvmem_lpc18xx_eeprom.o
 nvmem_lpc18xx_eeprom-y	:= lpc18xx_eeprom.o
 obj-$(CONFIG_NVMEM_LPC18XX_OTP)	+= nvmem_lpc18xx_otp.o
drivers/nvmem/jz4780-efuse.c new file +239 -0

239 lines not on this page · raw message

Signature · 1 line
2.23.0
maintainer
#2 lore raw

Re: [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse

Hi Nikolaus,

Quoted 246 lines · H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells.

To fetch for example the MAC address:

dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
Signed-off-by Paul Cercueil <[email protected]>
---
 drivers/nvmem/Kconfig        |  12 ++
 drivers/nvmem/Makefile       |   2 +
 drivers/nvmem/jz4780-efuse.c | 239 
+++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+)
 create mode 100644 drivers/nvmem/jz4780-efuse.c
drivers/nvmem/Kconfig +12 -0
index 35efab1ba8d9..d7b7f6d688e7 100644
@@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU
 	  This is a driver for the SCU On-Chip OTP Controller (OCOTP)
 	  available on i.MX8 SoCs.
 
+config JZ4780_EFUSE
+	tristate "JZ4780 EFUSE Memory Support"
+	depends on MACH_INGENIC || COMPILE_TEST
+	depends on HAS_IOMEM
+	depends on OF
+	select REGMAP_MMIO
+	help
+	  Say Y here to include support for JZ4780 efuse memory found on
+	  all JZ4780 SoC based devices.
+	  To compile this driver as a module, choose M here: the module
+	  will be called nvmem_jz4780_efuse.
+
 config NVMEM_LPC18XX_EEPROM
 	tristate "NXP LPC18XX EEPROM Memory Support"
 	depends on ARCH_LPC18XX || COMPILE_TEST
drivers/nvmem/Makefile +2 -0
index 6b466cd1427b..65a268d17807 100644
@@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP)	+= nvmem-imx-ocotp.o
 nvmem-imx-ocotp-y		:= imx-ocotp.o
 obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU)	+= nvmem-imx-ocotp-scu.o
 nvmem-imx-ocotp-scu-y		:= imx-ocotp-scu.o
+obj-$(CONFIG_JZ4780_EFUSE)		+= nvmem_jz4780_efuse.o
+nvmem_jz4780_efuse-y		:= jz4780-efuse.o
 obj-$(CONFIG_NVMEM_LPC18XX_EEPROM)	+= nvmem_lpc18xx_eeprom.o
 nvmem_lpc18xx_eeprom-y	:= lpc18xx_eeprom.o
 obj-$(CONFIG_NVMEM_LPC18XX_OTP)	+= nvmem_lpc18xx_otp.o
drivers/nvmem/jz4780-efuse.c new file +5 -0
new file mode 100644
index 000000000000..4b8077a8d251
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * JZ4780 EFUSE Memory Support driver
+ *
+ * Copyright (c) 2017 PrasannaKumar Muralidharan

<[email protected]>
+ * Copyright (c) 2020 H. Nikolaus Schaller <[email protected]>
+ */

drivers/nvmem/jz4780-efuse.c new file +7 -1
+
+/*
+ * Currently supports JZ4780 efuse which has 8K programmable bit.
+ * Efuse is separated into seven segments as below:
+ *
+ * 
-----------------------------------------------------------------------
+ * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048

bit |
+ *
-----------------------------------------------------------------------
+ *
+ * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
+ * which reads/writes based on strobes. The strobe is configured in the config
+ * register and is based on number of cycles of the bus clock.
+ *
+ * Driver supports read only as the writes are done in the Factory.
+ */

drivers/nvmem/jz4780-efuse.c new file +154 -0
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/timer.h>
+
+#define JZ_EFUCTRL		(0x0)	/* Control Register */
+#define JZ_EFUCFG		(0x4)	/* Configure Register*/
+#define JZ_EFUSTATE		(0x8)	/* Status Register */
+#define JZ_EFUDATA(n)		(0xC + (n) * 4)
+
+/* We read 32 byte chunks to avoid complexity in the driver. */
+#define JZ_EFU_READ_SIZE 32
+
+#define EFUCTRL_ADDR_MASK	0x3FF
+#define EFUCTRL_ADDR_SHIFT	21
+#define EFUCTRL_LEN_MASK	0x1F
+#define EFUCTRL_LEN_SHIFT	16
+#define EFUCTRL_PG_EN		BIT(15)
+#define EFUCTRL_WR_EN		BIT(1)
+#define EFUCTRL_RD_EN		BIT(0)
+
+#define EFUCFG_INT_EN		BIT(31)
+#define EFUCFG_RD_ADJ_MASK	0xF
+#define EFUCFG_RD_ADJ_SHIFT	20
+#define EFUCFG_RD_STR_MASK	0xF
+#define EFUCFG_RD_STR_SHIFT	16
+#define EFUCFG_WR_ADJ_MASK	0xF
+#define EFUCFG_WR_ADJ_SHIFT	12
+#define EFUCFG_WR_STR_MASK	0xFFF
+#define EFUCFG_WR_STR_SHIFT	0
+
+#define EFUSTATE_WR_DONE	BIT(1)
+#define EFUSTATE_RD_DONE	BIT(0)
+
+struct jz4780_efuse {
+	struct device *dev;
+	struct regmap *map;
+	struct clk *clk;
+};
+
+/* main entry point */
+static int jz4780_efuse_read(void *context, unsigned int offset,
+			     void *val, size_t bytes)
+{
+	struct jz4780_efuse *efuse = context;
+
+	while (bytes > 0) {
+		unsigned int start = offset & ~(JZ_EFU_READ_SIZE - 1);
+		unsigned int chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
+					 - offset);
+		char buf[JZ_EFU_READ_SIZE];
+		unsigned int tmp;
+		u32 ctrl;
+		int ret;
+
+		ctrl = (start << EFUCTRL_ADDR_SHIFT)
+			| ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
+			| EFUCTRL_RD_EN;
+
+		regmap_update_bits(efuse->map, JZ_EFUCTRL,
+				   (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
+				   (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
+				   EFUCTRL_PG_EN | EFUCTRL_WR_EN |
+				   EFUCTRL_RD_EN,
+				   ctrl);
+
+		ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
+					       tmp, tmp & EFUSTATE_RD_DONE,
+					       1 * MSEC_PER_SEC,
+					       50 * MSEC_PER_SEC);
+		if (ret < 0) {
+			dev_err(efuse->dev, "Time out while reading efuse data");
+			return ret;
+		}
+
+		ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
+				       buf, JZ_EFU_READ_SIZE / sizeof(u32));
+		if (ret < 0)
+			return ret;
+
+		memcpy(val, &buf[offset - start], chunk);
+
+		val += chunk;
+		offset += chunk;
+		bytes -= chunk;
+	}
+
+	return 0;
+}
+
+static struct nvmem_config jz4780_efuse_nvmem_config = {
+	.name = "jz4780-efuse",
+	.size = 1024,
+	.word_size = 1,
+	.stride = 1,
+	.owner = THIS_MODULE,
+	.reg_read = jz4780_efuse_read,
+};
+
+static const struct regmap_config jz4780_efuse_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.max_register = JZ_EFUDATA(7),
+};
+
+static int jz4780_efuse_probe(struct platform_device *pdev)
+{
+	struct nvmem_device *nvmem;
+	struct jz4780_efuse *efuse;
+	struct nvmem_config cfg;
+	unsigned long clk_rate;
+	unsigned long rd_adj;
+	unsigned long rd_strobe;
+	struct device *dev = &pdev->dev;
+	void __iomem *regs;
+	int ret;
+
+	efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
+	if (!efuse)
+		return -ENOMEM;
+
+	regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	efuse->map = devm_regmap_init_mmio(dev, regs,
+					   &jz4780_efuse_regmap_config);
+	if (IS_ERR(efuse->map))
+		return PTR_ERR(efuse->map);
+
+	efuse->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(efuse->clk))
+		return PTR_ERR(efuse->clk);
+
+	ret = clk_prepare_enable(efuse->clk);
+	if (ret < 0)
+		return ret;
+
+	clk_rate = clk_get_rate(efuse->clk);
+
+	efuse->dev = dev;
+
+	/*
+	 * rd_adj and rd_strobe are 4 bit values
+	 * conditions:
+	 *   bus clk_period * (rd_adj + 1) > 6.5ns
+	 *   bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
+	 *   i.e. rd_adj >= 6.5ns / clk_period

drivers/nvmem/jz4780-efuse.c line 186

Quoted 10 lines
drivers/nvmem/jz4780-efuse.c new file +10 -0
+	 *   i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
+	 * constants:
+	 *   1 / 6.5ns == 153846154 Hz
+	 *   1 / 35ns == 28571429 Hz
+	 */
+
+	rd_adj = clk_rate / 153846154;
+	rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
+
+	if (rd_adj > BIT(4) - 1 || rd_strobe > BIT(4) - 1) {

Just use 0xF or GENMASK(3, 0) instead of BIT(4) - 1

drivers/nvmem/jz4780-efuse.c line 188

Quoted 2 lines
drivers/nvmem/jz4780-efuse.c new file +2 -0
+		dev_err(&pdev->dev, "Cannot set clock configuration\n");
+		return -EINVAL;

You need to clk_disable_unprepare() before you return now, since the clock has been enabled. I'd suggest registering a cleanup function (with devm_add_action_or_reset) after clk_prepare_enable() is called, then you don't need extra handling in the rest of the probe, and the .remove function (and platform_set_drvdata) can be dropped too.

The rest looks pretty good.

Cheers,
-Paul

Quoted 55 lines
drivers/nvmem/jz4780-efuse.c new file +47 -0
+	}
+
+	regmap_update_bits(efuse->map, JZ_EFUCFG,
+			   (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
+			   (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
+			   (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
+			   (rd_strobe << EFUCFG_RD_STR_SHIFT));
+
+	cfg = jz4780_efuse_nvmem_config;
+	cfg.dev = &pdev->dev;
+	cfg.priv = efuse;
+
+	nvmem = devm_nvmem_register(dev, &cfg);
+	if (IS_ERR(nvmem))
+		return PTR_ERR(nvmem);
+
+	platform_set_drvdata(pdev, efuse);
+
+	return 0;
+}
+
+static int jz4780_efuse_remove(struct platform_device *pdev)
+{
+	struct jz4780_efuse *efuse = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(efuse->clk);
+
+	return 0;
+}
+
+static const struct of_device_id jz4780_efuse_match[] = {
+	{ .compatible = "ingenic,jz4780-efuse" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+
+static struct platform_driver jz4780_efuse_driver = {
+	.probe  = jz4780_efuse_probe,
+	.remove  = jz4780_efuse_remove,
+	.driver = {
+		.name = "jz4780-efuse",
+		.of_match_table = jz4780_efuse_match,
+	},
+};
+module_platform_driver(jz4780_efuse_driver);
+
+MODULE_AUTHOR("PrasannaKumar Muralidharan

<[email protected]>");

drivers/nvmem/jz4780-efuse.c new file +4 -1
+MODULE_AUTHOR("H. Nikolaus Schaller <[email protected]>");
+MODULE_AUTHOR("Paul Cercueil <[email protected]>");
+MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
--

2.23.0

author
#3 lore raw

Re: [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse

Hi Paul,

Quoted 43 lines

Am 27.02.2020 um 15:47 schrieb Paul Cercueil <[email protected]>:

Hi Nikolaus,

Quoted 37 lines · H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory and nvmem cells.
To fetch for example the MAC address:
dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
Signed-off-by Paul Cercueil <[email protected]>

---

drivers/nvmem/Kconfig        |  12 ++
drivers/nvmem/Makefile       |   2 +
drivers/nvmem/jz4780-efuse.c | 239 +++++++++++++++++++++++++++++++++++
3 files changed, 253 insertions(+)

create mode 100644 drivers/nvmem/jz4780-efuse.c

drivers/nvmem/Kconfig +14 -0
index 35efab1ba8d9..d7b7f6d688e7 100644
@@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU
 
 
+	clk_rate = clk_get_rate(efuse->clk);
+
+	efuse->dev = dev;
+
+	/*
+	 * rd_adj and rd_strobe are 4 bit values
+	 * conditions:
+	 *   bus clk_period * (rd_adj + 1) > 6.5ns
+	 *   bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
+	 *   i.e. rd_adj >= 6.5ns / clk_period
+	 *   i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
+	 * constants:
+	 *   1 / 6.5ns == 153846154 Hz
+	 *   1 / 35ns == 28571429 Hz
Quoted 8 lines

drivers/nvmem/Kconfig config NVMEM_IMX_OCOTP_SCU

Quoted 6 lines
drivers/nvmem/Kconfig +6 -0
+	 */
+
+	rd_adj = clk_rate / 153846154;
+	rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
+
+	if (rd_adj > BIT(4) - 1 || rd_strobe > BIT(4) - 1) {

Just use 0xF or GENMASK(3, 0) instead of BIT(4) - 1

Or would rd_adj >= BIT(4) be better since this is not used as a mask? This would also correspond to that the register is 4 bits wide.

Quoted 5 lines

drivers/nvmem/Kconfig

Quoted 3 lines
drivers/nvmem/Kconfig +2 -0
+		dev_err(&pdev->dev, "Cannot set clock configuration\n");
+		return -EINVAL;

You need to clk_disable_unprepare() before you return now, since the clock has been enabled.

Ah, ok! Forgot about that.

Quoted 1 line

I'd suggest registering a cleanup function (with devm_add_action_or_reset) after clk_prepare_enable() is called, then you don't need extra handling in the rest of the probe, and the .remove function (and platform_set_drvdata) can be dropped too.

Ok, this will indeed be simpler that the remove function if we take the error path into account.

Noted for v7.

Quoted 5 lines

The rest looks pretty good.

Cheers,
-Paul

BR,
Nikolaus

author
#4 lore raw

Re: [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse

Quoted 10 lines
Quoted 7 lines

drivers/nvmem/jz4780-efuse.c line 186

Quoted 5 lines
drivers/nvmem/jz4780-efuse.c new file +4 -0
+	rd_adj = clk_rate / 153846154;
+	rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
+
+	if (rd_adj > BIT(4) - 1 || rd_strobe > BIT(4) - 1) {

Just use 0xF or GENMASK(3, 0) instead of BIT(4) - 1

Or would rd_adj >= BIT(4) be better since this is not used as a mask? This would also correspond to that the register is 4 bits wide.

I just recognized that we already have these constants defined:

So I'll add

	if (rd_adj > EFUCFG_RD_ADJ_MASK || rd_strobe > EFUCFG_RD_STR_MASK) {

to v7.

BR,
Nikolaus

author
#5 lore raw

PATCH v6 2/6 Bindings: nvmem: add bindings for JZ4780 efuse

In reply to H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
[converted to yaml]
Signed-off-by Andreas Kemnade <[email protected]>
---
 .../bindings/nvmem/ingenic,jz4780-efuse.yaml  | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +50 -0
new file mode 100644
index 000000000000..b9c0ea09b335
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic JZ EFUSE driver bindings
+
+maintainers:
+  - PrasannaKumar Muralidharan <[email protected]>
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - ingenic,jz4780-efuse
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    # Handle for the ahb for the efuse.
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ahb2
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/jz4780-cgu.h>
+
+    efuse@134100d0 {
+        compatible = "ingenic,jz4780-efuse";
+        reg = <0x134100d0 0x2c>;
+
+        clocks = <&cgu JZ4780_CLK_AHB2>;
+        clock-names = "ahb2";
+    };
+
+...
Signature · 1 line
2.23.0
maintainer
#6 lore raw

Re: [PATCH v6 2/6] Bindings: nvmem: add bindings for JZ4780 efuse

Hi Nikolaus,

Quoted 44 lines · H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
[converted to yaml]
Signed-off-by Andreas Kemnade <[email protected]>
---
 .../bindings/nvmem/ingenic,jz4780-efuse.yaml  | 50 
+++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml

(quoted diff) +0 -0
new file mode 100644
index 000000000000..b9c0ea09b335

b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml

Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +19 -0
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic JZ EFUSE driver bindings
+
+maintainers:
+  - PrasannaKumar Muralidharan <[email protected]>
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - ingenic,jz4780-efuse
+

Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml line 29

Quoted 10 lines
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +10 -0
+  reg:
+    maxItems: 1
+
+  clocks:
+    # Handle for the ahb for the efuse.
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ahb2

Your driver does not actually require the clock to be 'ahb2', it will take the first clock independently of its name. So 'clock-names' can be dropped.

Quoted 8 lines
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +8 -0
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+unevaluatedProperties: false
+

Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml line 47

Quoted 10 lines
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +10 -0
+examples:
+  - |
+    #include <dt-bindings/clock/jz4780-cgu.h>
+
+    efuse@134100d0 {
+        compatible = "ingenic,jz4780-efuse";
+        reg = <0x134100d0 0x2c>;
+
+        clocks = <&cgu JZ4780_CLK_AHB2>;
+        clock-names = "ahb2";

Same here.

Cheers,
-Paul

Quoted 6 lines
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +3 -1
+    };
+
+...
--

2.23.0

author
#7 lore raw

Re: [PATCH v6 2/6] Bindings: nvmem: add bindings for JZ4780 efuse

Quoted 70 lines

Am 27.02.2020 um 15:49 schrieb Paul Cercueil <[email protected]>:

Hi Nikolaus,

Quoted 38 lines · H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]> This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
[converted to yaml]
Signed-off-by Andreas Kemnade <[email protected]>

---
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++

1 file changed, 50 insertions(+)

create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml

Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +19 -0
new file mode 100644
index 000000000000..b9c0ea09b335
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic JZ EFUSE driver bindings
+
+maintainers:
+  - PrasannaKumar Muralidharan <[email protected]>
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  compatible:
+    enum:
+      - ingenic,jz4780-efuse
+

Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml line 29

Quoted 10 lines
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +10 -0
+  reg:
+    maxItems: 1
+
+  clocks:
+    # Handle for the ahb for the efuse.
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ahb2

Your driver does not actually require the clock to be 'ahb2', it will take the first clock independently of its name. So 'clock-names' can be dropped.

Quoted 12 lines
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +12 -0
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/jz4780-cgu.h>
+
Quoted 8 lines

Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml line 47

Quoted 6 lines
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file +6 -0
+    efuse@134100d0 {
+        compatible = "ingenic,jz4780-efuse";
+        reg = <0x134100d0 0x2c>;
+
+        clocks = <&cgu JZ4780_CLK_AHB2>;
+        clock-names = "ahb2";

Same here.

Ok! Will also update in the real .dts.

BR and thanks,
Nikolaus

author
#8 lore raw

PATCH v6 3/6 Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI

In reply to H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
---
 .../ABI/testing/sysfs-driver-jz4780-efuse        | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse
Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file +16 -0
new file mode 100644
index 000000000000..bb6f5d6ceea0
@@ -0,0 +1,16 @@
+What:		/sys/devices/*/<our-device>/nvmem
+Date:		December 2017
+Contact:	PrasannaKumar Muralidharan <[email protected]>
+Description:	read-only access to the efuse on the Ingenic JZ4780 SoC
+		The SoC has a one time programmable 8K efuse that is
+		split into segments. The driver supports read only.
+		The segments are
+		0x000   64 bit Random Number
+		0x008  128 bit Ingenic Chip ID
+		0x018  128 bit Customer ID
+		0x028 3520 bit Reserved
+		0x1E0    8 bit Protect Segment
+		0x1E1 2296 bit HDMI Key
+		0x300 2048 bit Security boot key
+Users:		any user space application which wants to read the Chip
+		and Customer ID
Signature · 1 line
2.23.0
author
#9 lore raw

PATCH v6 4/6 nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver

In reply to H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
---
 MAINTAINERS | 5 +++++
 1 file changed, 5 insertions(+)
MAINTAINERS +5 -0
index fcd79fc38928..fcb8d89c2b2e 100644
@@ -8271,6 +8271,11 @@ M:	Zubair Lutfullah Kakakhel <[email protected]>
 S:	Maintained
 F:	drivers/dma/dma-jz4780.c
 
+INGENIC JZ4780 EFUSE Driver
+M:	PrasannaKumar Muralidharan <[email protected]>
+S:	Maintained
+F:	drivers/nvmem/jz4780-efuse.c
+
 INGENIC JZ4780 NAND DRIVER
 M:	Harvey Hunt <[email protected]>
 L:	[email protected]
Signature · 1 line
2.23.0
author
#10 lore raw

PATCH v6 5/6 MIPS: DTS: JZ4780: define node for JZ4780 efuse

In reply to H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board.

It also changes the nemc reg range to avoid overlap.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)
arch/mips/boot/dts/ingenic/jz4780.dtsi +16 -1
index f928329b034b..1e266be28096 100644
@@ -358,7 +358,7 @@
 
 	nemc: nemc@13410000 {
 		compatible = "ingenic,jz4780-nemc";
-		reg = <0x13410000 0x10000>;
+		reg = <0x13410000 0x4c>;
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges = <1 0 0x1b000000 0x1000000

@@ -373,6 +373,21 @@
 		status = "disabled";
 	};
 
+	efuse: efuse@134100d0 {
+		compatible = "ingenic,jz4780-efuse";
+		reg = <0x134100d0 0x2c>;
+
+		clocks = <&cgu JZ4780_CLK_AHB2>;
+		clock-names = "ahb2";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eth0_addr: eth-mac-addr@0x22 {
+			reg = <0x22 0x6>;
+		};
+	};
+
 	dma: dma@13420000 {
 		compatible = "ingenic,jz4780-dma";
 		reg = <0x13420000 0x400
Signature · 1 line
2.23.0
maintainer
#11 lore raw

Re: [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse

Hi Nikolaus,

Quoted 21 lines · H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]>

This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board.

It also changes the nemc reg range to avoid overlap.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>
---
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)
arch/mips/boot/dts/ingenic/jz4780.dtsi +0 -0
index f928329b034b..1e266be28096 100644

arch/mips/boot/dts/ingenic/jz4780.dtsi line 361

Quoted 5 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +1 -1
@@ -358,7 +358,7 @@
 
 	nemc: nemc@13410000 {
 		compatible = "ingenic,jz4780-nemc";
-		reg = <0x13410000 0x10000>;
+		reg = <0x13410000 0x4c>;

This is wrong, the real size of the register area is 1x15c.

arch/mips/boot/dts/ingenic/jz4780.dtsi line 381

Quoted 13 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +6 -0
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges = <1 0 0x1b000000 0x1000000

@@ -373,6 +373,21 @@
 		status = "disabled";
 	};
 
+	efuse: efuse@134100d0 {
+		compatible = "ingenic,jz4780-efuse";
+		reg = <0x134100d0 0x2c>;
+
+		clocks = <&cgu JZ4780_CLK_AHB2>;
+		clock-names = "ahb2";

As explained in my response to the other patch, 'clock-names' can go away.

Cheers,
-Paul

Quoted 15 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +9 -1
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eth0_addr: eth-mac-addr@0x22 {
+			reg = <0x22 0x6>;
+		};
+	};
+
 	dma: dma@13420000 {
 		compatible = "ingenic,jz4780-dma";
 		reg = <0x13420000 0x400
--

2.23.0

author
#12 lore raw

Re: [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse

Hi Paul,

Quoted 21 lines

Am 27.02.2020 um 15:57 schrieb Paul Cercueil <[email protected]>:

Hi Nikolaus,

Quoted 15 lines · H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]> This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board. It also changes the nemc reg range to avoid overlap.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan <[email protected]>
Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>

---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-

1 file changed, 16 insertions(+), 1 deletion(-)
arch/mips/boot/dts/ingenic/jz4780.dtsi +0 -1
index f928329b034b..1e266be28096 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
Quoted 8 lines

arch/mips/boot/dts/ingenic/jz4780.dtsi line 360

Quoted 6 lines

+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi

arch/mips/boot/dts/ingenic/jz4780.dtsi +1 -1
@@ -358,7 +358,7 @@
 	nemc: nemc@13410000 {
 		compatible = "ingenic,jz4780-nemc";
-		reg = <0x13410000 0x10000>;
+		reg = <0x13410000 0x4c>;

This is wrong, the real size of the register area is 1x15c.

It should not overlap with the efuse reg range which is:

<0x134100d0 0x2c>

If I look at JZ4780 Mobile Application Processor Programming Manual section 16.4.1 Register Description Table 16-4 Static Memory Interface Registers, I see

SMCR1 at 0x13410014 and
SACR6 at 0x13410048 and all 32 bits wide. I.e. a total size of 0x4c.

Ah, now I see. There is also Table 16-5 NAND Flash Interface Registers starting with NFCSR at 0x13410050 and ending with TGHH register at 0x13410154.

Hm. With this we are probably at "go back and start over"...

Either nemc must be separated into two drivers for Static Memory and one for NAND Flash. Or must become able to handle two register ranges.

Or the e-fuse driver must become a part of the nemc driver.

Well, another assumption is that there is no NAND driver. AFAIR it was even removed from the kernel because the maintainer did say it is not fixable (if I really remember correctly).

Quoted 15 lines

arch/mips/boot/dts/ingenic/jz4780.dtsi line 380

Quoted 13 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +6 -0
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges = <1 0 0x1b000000 0x1000000

@@ -373,6 +373,21 @@
 		status = "disabled";
 	};
+	efuse: efuse@134100d0 {
+		compatible = "ingenic,jz4780-efuse";
+		reg = <0x134100d0 0x2c>;
+
+		clocks = <&cgu JZ4780_CLK_AHB2>;
+		clock-names = "ahb2";

As explained in my response to the other patch, 'clock-names' can go away.

Yes.

BR,
Nikolaus

maintainer
#13 lore raw

Re: [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse

Quoted 50 lines · H. Nikolaus Schaller

Hi Paul,

Quoted 32 lines

Am 27.02.2020 um 15:57 schrieb Paul Cercueil <[email protected]>:

Hi Nikolaus,

Quoted 20 lines · H. Nikolaus Schaller

From: PrasannaKumar Muralidharan <[email protected]> This patch brings support for the JZ4780 efuse. Currently it only
exposes
a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board. It also changes the nemc reg range to avoid overlap.

Tested-by Mathieu Malaterre <[email protected]>
Signed-off-by PrasannaKumar Muralidharan

<[email protected]>

Signed-off-by Mathieu Malaterre <[email protected]>
Signed-off-by H. Nikolaus Schaller <[email protected]>

---

 arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index f928329b034b..1e266be28096 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -358,7 +358,7 @@

arch/mips/boot/dts/ingenic/jz4780.dtsi

Quoted 4 lines
arch/mips/boot/dts/ingenic/jz4780.dtsi +0 -0
 	nemc: nemc@13410000 {
 		compatible = "ingenic,jz4780-nemc";
 -		reg = <0x13410000 0x10000>;
 +		reg = <0x13410000 0x4c>;
Quoted 1 line

This is wrong, the real size of the register area is 1x15c.

It should not overlap with the efuse reg range which is:

<0x134100d0 0x2c>

If I look at JZ4780 Mobile Application Processor Programming Manual section 16.4.1 Register Description Table 16-4 Static Memory Interface Registers, I see

SMCR1 at 0x13410014 and
SACR6 at 0x13410048 and all 32 bits wide. I.e. a total size of 0x4c.

Ah, now I see. There is also Table 16-5 NAND Flash Interface Registers starting with NFCSR at 0x13410050 and ending with TGHH register at 0x13410154.

Quoted 6 lines

Hm. With this we are probably at "go back and start over"...

Either nemc must be separated into two drivers for Static Memory and one for NAND Flash. Or must become able to handle two register ranges.

Or the e-fuse driver must become a part of the nemc driver.

Nothing that bad. I'll make the NEMC driver request only the area it needs, out of the 0x10000 register space.

Then, you can move the efuse node *inside* the nemc node (with proper #address-cells/#size-cells/ranges and "simple-mfd" compatible string) and everything will work.

Quoted 3 lines

Well, another assumption is that there is no NAND driver. AFAIR it was even removed from the kernel because the maintainer did say it is not fixable (if I really remember correctly).

It's still there:
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

What was dropped from the kernel is MLC NAND support in UBI.

Cheers,
-Paul

Quoted 22 lines
Quoted 14 lines

Review

Quoted 13 lines
(quoted diff) +0 -0
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges = <1 0 0x1b000000 0x1000000
 @@ -373,6 +373,21 @@
 		status = "disabled";
 	};
 +	efuse: efuse@134100d0 {
 +		compatible = "ingenic,jz4780-efuse";
 +		reg = <0x134100d0 0x2c>;
 +
 +		clocks = <&cgu JZ4780_CLK_AHB2>;
 +		clock-names = "ahb2";
Quoted 2 lines

As explained in my response to the other patch, 'clock-names' can
go away.

Yes.

BR,
Nikolaus

author
#14 lore raw

PATCH v6 6/6 MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address

In reply to H. Nikolaus Schaller

There is a unique MAC address programmed into the eFuses of the JZ4780 chip in the CI20 factory. By using this for initializing the DM9000 Ethernet controller, every CI20 board has an individual - but stable - MAC address and DHCP can assign stable IP addresses.

Signed-off-by H. Nikolaus Schaller <[email protected]>
---
 arch/mips/boot/dts/ingenic/ci20.dts | 3 +++
 1 file changed, 3 insertions(+)
arch/mips/boot/dts/ingenic/ci20.dts +3 -0
index 37b93166bf22..6dc1f9eeff00 100644
@@ -355,6 +355,9 @@
 
 		interrupt-parent = <&gpe>;
 		interrupts = <19 4>;
+
+		nvmem-cells = <&eth0_addr>;
+		nvmem-cell-names = "mac-address";
 	};
 };
Signature · 1 line
2.23.0