ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)

Am 24.04.2020 um 22:34 schrieb H. Nikolaus Schaller <[email protected]>:

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.

With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).

The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does

all clock, reset and power-management through registers outside of the sgx register block.

Therefore all these properties are optional.

Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
.../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++

1 file changed, 150 insertions(+)

create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +11 -0

new file mode 100644
index 000000000000..33a9c4c6e784
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+  - H. Nikolaus Schaller <[email protected]>
+

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +129 -0

+
+properties:
+  $nodename:
+    pattern: '^gpu@[a-f0-9]+$'
+  compatible:
+    oneOf:
+      - description: SGX530-121 based SoC
+        items:
+          - enum:
+            - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar
+          - const: img,sgx530-121
+          - const: img,sgx530
+
+      - description: SGX530-125 based SoC
+        items:
+          - enum:
+            - ti,am3352-sgx530-125 # BeagleBone Black
+            - ti,am3517-sgx530-125
+            - ti,am4-sgx530-125
+            - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar
+            - ti,ti81xx-sgx530-125
+          - const: ti,omap3-sgx530-125
+          - const: img,sgx530-125
+          - const: img,sgx530
+
+      - description: SGX535-116 based SoC
+        items:
+          - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+          - const: img,sgx535-116
+          - const: img,sgx535
+
+      - description: SGX540-116 based SoC
+        items:
+          - const: intel,medfield-gma-sgx540 # Atom Z24xx
+          - const: img,sgx540-116
+          - const: img,sgx540
+
+      - description: SGX540-120 based SoC
+        items:
+          - enum:
+            - samsung,s5pv210-sgx540-120
+            - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
+          - const: img,sgx540-120
+          - const: img,sgx540
+
+      - description: SGX540-130 based SoC
+        items:
+          - enum:
+            - ingenic,jz4780-sgx540-130 # CI20
+          - const: img,sgx540-130
+          - const: img,sgx540
+
+      - description: SGX544-112 based SoC
+        items:
+          - const: ti,omap4470-sgx544-112
+          - const: img,sgx544-112
+          - const: img,sgx544
+
+      - description: SGX544-115 based SoC
+        items:
+          - enum:
+            - allwinner,sun8i-a31-sgx544-115
+            - allwinner,sun8i-a31s-sgx544-115
+            - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T) and similar
+          - const: img,sgx544-115
+          - const: img,sgx544
+
+      - description: SGX544-116 based SoC
+        items:
+          - enum:
+            - ti,dra7-sgx544-116 # DRA7
+            - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
+          - const: img,sgx544-116
+          - const: img,sgx544
+
+      - description: SGX545 based SoC
+        items:
+          - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
+          - const: img,sgx545-116
+          - const: img,sgx545
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    maxItems: 1
+    items:
+      - const: sgx
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    maxItems: 4
+    items:
+      - const: core
+      - const: sys
+      - const: mem
+      - const: hyd
+
+  sgx-supply: true
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu: gpu@fe00 {
+      compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544";
+      reg = <0xfe00 0x200>;
+      interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+    };
+
+...

Signature · 1 line

2.25.1

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.

With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).

The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block.

Therefore all these properties are optional.

Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 .../devicetree/bindings/gpu/img,pvrsgx.yaml   | 150 
++++++++++++++++++
 1 file changed, 150 insertions(+)
 create mode 100644 

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +13 -0

new file mode 100644
index 000000000000..33a9c4c6e784
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+  - H. Nikolaus Schaller <[email protected]>
+
+description: |+
+  This binding describes the Imagination SGX5 series of 3D 

accelerators which
+ are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +3 -0

+  Allwinner A83, and Intel Poulsbo and CedarView and more.
+
+  For an extensive list see: 

https://en.wikipedia.org/wiki/PowerVR#Implementations

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +2 -0

+
+  The SGX node is usually a child node of some DT node belonging to 

the SoC
+ which handles clocks, reset and general address space mapping of the SGX

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +11 -0

+  register area. If not, an optional clock can be specified here.
+
+properties:
+  $nodename:
+    pattern: '^gpu@[a-f0-9]+$'
+  compatible:
+    oneOf:
+      - description: SGX530-121 based SoC
+        items:
+          - enum:
+            - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 

600MHz and similar

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +10 -0

+          - const: img,sgx530-121
+          - const: img,sgx530
+
+      - description: SGX530-125 based SoC
+        items:
+          - enum:
+            - ti,am3352-sgx530-125 # BeagleBone Black
+            - ti,am3517-sgx530-125
+            - ti,am4-sgx530-125
+            - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, 

OpenPandora 1GHz and similar

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +22 -0

+            - ti,ti81xx-sgx530-125
+          - const: ti,omap3-sgx530-125
+          - const: img,sgx530-125
+          - const: img,sgx530
+
+      - description: SGX535-116 based SoC
+        items:
+          - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+          - const: img,sgx535-116
+          - const: img,sgx535
+
+      - description: SGX540-116 based SoC
+        items:
+          - const: intel,medfield-gma-sgx540 # Atom Z24xx
+          - const: img,sgx540-116
+          - const: img,sgx540
+
+      - description: SGX540-120 based SoC
+        items:
+          - enum:
+            - samsung,s5pv210-sgx540-120
+            - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and 

similar

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +22 -0

+          - const: img,sgx540-120
+          - const: img,sgx540
+
+      - description: SGX540-130 based SoC
+        items:
+          - enum:
+            - ingenic,jz4780-sgx540-130 # CI20
+          - const: img,sgx540-130
+          - const: img,sgx540
+
+      - description: SGX544-112 based SoC
+        items:
+          - const: ti,omap4470-sgx544-112
+          - const: img,sgx544-112
+          - const: img,sgx544
+
+      - description: SGX544-115 based SoC
+        items:
+          - enum:
+            - allwinner,sun8i-a31-sgx544-115
+            - allwinner,sun8i-a31s-sgx544-115
+            - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 

(Allwinner A83T) and similar

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +8 -0

+          - const: img,sgx544-115
+          - const: img,sgx544
+
+      - description: SGX544-116 based SoC
+        items:
+          - enum:
+            - ti,dra7-sgx544-116 # DRA7
+            - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and 

similar

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +33 -0

+          - const: img,sgx544-116
+          - const: img,sgx544
+
+      - description: SGX545 based SoC
+        items:
+          - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
+          - const: img,sgx545-116
+          - const: img,sgx545
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    maxItems: 1
+    items:
+      - const: sgx
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    maxItems: 4
+    items:
+      - const: core
+      - const: sys
+      - const: mem
+      - const: hyd
+
+  sgx-supply: true
+

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +9 -0

+
+additionalProperties: false
+
+examples:
+  - |+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu: gpu@fe00 {
+      compatible = "ti,omap5-sgx544-116", "img,sgx544-116", 

"img,sgx544";

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +5 -1

+      reg = <0xfe00 0x200>;
+      interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+    };
+
+...
--

2.25.1

Am 26.04.2020 um 15:11 schrieb Paul Cercueil <[email protected]>:

Hi Nikolaus,

Quoted 153 lines · H. Nikolaus Schaller

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.
With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).
The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block.
Therefore all these properties are optional.
Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
.../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++

1 file changed, 150 insertions(+)

create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +130 -0

new file mode 100644
index 000000000000..33a9c4c6e784
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+  - H. Nikolaus Schaller <[email protected]>
+
+description: |+
+  This binding describes the Imagination SGX5 series of 3D accelerators which
+  are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
+  Allwinner A83, and Intel Poulsbo and CedarView and more.
+
+  For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations
+
+  The SGX node is usually a child node of some DT node belonging to the SoC
+  which handles clocks, reset and general address space mapping of the SGX
+  register area. If not, an optional clock can be specified here.
+
+properties:
+  $nodename:
+    pattern: '^gpu@[a-f0-9]+$'
+  compatible:
+    oneOf:
+      - description: SGX530-121 based SoC
+        items:
+          - enum:
+            - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar
+          - const: img,sgx530-121
+          - const: img,sgx530
+
+      - description: SGX530-125 based SoC
+        items:
+          - enum:
+            - ti,am3352-sgx530-125 # BeagleBone Black
+            - ti,am3517-sgx530-125
+            - ti,am4-sgx530-125
+            - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar
+            - ti,ti81xx-sgx530-125
+          - const: ti,omap3-sgx530-125
+          - const: img,sgx530-125
+          - const: img,sgx530
+
+      - description: SGX535-116 based SoC
+        items:
+          - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+          - const: img,sgx535-116
+          - const: img,sgx535
+
+      - description: SGX540-116 based SoC
+        items:
+          - const: intel,medfield-gma-sgx540 # Atom Z24xx
+          - const: img,sgx540-116
+          - const: img,sgx540
+
+      - description: SGX540-120 based SoC
+        items:
+          - enum:
+            - samsung,s5pv210-sgx540-120
+            - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
+          - const: img,sgx540-120
+          - const: img,sgx540
+
+      - description: SGX540-130 based SoC
+        items:
+          - enum:
+            - ingenic,jz4780-sgx540-130 # CI20
+          - const: img,sgx540-130
+          - const: img,sgx540
+
+      - description: SGX544-112 based SoC
+        items:
+          - const: ti,omap4470-sgx544-112
+          - const: img,sgx544-112
+          - const: img,sgx544
+
+      - description: SGX544-115 based SoC
+        items:
+          - enum:
+            - allwinner,sun8i-a31-sgx544-115
+            - allwinner,sun8i-a31s-sgx544-115
+            - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T) and similar
+          - const: img,sgx544-115
+          - const: img,sgx544
+
+      - description: SGX544-116 based SoC
+        items:
+          - enum:
+            - ti,dra7-sgx544-116 # DRA7
+            - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
+          - const: img,sgx544-116
+          - const: img,sgx544
+
+      - description: SGX545 based SoC
+        items:
+          - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
+          - const: img,sgx545-116
+          - const: img,sgx545
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    maxItems: 1
+    items:
+      - const: sgx
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    maxItems: 4
+    items:
+      - const: core
+      - const: sys
+      - const: mem
+      - const: hyd
+
+  sgx-supply: true
+
+  power-domains:
+    maxItems: 1
+
+  resets:

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 136

Quoted 6 lines

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +6 -0

+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts

By not making 'clocks' required you make it possible to create broken bindings; according to your schema, a GPU node without a 'clocks' for the JZ4780 would be perfectly valid.

It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others.

See how it's done for instance on Documentation/devicetree/bindings/serial/samsung_uart.yaml.

Hi Paul,

Quoted 180 lines

Am 26.04.2020 um 15:11 schrieb Paul Cercueil <[email protected]>:

Hi Nikolaus,

Quoted 165 lines · H. Nikolaus Schaller

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.
With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).
The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block.
Therefore all these properties are optional.
Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---

 .../devicetree/bindings/gpu/img,pvrsgx.yaml   | 150 
++++++++++++++++++
 1 file changed, 150 insertions(+)
 create mode 100644 

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
new file mode 100644
index 000000000000..33a9c4c6e784
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml @@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+ - H. Nikolaus Schaller <[email protected]>
+
+description: |+
+ This binding describes the Imagination SGX5 series of 3D
accelerators which
+ are found in several different SoC like TI OMAP, Sitara,
Ingenic JZ4780,
+ Allwinner A83, and Intel Poulsbo and CedarView and more. +
+ For an extensive list see:
https://en.wikipedia.org/wiki/PowerVR#Implementations
+
+ The SGX node is usually a child node of some DT node belonging
to the SoC
+ which handles clocks, reset and general address space mapping
of the SGX
+ register area. If not, an optional clock can be specified here. +
+properties:
+ $nodename:
+ pattern: '^gpu@[a-f0-9]+$'
+ compatible:
+ oneOf:
+ - description: SGX530-121 based SoC
+ items:
+ - enum:
+ - ti,omap3-sgx530-121 # BeagleBoard A/B/C,
OpenPandora 600MHz and similar
+ - const: img,sgx530-121
+ - const: img,sgx530
+
+ - description: SGX530-125 based SoC
+ items:
+ - enum:

 +            - ti,am3352-sgx530-125 # BeagleBone Black
 +            - ti,am3517-sgx530-125
 +            - ti,am4-sgx530-125
 +            - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, 
OpenPandora 1GHz and similar
 +            - ti,ti81xx-sgx530-125
 +          - const: ti,omap3-sgx530-125
 +          - const: img,sgx530-125
 +          - const: img,sgx530
 +
 +      - description: SGX535-116 based SoC
 +        items:
 +          - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
 +          - const: img,sgx535-116
 +          - const: img,sgx535
 +
 +      - description: SGX540-116 based SoC
 +        items:
 +          - const: intel,medfield-gma-sgx540 # Atom Z24xx
 +          - const: img,sgx540-116
 +          - const: img,sgx540

+
+ - description: SGX540-120 based SoC
+ items:
+ - enum:
+ - samsung,s5pv210-sgx540-120
+ - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and
similar
+ - const: img,sgx540-120
+ - const: img,sgx540
+
+ - description: SGX540-130 based SoC
+ items:
+ - enum:
+ - ingenic,jz4780-sgx540-130 # CI20
+ - const: img,sgx540-130
+ - const: img,sgx540
+
+ - description: SGX544-112 based SoC
+ items:

 +          - const: ti,omap4470-sgx544-112
 +          - const: img,sgx544-112
 +          - const: img,sgx544
 +
 +      - description: SGX544-115 based SoC
 +        items:
 +          - enum:
 +            - allwinner,sun8i-a31-sgx544-115
 +            - allwinner,sun8i-a31s-sgx544-115
 +            - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 

(Allwinner A83T) and similar
+ - const: img,sgx544-115
+ - const: img,sgx544
+
+ - description: SGX544-116 based SoC
+ items:
+ - enum:
+ - ti,dra7-sgx544-116 # DRA7
+ - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and
similar
+ - const: img,sgx544-116
+ - const: img,sgx544
+
+ - description: SGX545 based SoC
+ items:
+ - const: intel,cedarview-gma3600-sgx545 # Atom N2600,
D2500
+ - const: img,sgx545-116
+ - const: img,sgx545
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ maxItems: 1
+ items:
+ - const: sgx
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ maxItems: 4
+ items:

 +      - const: core
 +      - const: sys
 +      - const: mem
 +      - const: hyd

+
+ sgx-supply: true
+
+ power-domains:
+ maxItems: 1

Quoted 8 lines

+
+ resets:
+ maxItems: 1
+
+required:

 +  - compatible
 +  - reg
 +  - interrupts

Quoted 2 lines

By not making 'clocks' required you make it possible to create
broken bindings; according to your schema, a GPU node without a 'clocks' for the JZ4780 would be perfectly valid.

Yes. But it will never pass a test with real hardware. So it can't be omitted anyways.

On a more general thought, this argument holds for any optional property. So it is not specific to clocks. Since the reg address values are also never specified you can still create broken bindings. Or by connecting the wrong clock. So the ways to create broken bindings are numerous.

I also assume that SGX integrators are not beginners and do you think they need to find out through a make dt_binding_check dtbs_check that they should define a clock? based on *assumptions* we do without having access to all systems?

IMHO the bindings documentation is a documentation. So it needs to be helpful but not perfect. Formalizing all corner cases in a bindings document (just because we can since .yaml was introduced) is IMHO overkill.

In times before the introduction of more formal .yaml I think we would not even have considered this for a comment in the bindings.txt.

Quoted 2 lines

It's possible to forbid the presence of the 'clocks' property on
some implementations, and require it on others.

To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture.

This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more.

Quoted 2 lines

See how it's done for instance on
Documentation/devicetree/bindings/serial/samsung_uart.yaml.

Yes I know the design pattern, but I wonder if such a move makes the whole thing even less maintainable.

Assume we have finished DTS for some SoC. Then these DTS have been tested on real hardware and are working. Clocks are there where needed and missing where not. We may now forbid or not forbid them for some implementations in the bindings.yaml but the result of dtbs_check won't change! Because they are tested and working and the bindings.yaml has been adapted to the result. So we have just duplicated something for no practical benefit.

Next, assume there is coming support for more and more new SoC. Then, developers not only have to figure out which clocks they need in the DTS but they also have to add a patch to the implementation specific part of the bindings.yaml to clearly define exactly the same what they already have written into their .dts (the clocks are either there for the of_node or they are not). So again the rules are for no benefit, since a new SoC is introduced exactly once. And tested if it works. And if it is there, it will stay as it is. It is just work for maintainers to review that patch as well.

It boils down to the question if we need to formalize the rule how a working DTS was derived. Or just have a working DTS and not formalize everything.

So IMHO carrying along such a detail (forbid clocks on some architectures) is nice to have (and fun to learn the .yaml thing) but not of benefit for anyone. Not for the DTS developer nor for the maintainers nor for the users of a Linux kernel. "Keep it simple" is always a good rule for maintainability.

In summary I don't see a good reason to follow this in v8. But you could add it by a separate patch later if the DTS have been reviewed and agreed.

BR and thanks,
Nikolaus

Am 03.05.2020 um 14:52 schrieb Paul Cercueil <[email protected]>:

Quoted 3 lines

Quoted 1 line

It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others.

To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture.
This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more.

As we said before, the number of clocks is a property of the GPU and *not* its integration into the SoC.

So you would *not* have a number of clocks between 0 and 4. You get either 0, or 4, depending on whether or not you have a wrapper.

Quoted 6 lines

Quoted 3 lines

See how it's done for instance on Documentation/devicetree/bindings/serial/samsung_uart.yaml.

Yes I know the design pattern, but I wonder if such a move makes the whole thing even less maintainable.
Assume we have finished DTS for some SoC. Then these DTS have been tested on real hardware and are working. Clocks are there where needed and missing where not. We may now forbid or not forbid them for some implementations in the bindings.yaml but the result of dtbs_check won't change! Because they are tested and working and the bindings.yaml has been adapted to the result. So we have just duplicated something for no practical benefit.
Next, assume there is coming support for more and more new SoC. Then, developers not only have to figure out which clocks they need in the DTS but they also have to add a patch to the implementation specific part of the bindings.yaml to clearly define exactly the same what they already have written into their .dts (the clocks are either there for the of_node or they are not). So again the rules are for no benefit, since a new SoC is introduced exactly once. And tested if it works. And if it is there, it will stay as it is. It is just work for maintainers to review that patch as well.

If you add support for a new SoC, you'd still need to modify the binding to add the compatible string. So the argument of "more work" is moot.

Hi Paul,

Quoted 9 lines

Am 03.05.2020 um 14:52 schrieb Paul Cercueil <[email protected]>:

Quoted 6 lines

Quoted 2 lines

It's possible to forbid the presence of the 'clocks' property on
some implementations, and require it on others.

To be precise we have to specify the exact number of clocks
(between 0 and 4) for every architecture.
This also contradicts my dream to get rid of the architecture
specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more.

Quoted 2 lines

As we said before, the number of clocks is a property of the GPU
and *not* its integration into the SoC.

Well, it is a not very well documented property of the GPU. We have no data sheet of the standalone GPU. Only several SoC data sheets which give some indications.

It appears as if some sgx5xx versions have 3 clocks and some have 4. So you are right, the number of clocks depends on the sgx5xx version and that could be made dependent in the bindings (if necessary).

Quoted 3 lines

So you would *not* have a number of clocks between 0 and 4. You get
either 0, or 4, depending on whether or not you have a wrapper.

I think this is contradicting your previous sentence. If the number of clocks is a property of the GPU and not the integration it must also not depend on whether there is a wrapper. I.e. it must be a constant for any type of integration.

The really correct variant would be to always make the SoC integration (wrapper) a separate subsystem (because it is never part of the SGX core but some interface bus) and clock provider and connect it explicitly to the clock inputs.

To be clear: I am not at all against describing the clocks. I just doubt that the time we invest into discussing on this level of detail and adding conditional clock requirements is worth the result. IMHO the bindings and .dts do not become better by describing them in more detail than just "optional". It just takes our time from contributing to other subsystems.

Quoted 11 lines

Quoted 10 lines

Quoted 4 lines

See how it's done for instance on
Documentation/devicetree/bindings/serial/samsung_uart.yaml.

Yes I know the design pattern, but I wonder if such a move makes
the whole thing even less maintainable.
Assume we have finished DTS for some SoC. Then these DTS have been
tested on real hardware and are working. Clocks are there where needed and missing where not. We may now forbid or not forbid them for some implementations in the bindings.yaml but the result of dtbs_check won't change! Because they are tested and working and the bindings.yaml has been adapted to the result. So we have just duplicated something for no practical benefit.
Next, assume there is coming support for more and more new SoC.
Then, developers not only have to figure out which clocks they need in the DTS but they also have to add a patch to the implementation specific part of the bindings.yaml to clearly define exactly the same what they already have written into their .dts (the clocks are either there for the of_node or they are not). So again the rules are for no benefit, since a new SoC is introduced exactly once. And tested if it works. And if it is there, it will stay as it is. It is just work for maintainers to review that patch as well.

Quoted 2 lines

If you add support for a new SoC, you'd still need to modify the
binding to add the compatible string. So the argument of "more work" is moot.

Agreed, I forgot this aspect. Nevertheless, it is easier to review a new compatible string than a new clock number rule (question: how do you practically review this? By looking if it does match the DTS?).

We have to add the compatible string as long as we need to have the SoC name in the compatible string (which as said is my dream to get rid of in far future). If we could get rid of it, there won't be a change any more. By just taking "img,sgx544" into a new SoC. The change would be moved into SoC specific wrappers. In such an ideal world, we would explicitly describe the wrappers as separate DT nodes. Even if they have no explicit driver (e.g. by some simple-pm-bus).

PRCM,bus,
Processor <<---->> Wrapper <<----->> SGX

ti,...             ti,sysc           img,sgx530
img,...            simple-bus        img,sgx540
samsung,...        ...               img,sgx544
other,             other,gpu-wrapper img,...

But this IMHO correct proposal was already rejected.

So at the moment we are circling around several proposals because none can fulfill all requirements.

Therefore my attempt to solve the gordian knot is to make clocks generally optional. This keeps the bindings simple but not generally wrong. And since the DTS are not only tested against bindings.yaml but on real hardware, the omission to enforce a specific number of clocks doesn't harm anyone. As said it is impossible to get the SGX running without defining the correct clocks (whether they are enforced by bindings.yaml or not).

You have a new SoC with a SGX, and you only need to enable one clock to get it to work. So you create a devicetree node which receives only one clock.

Turns out, that the bootloader was enabling the other 3 clocks, and since the last release, it doesn't anymore. You're left with having to support a broken devicetree.

That's the kind of problem that can be easily avoided by enforcing the number of clocks that have to be provided.

Am 03.05.2020 um 17:01 schrieb Tony Lindgren <[email protected]>:

Quoted 9 lines · Paul Cercueil

You have a new SoC with a SGX, and you only need to enable one clock to get it to work. So you create a devicetree node which receives only one clock.

Turns out, that the bootloader was enabling the other 3 clocks, and since the last release, it doesn't anymore. You're left with having to support a broken devicetree.

That's the kind of problem that can be easily avoided by enforcing the number of clocks that have to be provided.

The number of clocks depends on how it's wired for the SoC.

On omaps, there's are no controls for additinoal SGX clocks. Sure some of the clocks may be routed to multple places internally by the wrapper module. But we have no control over that.

If we wanted to specify just the "fck" clock on omaps, then we can do it with something like this:

allOf:
- if:
properites:
compatible:
enum:
- "ti,omap4-sgx544-112"
- "ti,omap5-sgx544-116"
- "ti,dra7-sgx544-116"
then:
properties:
clocks:
minItems: 1
maxItems: 1

clock-names:
const: fck

required:
- clocks
- clock-names

Am 03.05.2020 um 16:18 schrieb Paul Cercueil <[email protected]>:

Quoted 1 line · H. Nikolaus Schaller

Hi Paul,

Quoted 6 lines

Quoted 5 lines

Am 03.05.2020 um 14:52 schrieb Paul Cercueil <[email protected]>:

Quoted 3 lines

Quoted 1 line

It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others.

To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture.
This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more.

As we said before, the number of clocks is a property of the GPU and *not* its integration into the SoC.

Well, it is a not very well documented property of the GPU. We have no data sheet of the standalone GPU. Only several SoC data sheets which give some indications.

Maybe we can nicely ask them?

I expect Paul Burton to have some contacts at ImgTec. Asking for a doc would be too much, but maybe they can help a bit with the DT bindings.

Quoted 4 lines

It appears as if some sgx5xx versions have 3 clocks and some have 4. So you are right, the number of clocks depends on the sgx5xx version and that could be made dependent in the bindings (if necessary).

Quoted 1 line

So you would *not* have a number of clocks between 0 and 4. You get either 0, or 4, depending on whether or not you have a wrapper.

I think this is contradicting your previous sentence. If the number of clocks is a property of the GPU and not the integration it must also not depend on whether there is a wrapper. I.e. it must be a constant for any type of integration.

Well, I expected all SGX versions to have 4 clocks.

If some SGX versions have 3 clocks, and others have 4 clocks, it's still OK as long as the number of clocks is enforced, so that all implementations of a given SGX core will have to use the same number of clocks.

Quoted 1 line

The really correct variant would be to always make the SoC integration (wrapper) a separate subsystem (because it is never part of the SGX core but some interface bus) and clock provider and connect it explicitly to the clock inputs.

About the wrapper... I don't really know how it's done there. But you could very well pass all clocks unconditionally to the SGX node, even if it's inside a wrapper. The wrapper itself probably needs only one clock, the one that allows it to access its registers.

Quoted 1 line

To be clear: I am not at all against describing the clocks. I just doubt that the time we invest into discussing on this level of detail and adding conditional clock requirements is worth the result. IMHO the bindings and .dts do not become better by describing them in more detail than just "optional". It just takes our time from contributing to other subsystems.

You have a new SoC with a SGX, and you only need to enable one clock to get it to work. So you create a devicetree node which receives only one clock.

Turns out, that the bootloader was enabling the other 3 clocks,

and since the last release, it doesn't anymore. You're left with having to support a broken devicetree.

That's the kind of problem that can be easily avoided by enforcing the number of clocks that have to be provided.

Quoted 1 line

Quoted 1 line

Quoted 1 line

Quoted 1 line

See how it's done for instance on Documentation/devicetree/bindings/serial/samsung_uart.yaml.

Quoted 6 lines

Quoted 4 lines

Quoted 3 lines

Yes I know the design pattern, but I wonder if such a move makes the whole thing even less maintainable.
Assume we have finished DTS for some SoC. Then these DTS have been tested on real hardware and are working. Clocks are there where needed and missing where not. We may now forbid or not forbid them for some implementations in the bindings.yaml but the result of dtbs_check won't change! Because they are tested and working and the bindings.yaml has been adapted to the result. So we have just duplicated something for no practical benefit.
Next, assume there is coming support for more and more new SoC. Then, developers not only have to figure out which clocks they need in the DTS but they also have to add a patch to the implementation specific part of the bindings.yaml to clearly define exactly the same what they already have written into their .dts (the clocks are either there for the of_node or they are not). So again the rules are for no benefit, since a new SoC is introduced exactly once. And tested if it works. And if it is there, it will stay as it is. It is just work for maintainers to review that patch as well.

If you add support for a new SoC, you'd still need to modify the binding to add the compatible string. So the argument of "more work" is moot.

Agreed, I forgot this aspect. Nevertheless, it is easier to review a new compatible string than a new clock number rule (question: how do you practically review this? By looking if it does match the DTS?).
We have to add the compatible string as long as we need to have the SoC name in the compatible string (which as said is my dream to get rid of in far future). If we could get rid of it, there won't be a change any more. By just taking "img,sgx544" into a new SoC. The change would be moved into SoC specific wrappers. In such an ideal world, we would explicitly describe the wrappers as separate DT nodes. Even if they have no explicit driver (e.g. by some simple-pm-bus).

What's wrong with having the SoC name in the compatible string?

You cannot use just a "img,sgx544" compatible string, as then you would assume that the same SGX version in (e.g.) an Ingenic or a Omap SoC is the exact same. This may actually be true.

But the moment you discover even a tiny thing that needs to be handled differently, you wouldn't have the possibility to do so.

Quoted 10 lines

PRCM,bus,
Processor <<---->> Wrapper <<----->> SGX

ti,...             ti,sysc           img,sgx530
img,...            simple-bus        img,sgx540
samsung,...        ...               img,sgx544
other,             other,gpu-wrapper img,...

But this IMHO correct proposal was already rejected.
So at the moment we are circling around several proposals because none can fulfill all requirements.
Therefore my attempt to solve the gordian knot is to make clocks generally optional. This keeps the bindings simple but not generally wrong. And since the DTS are not only tested against bindings.yaml but on real hardware, the omission to enforce a specific number of clocks doesn't harm anyone. As said it is impossible to get the SGX running without defining the correct clocks (whether they are enforced by bindings.yaml or not).

That's what I tried to explain above. You'd be able to get the SGX to work without a single clock in devicetree. That doesn't mean it should be allowed.

Cheers,
-Paul

Am 03.05.2020 um 18:41 schrieb H. Nikolaus Schaller <[email protected]>:

Hi Paul and Paul,

Quoted 6 lines

Am 03.05.2020 um 16:18 schrieb Paul Cercueil <[email protected]>:

Quoted 1 line · H. Nikolaus Schaller

Hi Paul,

Quoted 8 lines

Quoted 6 lines

Quoted 5 lines

Am 03.05.2020 um 14:52 schrieb Paul Cercueil <[email protected]>:

Quoted 3 lines

Quoted 1 line

It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others.

To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture.
This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more.

As we said before, the number of clocks is a property of the GPU and *not* its integration into the SoC.

Well, it is a not very well documented property of the GPU. We have no data sheet of the standalone GPU. Only several SoC data sheets which give some indications.

Maybe we can nicely ask them?

There is some (old) answer here:

https://github.com/MIPS/CI20_linux/blob/ci20-v3.18/arch/mips/boot/dts/jz4780.dtsi#L63

Quoted 1 line

I expect Paul Burton to have some contacts at ImgTec. Asking for a doc would be too much, but maybe they can help a bit with the DT bindings.

Good idea! It is definitively worth to try. Therefore I have moved him from CC: to To:

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.

With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).

The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block.

Therefore all these properties are optional.

Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
  .../devicetree/bindings/gpu/img,pvrsgx.yaml   | 150 ++++++++++++++++++
  1 file changed, 150 insertions(+)

create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +74 -0

new file mode 100644
index 000000000000..33a9c4c6e784
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+  - H. Nikolaus Schaller <[email protected]>
+
+description: |+
+  This binding describes the Imagination SGX5 series of 3D accelerators which
+  are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
+  Allwinner A83, and Intel Poulsbo and CedarView and more.
+
+  For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations
+
+  The SGX node is usually a child node of some DT node belonging to the SoC
+  which handles clocks, reset and general address space mapping of the SGX
+  register area. If not, an optional clock can be specified here.
+
+properties:
+  $nodename:
+    pattern: '^gpu@[a-f0-9]+$'
+  compatible:
+    oneOf:
+      - description: SGX530-121 based SoC
+        items:
+          - enum:
+            - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar
+          - const: img,sgx530-121
+          - const: img,sgx530
+
+      - description: SGX530-125 based SoC
+        items:
+          - enum:
+            - ti,am3352-sgx530-125 # BeagleBone Black
+            - ti,am3517-sgx530-125
+            - ti,am4-sgx530-125
+            - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar
+            - ti,ti81xx-sgx530-125
+          - const: ti,omap3-sgx530-125
+          - const: img,sgx530-125
+          - const: img,sgx530
+
+      - description: SGX535-116 based SoC
+        items:
+          - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+          - const: img,sgx535-116
+          - const: img,sgx535
+
+      - description: SGX540-116 based SoC
+        items:
+          - const: intel,medfield-gma-sgx540 # Atom Z24xx
+          - const: img,sgx540-116
+          - const: img,sgx540
+
+      - description: SGX540-120 based SoC
+        items:
+          - enum:
+            - samsung,s5pv210-sgx540-120
+            - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
+          - const: img,sgx540-120
+          - const: img,sgx540
+
+      - description: SGX540-130 based SoC
+        items:
+          - enum:
+            - ingenic,jz4780-sgx540-130 # CI20
+          - const: img,sgx540-130
+          - const: img,sgx540
+
+      - description: SGX544-112 based SoC

Am 26.04.2020 um 21:36 schrieb Philipp Rossak <[email protected]>:

Hi Nikolaus,

Quoted 31 lines · H. Nikolaus Schaller

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.
With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).
The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block.
Therefore all these properties are optional.
Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 .../devicetree/bindings/gpu/img,pvrsgx.yaml   | 150 ++++++++++++++++++
 1 file changed, 150 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +8 -0

new file mode 100644
index 000000000000..33a9c4c6e784
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 84

Quoted 11 lines

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +11 -0

+      - description: SGX544-112 based SoC
+        items:
+          - const: ti,omap4470-sgx544-112
+          - const: img,sgx544-112
+          - const: img,sgx544
+
+      - description: SGX544-115 based SoC
+        items:
+          - enum:
+            - allwinner,sun8i-a31-sgx544-115
+            - allwinner,sun8i-a31s-sgx544-115

those two bindings are wrong.
It should be allwinner,sun6i-a31-sgx544-115 and allwinner,sun6i-a31s-sgx544-115. I did a copy paste error in the patches that I provided for this series.

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.

With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).

The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block.

Therefore all these properties are optional.

Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 .../devicetree/bindings/gpu/img,pvrsgx.yaml   | 150 ++++++++++++++++++
 1 file changed, 150 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +21 -0

new file mode 100644
index 000000000000..33a9c4c6e784
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+  - H. Nikolaus Schaller <[email protected]>
+
+description: |+
+  This binding describes the Imagination SGX5 series of 3D accelerators which
+  are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
+  Allwinner A83, and Intel Poulsbo and CedarView and more.
+
+  For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations
+
+  The SGX node is usually a child node of some DT node belonging to the SoC
+  which handles clocks, reset and general address space mapping of the SGX
+  register area. If not, an optional clock can be specified here.

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +119 -0

+          - const: img,sgx530-121
+          - const: img,sgx530
+
+      - description: SGX530-125 based SoC
+        items:
+          - enum:
+            - ti,am3352-sgx530-125 # BeagleBone Black
+            - ti,am3517-sgx530-125
+            - ti,am4-sgx530-125
+            - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar
+            - ti,ti81xx-sgx530-125
+          - const: ti,omap3-sgx530-125
+          - const: img,sgx530-125
+          - const: img,sgx530
+
+      - description: SGX535-116 based SoC
+        items:
+          - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+          - const: img,sgx535-116
+          - const: img,sgx535
+
+      - description: SGX540-116 based SoC
+        items:
+          - const: intel,medfield-gma-sgx540 # Atom Z24xx
+          - const: img,sgx540-116
+          - const: img,sgx540
+
+      - description: SGX540-120 based SoC
+        items:
+          - enum:
+            - samsung,s5pv210-sgx540-120
+            - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
+          - const: img,sgx540-120
+          - const: img,sgx540
+
+      - description: SGX540-130 based SoC
+        items:
+          - enum:
+            - ingenic,jz4780-sgx540-130 # CI20
+          - const: img,sgx540-130
+          - const: img,sgx540
+
+      - description: SGX544-112 based SoC
+        items:
+          - const: ti,omap4470-sgx544-112
+          - const: img,sgx544-112
+          - const: img,sgx544
+
+      - description: SGX544-115 based SoC
+        items:
+          - enum:
+            - allwinner,sun8i-a31-sgx544-115
+            - allwinner,sun8i-a31s-sgx544-115
+            - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T) and similar
+          - const: img,sgx544-115
+          - const: img,sgx544
+
+      - description: SGX544-116 based SoC
+        items:
+          - enum:
+            - ti,dra7-sgx544-116 # DRA7
+            - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
+          - const: img,sgx544-116
+          - const: img,sgx544
+
+      - description: SGX545 based SoC
+        items:
+          - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
+          - const: img,sgx545-116
+          - const: img,sgx545
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    maxItems: 1
+    items:
+      - const: sgx
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    maxItems: 4
+    items:
+      - const: core
+      - const: sys
+      - const: mem
+      - const: hyd
+
+  sgx-supply: true
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu: gpu@fe00 {
+      compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544";
+      reg = <0xfe00 0x200>;
+      interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+    };
+
+...

Signature · 1 line

2.25.1

Am 05.05.2020 um 17:53 schrieb Rob Herring <[email protected]>:

Quoted 21 lines · H. Nikolaus Schaller

The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others.

With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt).

The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block.

Therefore all these properties are optional.

Tested by make dt_binding_check

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
.../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++

1 file changed, 150 insertions(+)

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml line 31

Quoted 5 lines

Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file +5 -0

+    oneOf:
+      - description: SGX530-121 based SoC
+        items:
+          - enum:
+            - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar

Should be indented 2 more here and elsewhere where you have a list under a list.

Add SGX GPU node with interrupt. Tested on PandaBoard ES.

Since omap4420/30/60 and omap4470 come with different SGX variants we need to introduce a new omap4470.dtsi. If an omap4470 board does not want to use SGX it is no problem to still include omap4460.dtsi.

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi   | 11 ++++++-----
 arch/arm/boot/dts/omap4470.dts | 15 +++++++++++++++
 2 files changed, 21 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap4470.dts

arch/arm/boot/dts/omap4.dtsi +6 -5

index 763bdea8c829..15ff3d7146af 100644
@@ -389,7 +389,7 @@ abb_iva: regulator-abb-iva {
 			status = "disabled";
 		};
 
-		target-module@56000000 {
+		sgx_module: target-module@56000000 {
 			compatible = "ti,sysc-omap4", "ti,sysc";
 			reg = <0x5600fe00 0x4>,
 			      <0x5600fe10 0x4>;

@@ -408,10 +408,11 @@ target-module@56000000 {
 			#size-cells = <1>;
 			ranges = <0 0x56000000 0x2000000>;
 
-			/*
-			 * Closed source PowerVR driver, no child device
-			 * binding or driver in mainline
-			 */
+			gpu: gpu@0 {
+				compatible = "ti,omap4-sgx540-120", "img,sgx540-120", 
 "img,sgx540";
+				reg = <0x0 0x2000000>;	/* 32MB */
+				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			};
 		};
 

arch/arm/boot/dts/omap4.dtsi +0 -0

 		/*

arch/arm/boot/dts/omap4470.dts new file +5 -0

new file mode 100644
index 000000000000..f29c581300bf
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4470 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - 

http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */

arch/arm/boot/dts/omap4470.dts new file +1 -0

+	compatible = "ti,omap4470-sgx544-112", "img,sgx544-112", 

"img,sgx544";
+};
--
2.25.1

Am 26.04.2020 um 14:50 schrieb Paul Cercueil <[email protected]>:

Hi Nikolaus,

Quoted 34 lines · H. Nikolaus Schaller

Add SGX GPU node with interrupt. Tested on PandaBoard ES. Since omap4420/30/60 and omap4470 come with different SGX variants we need to introduce a new omap4470.dtsi. If an omap4470 board does not want to use SGX it is no problem to still include omap4460.dtsi.

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
arch/arm/boot/dts/omap4.dtsi | 11 ++++++-----
arch/arm/boot/dts/omap4470.dts | 15 +++++++++++++++

2 files changed, 21 insertions(+), 5 deletions(-)

create mode 100644 arch/arm/boot/dts/omap4470.dts

arch/arm/boot/dts/omap4.dtsi +5 -5

index 763bdea8c829..15ff3d7146af 100644
@@ -389,7 +389,7 @@ abb_iva: regulator-abb-iva {
 			status = "disabled";
 		};
-		target-module@56000000 {
+		sgx_module: target-module@56000000 {
 			compatible = "ti,sysc-omap4", "ti,sysc";
 			reg = <0x5600fe00 0x4>,
 			      <0x5600fe10 0x4>;

@@ -408,10 +408,11 @@ target-module@56000000 {
 			#size-cells = <1>;
 			ranges = <0 0x56000000 0x2000000>;
-			/*
-			 * Closed source PowerVR driver, no child device
-			 * binding or driver in mainline
-			 */
+			gpu: gpu@0 {
+				compatible = "ti,omap4-sgx540-120", "img,sgx540-120", "img,sgx540";
+				reg = <0x0 0x2000000>;	/* 32MB */
+				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/omap4470.dts

Quoted 8 lines

arch/arm/boot/dts/omap4.dtsi +1 -0

+			};
 		};
 		/*

arch/arm/boot/dts/omap4470.dts new file +0 -0

new file mode 100644
index 000000000000..f29c581300bf

Quoted 8 lines

arch/arm/boot/dts/omap4470.dts new file +7 -0

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4470 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License

arch/arm/boot/dts/omap4470.dts line 13

Quoted 6 lines

arch/arm/boot/dts/omap4470.dts new file +6 -0

+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include "omap4460.dtsi"
+
+&sgx {

Does this even compile?

The node's handle is named sgx_module, not sgx.

From: Jonathan Bakker <[email protected]>

All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.

There is no external regulator for it so it can be enabled by default.

Signed-off-by Jonathan Bakker <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/boot/dts/s5pv210.dtsi +1 -0

index 2ad642f51fd9..abbdda205c1b 100644
@@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 {
 			#interrupt-cells = <1>;
 		};
 
+		gpu: gpu@f3000000 {

arch/arm/boot/dts/s5pv210.dtsi +2 -1

+		};
+
 		fimd: fimd@f8000000 {
 			compatible = "samsung,s5pv210-fimd";
 			interrupt-parent = <&vic2>;
--

2.25.1

Quoted 21 lines · H. Nikolaus Schaller

From: Jonathan Bakker <[email protected]>

All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.

There is no external regulator for it so it can be enabled by default.

Signed-off-by Jonathan Bakker <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++

 1 file changed, 13 insertions(+)

arch/arm/boot/dts/s5pv210.dtsi +1 -0

index 2ad642f51fd9..abbdda205c1b 100644
@@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 {
              #interrupt-cells = <1>;
          };
 
+        gpu: gpu@f3000000 {

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 525

Quoted 10 lines

arch/arm/boot/dts/s5pv210.dtsi +10 -0

+            compatible = "samsung,s5pv210-sgx540-120";
+            reg = <0xf3000000 0x10000>;
+            interrupt-parent = <&vic2>;
+            interrupts = <10>;
+            clock-names = "core";
+            clocks = <&clocks CLK_G3D>;
+
+            assigned-clocks = <&clocks MOUT_G3D>, <&clocks DOUT_G3D>;
+            assigned-clock-rates = <0>, <66700000>;
+            assigned-clock-parents = <&clocks MOUT_MPLL>;

What are these clocks for, and why are they reparented / reclocked?

Shouldn't they be passed to 'clocks' as well?

-Paul

Quoted 8 lines

arch/arm/boot/dts/s5pv210.dtsi +2 -0

+        };
+
          fimd: fimd@f8000000 {
              compatible = "samsung,s5pv210-fimd";
              interrupt-parent = <&vic2>;

Signature · 1 line

2.25.1

Hi Paul,

Quoted 23 lines · Paul Cercueil

Quoted 20 lines · H. Nikolaus Schaller

From: Jonathan Bakker <[email protected]>

All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.

There is no external regulator for it so it can be enabled by default.

Signed-off-by Jonathan Bakker <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++

 1 file changed, 13 insertions(+)

arch/arm/boot/dts/s5pv210.dtsi +0 -0

index 2ad642f51fd9..abbdda205c1b 100644
@@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 {
              #interrupt-cells = <1>;
          };
 

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 516

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi +2 -0

+        gpu: gpu@f3000000 {
+            compatible = "samsung,s5pv210-sgx540-120";

Quoted 10 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 525

Quoted 9 lines

arch/arm/boot/dts/s5pv210.dtsi +9 -0

+            reg = <0xf3000000 0x10000>;
+            interrupt-parent = <&vic2>;
+            interrupts = <10>;
+            clock-names = "core";
+            clocks = <&clocks CLK_G3D>;
+
+            assigned-clocks = <&clocks MOUT_G3D>, <&clocks DOUT_G3D>;
+            assigned-clock-rates = <0>, <66700000>;
+            assigned-clock-parents = <&clocks MOUT_MPLL>;

Quoted 6 lines

What are these clocks for, and why are they reparented / reclocked?

Shouldn't they be passed to 'clocks' as well?

-Paul

The G3D clock system can have multiple parents, and for stable operation it's recommended to use the MPLL clock as the parent (which in turn is actually a mux as well). MOUT_G3D is simply the mux for CLK_G3D (SGX core clock), DOUT_G3D is the divider. DOUT_G3D could equally be CLK_G3D (and probably should be, for readability) as CLK_G3D is simply the gate and DOUT_G3D is the divider for it.

Quoted 26 lines · Jonathan Bakker

Hi Paul,

Quoted 23 lines · Paul Cercueil

Quoted 20 lines · H. Nikolaus Schaller

From: Jonathan Bakker <[email protected]>

All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.

There is no external regulator for it so it can be enabled by default.

Signed-off-by Jonathan Bakker <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++

 1 file changed, 13 insertions(+)

arch/arm/boot/dts/s5pv210.dtsi +0 -0

index 2ad642f51fd9..abbdda205c1b 100644
@@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 {
              #interrupt-cells = <1>;
          };
 

Quoted 2 lines

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 516

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi +2 -0

+        gpu: gpu@f3000000 {
+            compatible = "samsung,s5pv210-sgx540-120";

This should not pass the bindings check because you missed last compatibles.

Quoted 17 lines

Quoted 10 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 525

Quoted 9 lines

arch/arm/boot/dts/s5pv210.dtsi +9 -0

+            reg = <0xf3000000 0x10000>;
+            interrupt-parent = <&vic2>;
+            interrupts = <10>;
+            clock-names = "core";
+            clocks = <&clocks CLK_G3D>;
+
+            assigned-clocks = <&clocks MOUT_G3D>, <&clocks DOUT_G3D>;
+            assigned-clock-rates = <0>, <66700000>;
+            assigned-clock-parents = <&clocks MOUT_MPLL>;

Quoted 6 lines

What are these clocks for, and why are they reparented / reclocked?

Shouldn't they be passed to 'clocks' as well?

-Paul

Quoted 6 lines

The G3D clock system can have multiple parents, and for stable operation it's recommended to use the MPLL clock as the parent (which in turn is actually a mux as well). MOUT_G3D is simply the mux for CLK_G3D (SGX core clock), DOUT_G3D is the divider. DOUT_G3D could equally be CLK_G3D (and probably should be, for readability) as CLK_G3D is simply the gate and DOUT_G3D is the divider for it.

Good point, it should be CLK_G3D instead of DOUT. Can you fix this as well?

Best regards,
Krzysztof

Hi Krzysztof,

Quoted 27 lines · Krzysztof Kozlowski

Quoted 26 lines · Jonathan Bakker

Hi Paul,

Quoted 23 lines · Paul Cercueil

Quoted 20 lines · H. Nikolaus Schaller

From: Jonathan Bakker <[email protected]>

All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.

There is no external regulator for it so it can be enabled by default.

Signed-off-by Jonathan Bakker <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++

 1 file changed, 13 insertions(+)

arch/arm/boot/dts/s5pv210.dtsi +0 -0

index 2ad642f51fd9..abbdda205c1b 100644
@@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 {
              #interrupt-cells = <1>;
          };
 

Quoted 6 lines

Quoted 2 lines

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 516

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi +2 -0

+        gpu: gpu@f3000000 {
+            compatible = "samsung,s5pv210-sgx540-120";

This should not pass the bindings check because you missed last compatibles.

Thanks for pointing that out, I'll add it and make sure it passes the bindings check.

Quoted 24 lines

Quoted 23 lines

Quoted 10 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 525

Quoted 9 lines

arch/arm/boot/dts/s5pv210.dtsi +9 -0

+            reg = <0xf3000000 0x10000>;
+            interrupt-parent = <&vic2>;
+            interrupts = <10>;
+            clock-names = "core";
+            clocks = <&clocks CLK_G3D>;
+
+            assigned-clocks = <&clocks MOUT_G3D>, <&clocks DOUT_G3D>;
+            assigned-clock-rates = <0>, <66700000>;
+            assigned-clock-parents = <&clocks MOUT_MPLL>;

Quoted 6 lines

What are these clocks for, and why are they reparented / reclocked?

Shouldn't they be passed to 'clocks' as well?

-Paul

The G3D clock system can have multiple parents, and for stable operation it's recommended to use the MPLL clock as the parent (which in turn is actually a mux as well). MOUT_G3D is simply the mux for CLK_G3D (SGX core clock), DOUT_G3D is the divider. DOUT_G3D could equally be CLK_G3D (and probably should be, for readability) as CLK_G3D is simply the gate and DOUT_G3D is the divider for it.

Quoted 2 lines

Good point, it should be CLK_G3D instead of DOUT. Can you fix this as well?

Yep, will do. Nikolaus, I'll send you an updated patch to include.

Quoted 61 lines · Jonathan Bakker

Quoted 27 lines · Krzysztof Kozlowski

Quoted 26 lines · Jonathan Bakker

Hi Paul,

Quoted 23 lines · Paul Cercueil

Quoted 20 lines · H. Nikolaus Schaller

From: Jonathan Bakker <[email protected]>

All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.

There is no external regulator for it so it can be enabled by default.

Signed-off-by Jonathan Bakker <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++

 1 file changed, 13 insertions(+)

arch/arm/boot/dts/s5pv210.dtsi +0 -0

index 2ad642f51fd9..abbdda205c1b 100644
@@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 {
              #interrupt-cells = <1>;
          };
 

Quoted 6 lines

Quoted 2 lines

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 516

Quoted 2 lines

arch/arm/boot/dts/s5pv210.dtsi +2 -0

+        gpu: gpu@f3000000 {
+            compatible = "samsung,s5pv210-sgx540-120";

This should not pass the bindings check because you missed last compatibles.

Thanks for pointing that out, I'll add it and make sure it passes the bindings check.

Quoted 24 lines

Quoted 23 lines

Quoted 10 lines

arch/arm/boot/dts/s5pv210.dtsi vic3: interrupt-controller@f2300000 { · line 525

Quoted 9 lines

arch/arm/boot/dts/s5pv210.dtsi +9 -0

+            reg = <0xf3000000 0x10000>;
+            interrupt-parent = <&vic2>;
+            interrupts = <10>;
+            clock-names = "core";
+            clocks = <&clocks CLK_G3D>;
+
+            assigned-clocks = <&clocks MOUT_G3D>, <&clocks DOUT_G3D>;
+            assigned-clock-rates = <0>, <66700000>;
+            assigned-clock-parents = <&clocks MOUT_MPLL>;

Quoted 6 lines

What are these clocks for, and why are they reparented / reclocked?

Shouldn't they be passed to 'clocks' as well?

-Paul

The G3D clock system can have multiple parents, and for stable operation it's recommended to use the MPLL clock as the parent (which in turn is actually a mux as well). MOUT_G3D is simply the mux for CLK_G3D (SGX core clock), DOUT_G3D is the divider. DOUT_G3D could equally be CLK_G3D (and probably should be, for readability) as CLK_G3D is simply the gate and DOUT_G3D is the divider for it.

Quoted 5 lines

Quoted 2 lines

Good point, it should be CLK_G3D instead of DOUT. Can you fix this as well?

Yep, will do. Nikolaus, I'll send you an updated patch to include.

How are assigned-clocks handled in the yaml DT schema? When running make dtbs_check, I end up with messages such as

arch/arm/boot/dts/s5pv210-aquila.dt.yaml: gpu@f3000000: 'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks' do not match any of the regexes: 'pinctrl-[0-9]+'

Do they need to explicitly be listed as valid entries?

Hi all,

Quoted 75 lines · Jonathan Bakker

Hi Krzysztof,

Quoted 31 lines · Krzysztof Kozlowski

Quoted 30 lines · Jonathan Bakker

Hi Paul,

Quoted 27 lines · Paul Cercueil

Quoted 23 lines · H. Nikolaus Schaller

From: Jonathan Bakker <[email protected]>

All s5pv210 devices have a PowerVR SGX 540 (revision 120)
attached.

There is no external regulator for it so it can be enabled by
default.

Signed-off-by Jonathan Bakker <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---

  arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++
  1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/s5pv210.dtsi
b/arch/arm/boot/dts/s5pv210.dtsi
index 2ad642f51fd9..abbdda205c1b 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi

 @@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 {
              #interrupt-cells = <1>;
          };

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+ gpu: gpu@f3000000 {
+ compatible = "samsung,s5pv210-sgx540-120";

This should not pass the bindings check because you missed last compatibles.

Thanks for pointing that out, I'll add it and make sure it passes
the bindings check.

Quoted 31 lines

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 +            reg = <0xf3000000 0x10000>;
 +            interrupt-parent = <&vic2>;
 +            interrupts = <10>;
 +            clock-names = "core";
 +            clocks = <&clocks CLK_G3D>;

+
+ assigned-clocks = <&clocks MOUT_G3D>, <&clocks
DOUT_G3D>;
+ assigned-clock-rates = <0>, <66700000>;
+ assigned-clock-parents = <&clocks MOUT_MPLL>;

Quoted 7 lines

What are these clocks for, and why are they reparented /
reclocked?

Shouldn't they be passed to 'clocks' as well?

-Paul

The G3D clock system can have multiple parents, and for stable
operation
it's recommended to use the MPLL clock as the parent (which in
turn
is actually a mux as well). MOUT_G3D is simply the mux for
CLK_G3D
(SGX core clock), DOUT_G3D is the divider. DOUT_G3D could
equally be CLK_G3D
(and probably should be, for readability) as CLK_G3D is simply
the gate and
DOUT_G3D is the divider for it.

Quoted 6 lines

Quoted 3 lines

Good point, it should be CLK_G3D instead of DOUT. Can you fix
this as
well?

Yep, will do. Nikolaus, I'll send you an updated patch to include.

How are assigned-clocks handled in the yaml DT schema? When running make dtbs_check, I end up with messages such as

arch/arm/boot/dts/s5pv210-aquila.dt.yaml: gpu@f3000000: 'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks' do not match any of the regexes: 'pinctrl-[0-9]+'

Do they need to explicitly be listed as valid entries?

From: Philipp Rossak <[email protected]>

We are adding the devicetree binding for the PVR-SGX-544-115 gpu.

This driver is currently under development in the openpvrsgx-devgroup. Right now the full binding is not figured out, so we provide here a placeholder. It will be completed as soon as there is a demo available.

The currently used binding that is used during development is more complete and was already verifyed by loading the kernelmodule successful.

Signed-off-by Philipp Rossak <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

arch/arm/boot/dts/sun6i-a31.dtsi +0 -0

index f3425a66fc0a..933a825bf460 100644
@@ -1417,5 +1417,16 @@ p2wi: i2c@1f03400 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

arch/arm/boot/dts/sun6i-a31.dtsi +1 -1

+		};
 	};
 };
--

2.25.1

Quoted 17 lines · H. Nikolaus Schaller

From: Philipp Rossak <[email protected]>

We are adding the devicetree binding for the PVR-SGX-544-115 gpu.

This driver is currently under development in the openpvrsgx-devgroup. Right now the full binding is not figured out, so we provide here a placeholder. It will be completed as soon as there is a demo available.

The currently used binding that is used during development is more complete and was already verifyed by loading the kernelmodule successful.

Signed-off-by Philipp Rossak <[email protected]>

Signed-off-by H. Nikolaus Schaller <[email protected]>

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++

 1 file changed, 11 insertions(+)

arch/arm/boot/dts/sun6i-a31.dtsi p2wi: i2c@1f03400 { · line 1422

Quoted 11 lines

arch/arm/boot/dts/sun6i-a31.dtsi +3 -0

index f3425a66fc0a..933a825bf460 100644
@@ -1417,5 +1417,16 @@ p2wi: i2c@1f03400 {
              #address-cells = <1>;
              #size-cells = <0>;
          };
+
+        gpu: gpu@1c400000 {
+            compatible = "allwinner,sun8i-a31-sgx544-115",

arch/arm/boot/dts/sun6i-a31.dtsi p2wi: i2c@1f03400 { · line 1429

Quoted 7 lines

arch/arm/boot/dts/sun6i-a31.dtsi +7 -0

+                     "img,sgx544-115", "img,sgx544";
+            reg = <0x01c40000 0x10000>;
+            /*
+             * This node is currently a placeholder for the gpu.
+             * This will be completed when a full demonstration
+             * of the openpvrsgx driver is available for this board.
+             */

This node doesn't have clocks, so I don't see how it'd work.

Better delay the introduction of the GPU node for this board until you know it works.

-Paul