Add logic to consolidate TRBs for Synopsys xHC

PATCH Superseded Tejas Joglekar 2 participants 11 messages Oct 16, 2020 – Nov 19, 2020 1 message not in the archive

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USB USB xHCI driver DesignWare USB3 DRD IP driver

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Tejas Joglekar

author

2020-10-16 13:04 UTC #0 lore raw

v5 cover Add logic to consolidate TRBs for Synopsys xHC

The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command.

For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB).

If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.

This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform.

Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS.

Changes since v4:
- Updated [Patch 3/3] platform data structure initialization
- Trivial changes in commit wordings

Changes since v3:
- Removed the dt-binding patch
- Added new patch to pass the quirk as platform data
- Modified the patch to set the quirk

Changes since v2:
- Modified the xhci_unmap_temp_buffer function to unmap dma and c the dma flag
- Removed RFC tag

Changes since v1:
- Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4]
- Renamed the property and quirk as in other patches based on [PATCH 1/4]

Tejas Joglekar (3):
usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK
usb: xhci: Use temporary buffer to consolidate SG
usb: dwc3: Pass quirk as platform data

 drivers/usb/dwc3/host.c      |  10 +++
 drivers/usb/host/xhci-plat.c |   3 +
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   5 ++
 5 files changed, 155 insertions(+), 2 deletions(-)

Signature · 1 line

2.28.0

Tejas Joglekar

author

2020-10-16 13:05 UTC #1 lore raw

PATCH v5 1/3 usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK

This commit uses the private data passed by parent device to set the quirk for Synopsys xHC. This patch fixes the SNPS xHC hang issue when the data is scattered across small buffers which does not make atleast MPS size for given TRB cache size of SNPS xHC.

Signed-off-by Tejas Joglekar <[email protected]>

---
 drivers/usb/host/xhci-plat.c | 3 +++
 drivers/usb/host/xhci.h      | 1 +
 2 files changed, 4 insertions(+)

drivers/usb/host/xhci-plat.c +3 -0

index aa2d35f98200..4d34f6005381 100644
@@ -333,6 +333,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
 	if (priv && (priv->quirks & XHCI_SKIP_PHY_INIT))
 		hcd->skip_phy_initialization = 1;
 
+	if (priv && (priv->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK))
+		xhci->quirks |= XHCI_SG_TRB_CACHE_SIZE_QUIRK;
+
 	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (ret)
 		goto disable_usb_phy;

drivers/usb/host/xhci.h +1 -0

index 8be88379c0fb..f8e453a2674d 100644
@@ -1877,6 +1877,7 @@ struct xhci_hcd {
 #define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
 #define XHCI_RENESAS_FW_QUIRK	BIT_ULL(36)
 #define XHCI_SKIP_PHY_INIT	BIT_ULL(37)
+#define XHCI_SG_TRB_CACHE_SIZE_QUIRK	BIT_ULL(38)
 
 	unsigned int		num_active_eps;
 	unsigned int		limit_active_eps;

Signature · 1 line

2.28.0

Tejas Joglekar

author

2020-10-16 13:05 UTC #2 lore raw

PATCH v5 2/3 usb: xhci: Use temporary buffer to consolidate SG

In reply to Tejas Joglekar

If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.

This can be a problem if a class driver queues SG requests with many small-buffer entries. The XHCI driver will create a chained TRB for each entry which may trigger this issue.

This patch adds logic to the XHCI driver to detect and prevent this from happening.

For every (TRB_CACHE_SIZE - 2), we check the total buffer size of the SG list and if the last window of (TRB_CACHE_SIZE - 2) SG list length and we don't make up at least 1 MPS, we create a temporary buffer to consolidate full SG list into the buffer.

We check at (TRB_CACHE_SIZE - 2) window because it is possible that there would be a link and/or event data TRB that take up to 2 of the cache entries.

We discovered this issue with devices on other platforms but have not yet come across any device that triggers this on Linux. But it could be a real problem now or in the future. All it takes is N number of small chained TRBs. And other instances of the Synopsys IP may have smaller values for the TRB_CACHE_SIZE which would exacerbate the problem.

Signed-off-by Tejas Joglekar <[email protected]>

---
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   4 +
 3 files changed, 141 insertions(+), 2 deletions(-)

drivers/usb/host/xhci-ring.c +1 -1

index 167dae117f73..6d4dae5e5f21 100644
@@ -3325,7 +3325,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
 
 	full_len = urb->transfer_buffer_length;
 	/* If we have scatter/gather list, we use it. */
-	if (urb->num_sgs) {
+	if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
 		num_sgs = urb->num_mapped_sgs;
 		sg = urb->sg;
 		addr = (u64) sg_dma_address(sg);

drivers/usb/host/xhci.c +136 -1

161 lines not on this page · raw message

drivers/usb/host/xhci.h +4 -0

index f8e453a2674d..f69504f91b5e 100644
@@ -1330,6 +1330,10 @@ enum xhci_setup_dev {
 #define TRB_SIA			(1<<31)
 #define TRB_FRAME_ID(p)		(((p) & 0x7ff) << 20)
 
+/* TRB cache size for xHC with TRB cache */
+#define TRB_CACHE_SIZE_HS	8
+#define TRB_CACHE_SIZE_SS	16
+
 struct xhci_generic_trb {
 	__le32 field[4];
 };

Signature · 1 line

2.28.0

Tejas Joglekar

author

2020-10-16 13:05 UTC #3 lore raw

PATCH v5 3/3 usb: dwc3: Pass quirk as platform data

In reply to Tejas Joglekar

This commit adds the platform device data to setup the XHCI_SG_TRB_CACHE_SIZE_QUIRK quirk. DWC3 hosts which are PCI devices does not use OF to create platform device but create xhci-plat platform device at runtime. So this patch allows parent device to supply the quirk through platform data.

Signed-off-by Tejas Joglekar <[email protected]>

---
 drivers/usb/dwc3/host.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

drivers/usb/dwc3/host.c +10 -0

index e195176580de..0434bc8cec12 100644
@@ -11,6 +11,11 @@
 #include <linux/platform_device.h>
 
 #include "core.h"
+#include "../host/xhci-plat.h"
+
+static const struct xhci_plat_priv dwc3_pdata = {
+	.quirks = XHCI_SG_TRB_CACHE_SIZE_QUIRK,
+};
 
 static int dwc3_host_get_irq(struct dwc3 *dwc)
 {

@@ -87,6 +92,11 @@ int dwc3_host_init(struct dwc3 *dwc)
 		goto err;
 	}
 
+	ret = platform_device_add_data(xhci, &dwc3_pdata, sizeof(dwc3_pdata));
+	if (ret) {
+		dev_err(dwc->dev, "couldn't add platform data to xHCI device\n");
+		goto err;
+	}
 	memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
 
 	if (dwc->usb3_lpm_capable)

Signature · 1 line

2.28.0

Tejas Joglekar

author

2020-10-27 18:28 UTC #4 lore raw

In reply to Tejas Joglekar

Hi Mathias,

Quoted 48 lines · Tejas Joglekar

The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command.
For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB).
If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.
This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform.
Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS.
Changes since v4:
- Updated [Patch 3/3] platform data structure initialization
- Trivial changes in commit wordings
Changes since v3:
- Removed the dt-binding patch
- Added new patch to pass the quirk as platform data
- Modified the patch to set the quirk
Changes since v2:
- Modified the xhci_unmap_temp_buffer function to unmap dma and c the dma flag
- Removed RFC tag
Changes since v1:
- Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4]
- Renamed the property and quirk as in other patches based on [PATCH 1/4]
Tejas Joglekar (3):
usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK
usb: xhci: Use temporary buffer to consolidate SG
usb: dwc3: Pass quirk as platform data

Quoted 7 lines

 drivers/usb/dwc3/host.c      |  10 +++
 drivers/usb/host/xhci-plat.c |   3 +
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   5 ++
 5 files changed, 155 insertions(+), 2 deletions(-)

I have removed the dependency on setting quirk through device tree binding and added the quirk using platform data. Can you please review and if everything looks OK, can you please add this patch series to your tree?

Thanks & Regards,
Tejas Joglekar

A message that is not in the archive (sent off-list or not yet received): [email protected]

Tejas Joglekar

author

2020-10-29 02:13 UTC #6 lore raw

Hi,

Quoted 59 lines · Mathias Nyman

Quoted 58 lines · Tejas Joglekar
Hi Mathias,
Quoted 55 lines · Tejas Joglekar
The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command.
For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB).
If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.
This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform.
Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS.
Changes since v4:
- Updated [Patch 3/3] platform data structure initialization
- Trivial changes in commit wordings
Changes since v3:
- Removed the dt-binding patch
- Added new patch to pass the quirk as platform data
- Modified the patch to set the quirk
Changes since v2:
- Modified the xhci_unmap_temp_buffer function to unmap dma and c the dma flag
- Removed RFC tag
Changes since v1:
- Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4]
- Renamed the property and quirk as in other patches based on [PATCH 1/4]
Tejas Joglekar (3):
usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK
usb: xhci: Use temporary buffer to consolidate SG
usb: dwc3: Pass quirk as platform data
 drivers/usb/dwc3/host.c      |  10 +++
 drivers/usb/host/xhci-plat.c |   3 +
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   5 ++
 5 files changed, 155 insertions(+), 2 deletions(-)

Quoted 7 lines

Quoted 3 lines
I have removed the dependency on setting quirk through device tree binding and added the quirk using platform data. Can you please review and if everything looks OK, can you please add this patch series to your tree?
Sure, there aren't any functional changes to xhci since v3 of this series right? And if I remember correctly Felipe didn't have any objections to the dwc3 part either.

You are right, there are no functional changes to xhci since v3.

Quoted 5 lines

Felipe, do you want to take the 3/3 dwc3 patch separately after 1/3 and 2/3 are in, or should I take them all, or ask if Greg would like to pick up this series?
-Mathias

Regards,
Tejas Joglekar

Tejas Joglekar

author

2020-11-06 16:07 UTC #7 lore raw

Hi Felipe,

Quoted 61 lines · Tejas Joglekar

Hi,
Quoted 59 lines · Mathias Nyman
Quoted 58 lines · Tejas Joglekar
Hi Mathias,
Quoted 55 lines · Tejas Joglekar
The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command.
For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB).
If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.
This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform.
Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS.
Changes since v4:
- Updated [Patch 3/3] platform data structure initialization
- Trivial changes in commit wordings
Changes since v3:
- Removed the dt-binding patch
- Added new patch to pass the quirk as platform data
- Modified the patch to set the quirk
Changes since v2:
- Modified the xhci_unmap_temp_buffer function to unmap dma and c the dma flag
- Removed RFC tag
Changes since v1:
- Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4]
- Renamed the property and quirk as in other patches based on [PATCH 1/4]
Tejas Joglekar (3):
usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK
usb: xhci: Use temporary buffer to consolidate SG
usb: dwc3: Pass quirk as platform data
 drivers/usb/dwc3/host.c      |  10 +++
 drivers/usb/host/xhci-plat.c |   3 +
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   5 ++
 5 files changed, 155 insertions(+), 2 deletions(-)

Quoted 12 lines

Quoted 7 lines
Quoted 3 lines
I have removed the dependency on setting quirk through device tree binding and added the quirk using platform data. Can you please review and if everything looks OK, can you please add this patch series to your tree?
Sure, there aren't any functional changes to xhci since v3 of this series right? And if I remember correctly Felipe didn't have any objections to the dwc3 part either.
You are right, there are no functional changes to xhci since v3.
Quoted 3 lines
Felipe, do you want to take the 3/3 dwc3 patch separately after 1/3 and 2/3 are in, or should I take them all, or ask if Greg would like to pick up this series?

How would you like Mathias to go about merging the patch series?

Quoted 6 lines

Quoted 2 lines
-Mathias
Regards,
Tejas Joglekar

Thanks & Regards,
Tejas Joglekar

Tejas Joglekar

author

2020-11-12 05:40 UTC #8 lore raw

Hi,

Quoted 68 lines · Tejas Joglekar

Hi Felipe,
Quoted 66 lines · Tejas Joglekar
Hi,
Quoted 64 lines · Mathias Nyman
Quoted 57 lines · Tejas Joglekar
Hi Mathias,
Quoted 48 lines · Tejas Joglekar
The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command.
For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB).
If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.
This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform.
Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS.
Changes since v4:
- Updated [Patch 3/3] platform data structure initialization
- Trivial changes in commit wordings
Changes since v3:
- Removed the dt-binding patch
- Added new patch to pass the quirk as platform data
- Modified the patch to set the quirk
Changes since v2:
- Modified the xhci_unmap_temp_buffer function to unmap dma and c the dma flag
- Removed RFC tag
Changes since v1:
- Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4]
- Renamed the property and quirk as in other patches based on [PATCH 1/4]
Tejas Joglekar (3):
usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK
usb: xhci: Use temporary buffer to consolidate SG
usb: dwc3: Pass quirk as platform data
Quoted 7 lines
 drivers/usb/dwc3/host.c      |  10 +++
 drivers/usb/host/xhci-plat.c |   3 +
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   5 ++
 5 files changed, 155 insertions(+), 2 deletions(-)
Quoted 3 lines
I have removed the dependency on setting quirk through device tree binding and added the quirk using platform data. Can you please review and if everything looks OK, can you please add this patch series to your tree?
Sure, there aren't any functional changes to xhci since v3 of this series right? And if I remember correctly Felipe didn't have any objections to the dwc3 part either.

Quoted 6 lines

Quoted 5 lines
You are right, there are no functional changes to xhci since v3.
Quoted 3 lines
Felipe, do you want to take the 3/3 dwc3 patch separately after 1/3 and 2/3 are in, or should I take them all, or ask if Greg would like to pick up this series?
How would you like Mathias to go about merging the patch series?

@Felipe: Any input on this ?

Thanks & Regards,

Tejas Joglekar

author

2020-11-17 17:17 UTC #9 lore raw

Hello Mathias,

Quoted 75 lines · Tejas Joglekar

Hi,
Quoted 73 lines · Tejas Joglekar
Hi Felipe,
Quoted 71 lines · Tejas Joglekar
Hi,
Quoted 58 lines · Mathias Nyman
Quoted 57 lines · Tejas Joglekar
Hi Mathias,
Quoted 55 lines · Tejas Joglekar
The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command.
For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB).
If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.
This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform.
Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS.
Changes since v4:
- Updated [Patch 3/3] platform data structure initialization
- Trivial changes in commit wordings
Changes since v3:
- Removed the dt-binding patch
- Added new patch to pass the quirk as platform data
- Modified the patch to set the quirk
Changes since v2:
- Modified the xhci_unmap_temp_buffer function to unmap dma and c the dma flag
- Removed RFC tag
Changes since v1:
- Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4]
- Renamed the property and quirk as in other patches based on [PATCH 1/4]
Tejas Joglekar (3):
usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK
usb: xhci: Use temporary buffer to consolidate SG
usb: dwc3: Pass quirk as platform data
 drivers/usb/dwc3/host.c      |  10 +++
 drivers/usb/host/xhci-plat.c |   3 +
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   5 ++
 5 files changed, 155 insertions(+), 2 deletions(-)
Quoted 6 lines
Quoted 3 lines
I have removed the dependency on setting quirk through device tree binding and added the quirk using platform data. Can you please review and if everything looks OK, can you please add this patch series to your tree?
Sure, there aren't any functional changes to xhci since v3 of this series right? And if I remember correctly Felipe didn't have any objections to the dwc3 part either.
You are right, there are no functional changes to xhci since v3.
Quoted 3 lines
Felipe, do you want to take the 3/3 dwc3 patch separately after 1/3 and 2/3 are in, or should I take them all, or ask if Greg would like to pick up this series?

@Mathias: Can you please take up 2 patches and may be Felipe can take up the dwc3 ?

It would help if this patch series goes in upcoming rc.

Quoted 4 lines

Quoted 1 line
How would you like Mathias to go about merging the patch series?
@Felipe: Any input on this ?

Thanks & Regards,

Tejas Joglekar

Mathias Nyman

2020-11-18 14:07 UTC #10 lore raw

Quoted 72 lines · Tejas Joglekar

Hello Mathias,
Quoted 70 lines · Tejas Joglekar
Hi,
Quoted 68 lines · Tejas Joglekar
Hi Felipe,
Quoted 66 lines · Tejas Joglekar
Hi,
Quoted 64 lines · Mathias Nyman
Quoted 57 lines · Tejas Joglekar
Hi Mathias,
Quoted 48 lines · Tejas Joglekar
The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8 for HS. The controller loads and updates the TRB cache from the transfer ring in system memory whenever the driver issues a start transfer or update transfer command.
For chained TRBs, the Synopsys xHC requires that the total amount of bytes for all TRBs loaded in the TRB cache be greater than or equal to 1 MPS. Or the chain ends within the TRB cache (with a last TRB).
If this requirement is not met, the controller will not be able to send or receive a packet and it will hang causing a driver timeout and error.
This patch set adds logic to the XHCI driver to detect and prevent this from happening along with the quirk to enable this logic for Synopsys HAPS platform.
Based on Mathias's feedback on previous implementation where consolidation was done in TRB cache, with this patch series the implementation is done during mapping of the URB by consolidating the SG list into a temporary buffer if the SG list buffer sizes within TRB_CACHE_SIZE is less than MPS.
Changes since v4:
- Updated [Patch 3/3] platform data structure initialization
- Trivial changes in commit wordings
Changes since v3:
- Removed the dt-binding patch
- Added new patch to pass the quirk as platform data
- Modified the patch to set the quirk
Changes since v2:
- Modified the xhci_unmap_temp_buffer function to unmap dma and c the dma flag
- Removed RFC tag
Changes since v1:
- Comments from Greg are addressed on [PATCH 4/4] and [PATCH 1/4]
- Renamed the property and quirk as in other patches based on [PATCH 1/4]
Tejas Joglekar (3):
usb: xhci: Set quirk for XHCI_SG_TRB_CACHE_SIZE_QUIRK
usb: xhci: Use temporary buffer to consolidate SG
usb: dwc3: Pass quirk as platform data
Quoted 7 lines
 drivers/usb/dwc3/host.c      |  10 +++
 drivers/usb/host/xhci-plat.c |   3 +
 drivers/usb/host/xhci-ring.c |   2 +-
 drivers/usb/host/xhci.c      | 137 ++++++++++++++++++++++++++++++++++-
 drivers/usb/host/xhci.h      |   5 ++
 5 files changed, 155 insertions(+), 2 deletions(-)
Quoted 3 lines
I have removed the dependency on setting quirk through device tree binding and added the quirk using platform data. Can you please review and if everything looks OK, can you please add this patch series to your tree?
Sure, there aren't any functional changes to xhci since v3 of this series right? And if I remember correctly Felipe didn't have any objections to the dwc3 part either.

Quoted 9 lines

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
You are right, there are no functional changes to xhci since v3.
Quoted 3 lines
Felipe, do you want to take the 3/3 dwc3 patch separately after 1/3 and 2/3 are in, or should I take them all, or ask if Greg would like to pick up this series?
@Mathias: Can you please take up 2 patches and may be Felipe can take up the dwc3 ?
It would help if this patch series goes in upcoming rc.

Sure, added two first patches to my for-usb-next branch. Let them sit there for a while to get them through some testing loops

-Mathias

Tejas Joglekar

author

2020-11-19 01:19 UTC #11 lore raw

Quoted 9 lines · Mathias Nyman

Quoted 4 lines
@Mathias: Can you please take up 2 patches and may be Felipe can take up the dwc3 ?
It would help if this patch series goes in upcoming rc.
Sure, added two first patches to my for-usb-next branch. Let them sit there for a while to get them through some testing loops
-Mathias

Sure, thanks Mathias