Add support for Hikey 970 PCIe
Subsystems (6)
Device tree bindings PCI Generic PHY framework PCI native host bridge and endpoint drivers +2 more subsystems
cover Add support for Hikey 970 PCIe
That's the third attempt of adding PCIe support for Hikey 970 from my side. The past attempt was this one:
https://lore.kernel.org/lkml/[email protected]/
As requested by Rob Herring, this series use a different approach than the past attempt: it first splits the PHY part into a separate driver. Then, it adds support for Kirin 970.
Due to such change, the DT bindings had to change, as several properties moved from the PCIe driver to the PHY. IMO, it makes a lot more sense now.
This is is currently a work in progress. There are still a few things to be solved, but let me send what I have so far for a quick review if this approach is acceptable.
Manivannan,
Please notice that this patch:
PCI: kirin: split PHY interface from the driver
Contains the code written by you, on your attempt to upstream this. If you're OK, please send your SoB. I should likely add a Co-authored-by:
tag at the final version.
The same somewhat applies to this patch:
arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware
but at the reverse direction, as I had to shift some properties from the PCIe binding to the PCIe PHY one.
Also, if this approach is OK, I'm considering to move all clock lines to the PHY driver, as it makes more sense there, and the device is *very* sensitive to the clock order. Any change at the sequence may cause the SoC to generate a NMI interrupt (SError), which, in turn, causes a kernel panic.
Manivannan Sadhasivam (1):
arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller
hardware
Mauro Carvalho Chehab (6):
PCI: kirin: split PHY interface from the driver
PCI: kirin: use regmap for APB registers
bindings: kirin-pcie.txt: fix compatible string
bindings: kirin-pcie.txt: drop PHY properties
bindings: phy: add bindings for Hikey 960 PCIe PHY
phy: add driver for Kirin 970 PCIe PHY
.../devicetree/bindings/pci/kirin-pcie.txt | 24 +- .../phy/hisilicon,phy-hi3660-pcie.yaml | 70 ++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 +- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 ++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - drivers/pci/controller/dwc/pcie-kirin.c | 254 ++---- drivers/phy/hisilicon/Kconfig | 20 + drivers/phy/hisilicon/Makefile | 2 + drivers/phy/hisilicon/phy-hi3660-pcie.c | 273 ++++++ drivers/phy/hisilicon/phy-hi3670-pcie.c | 844 ++++++++++++++++++ 10 files changed, 1370 insertions(+), 219 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
Signature · 1 line
2.31.1
RFC PATCH 1/7 PCI: kirin: split PHY interface from the driver
The pcie-kirin PCIe driver contains internally a PHY interface for a Hikey 960. As we'll be adding support also for Hikey 970, we need to first split the PHY into a separate driver.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
--- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 24 +- drivers/pci/controller/dwc/pcie-kirin.c | 206 +++------------- drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3660-pcie.c | 273 ++++++++++++++++++++++ 5 files changed, 333 insertions(+), 181 deletions(-) create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
arch/arm64/boot/dts/hisilicon/hi3660.dtsi +15 -9
@@ -1001,17 +1001,28 @@ spi3: spi@ff3b3000 { status = "disabled"; }; + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>; + clock-names = "pcie_phy_ref", "pcie_apb_phy"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xf5000000 0x0 0x2000>; - reg-names = "dbi", "apb", "phy", "config"; + reg-names = "dbi", "apb", "config"; bus-range = <0x0 0x1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + phys = <&pcie_phy>; ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>;
@@ -1028,15 +1039,10 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + clocks = <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", - "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; + clock-names = "pcie_aux", "pcie_apb_sys", "pcie_aclk"; }; /* UFS */
drivers/pci/controller/dwc/pcie-kirin.c +34 -172
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drivers/phy/hisilicon/Kconfig +10 -0
@@ -23,6 +23,16 @@ config PHY_HI3660_USB To compile this driver as a module, choose M here. +config PHY_HI3660_PCIE + tristate "hi3660 PCIe PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HISILICON HI3660 PCIe PHY. + + To compile this driver as a module, choose M here. + config PHY_HI3670_USB tristate "hi3670 USB PHY support" depends on (ARCH_HISI && ARM64) || COMPILE_TEST
drivers/phy/hisilicon/Makefile +1 -0
@@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_HI3660_USB) += phy-hi3660-usb3.o +obj-$(CONFIG_PHY_HI3660_PCIE) += phy-hi3660-pcie.o obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o
drivers/phy/hisilicon/phy-hi3660-pcie.c new file +273 -0
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Signature · 1 line
2.31.1
RFC PATCH 2/7 PCI: kirin: use regmap for APB registers
In reply to Mauro Carvalho ChehabThe PHY layer need to access APB registers too, for Kirin 970. So, place them into a named regmap.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
--- drivers/pci/controller/dwc/pcie-kirin.c | 51 +++++++++++++------------ 1 file changed, 27 insertions(+), 24 deletions(-)
drivers/pci/controller/dwc/pcie-kirin.c +27 -24
@@ -55,23 +55,11 @@struct kirin_pcie {struct dw_pcie *pci;struct phy *phy; -void __iomem *apb_base; +struct regmap *apb;struct clk *apb_sys_clk;struct clk *pcie_aux_clk; }; -/* Registers in PCIeCTRL */ -static inline void kirin_apb_ctrl_writel (struct kirin_pcie *kirin_pcie, -u32 val,u32 reg) -{ -writel (val, kirin_pcie->apb_base + reg); -} - -static inline u32 kirin_apb_ctrl_readl (struct kirin_pcie *kirin_pcie,u32 reg) -{ -return readl (kirin_pcie->apb_base + reg); -} -static long kirin_pcie_get_clk (struct kirin_pcie *kirin_pcie,struct platform_device *pdev) {
@@ -88,13 +76,27 @@ static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,return 0 ; } +static const struct regmap_config pcie_kirin_regmap_conf = { + .name ="kirin_pcie_apb" , + .reg_bits =32 , + .val_bits =32 , + .reg_stride =4 , +}; +static long kirin_pcie_get_resource (struct kirin_pcie *kirin_pcie,struct platform_device *pdev) { - kirin_pcie->apb_base = -devm_platform_ioremap_resource_byname (pdev,"apb" ); -if (IS_ERR (kirin_pcie->apb_base)) -return PTR_ERR (kirin_pcie->apb_base); +struct device *dev = &pdev->dev; +void __iomem *apb_base; + + apb_base =devm_platform_ioremap_resource_byname (pdev,"apb" ); +if (IS_ERR (apb_base)) +return PTR_ERR (apb_base); + + kirin_pcie->apb =devm_regmap_init_mmio (dev, apb_base, + &pcie_kirin_regmap_conf); +if (IS_ERR (kirin_pcie->apb)) +return PTR_ERR (kirin_pcie->apb);return 0 ; }
@@ -148,13 +150,13 @@ static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, {u32 val; - val =kirin_apb_ctrl_readl (kirin_pcie,SOC_PCIECTRL_CTRL0_ADDR ); +regmap_read (kirin_pcie->apb,SOC_PCIECTRL_CTRL0_ADDR , &val);if (on) val = val |PCIE_ELBI_SLV_DBI_ENABLE ;else val = val & ~PCIE_ELBI_SLV_DBI_ENABLE ; -kirin_apb_ctrl_writel (kirin_pcie, val,SOC_PCIECTRL_CTRL0_ADDR ); +regmap_write (kirin_pcie->apb,SOC_PCIECTRL_CTRL0_ADDR , val); } static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
@@ -162,13 +164,13 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, {u32 val; - val =kirin_apb_ctrl_readl (kirin_pcie,SOC_PCIECTRL_CTRL1_ADDR ); +regmap_read (kirin_pcie->apb,SOC_PCIECTRL_CTRL1_ADDR , &val);if (on) val = val |PCIE_ELBI_SLV_DBI_ENABLE ;else val = val & ~PCIE_ELBI_SLV_DBI_ENABLE ; -kirin_apb_ctrl_writel (kirin_pcie, val,SOC_PCIECTRL_CTRL1_ADDR ); +regmap_write (kirin_pcie->apb,SOC_PCIECTRL_CTRL1_ADDR , val); } static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
@@ -228,8 +230,9 @@ static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,static int kirin_pcie_link_up (struct dw_pcie *pci) {struct kirin_pcie *kirin_pcie =to_kirin_pcie (pci); -u32 val =kirin_apb_ctrl_readl (kirin_pcie,PCIE_APB_PHY_STATUS0 ); +u32 val; +regmap_read (kirin_pcie->apb,PCIE_APB_PHY_STATUS0 , &val);if ((val &PCIE_LINKUP_ENABLE ) ==PCIE_LINKUP_ENABLE )return 1 ;
@@ -241,8 +244,8 @@ static int kirin_pcie_start_link(struct dw_pcie *pci)struct kirin_pcie *kirin_pcie =to_kirin_pcie (pci);/* assert LTSSM enable */ -kirin_apb_ctrl_writel (kirin_pcie,PCIE_LTSSM_ENABLE_BIT , -PCIE_APP_LTSSM_ENABLE ); +regmap_write (kirin_pcie->apb,PCIE_APP_LTSSM_ENABLE , +PCIE_LTSSM_ENABLE_BIT );return 0 ; }
Signature · 1 line
2.31.1
RFC PATCH 3/7 bindings: kirin-pcie.txt: fix compatible string
In reply to Mauro Carvalho ChehabThe pcie-kirin driver doesn't declare a hisilicon,kirin-pcie. Also, remove the useless comment after the description, as other compat will be supported by the same driver in the future.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
--- Documentation/devicetree/bindings/pci/kirin-pcie.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pci/kirin-pcie.txt +2 -2
@@ -9,7 +9,7 @@ Additional properties are described here: Required properties - compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC + "hisilicon,kirin960-pcie" - reg: Should contain rc_dbi, apb, phy, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers;
@@ -23,7 +23,7 @@ Optional properties: Example based on kirin960: pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; + compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; reg-names = "dbi","apb","phy", "config";
Signature · 1 line
2.31.1
RFC PATCH 4/7 bindings: kirin-pcie.txt: drop PHY properties
In reply to Mauro Carvalho ChehabThere are several properties there that belong to the PHY interface. Drop them, as a new binding file will describe the PHY properties for Kirin 960.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
--- .../devicetree/bindings/pci/kirin-pcie.txt | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-)
Documentation/devicetree/bindings/pci/kirin-pcie.txt +6 -13
@@ -10,13 +10,11 @@ Additional properties are described here: Required properties - compatible: "hisilicon,kirin960-pcie" -- reg: Should contain rc_dbi, apb, phy, config registers location and length. +- reg: Should contain rc_dbi, apb, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers; "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. Optional properties:
@@ -25,8 +23,8 @@ Example based on kirin960: pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; + <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb", "config"; bus-range = <0x0 0x1>; #address-cells = <3>; #size-cells = <2>;
@@ -39,12 +37,7 @@ Example based on kirin960: <0x0 0 0 2 &gic 0 0 0 283 4>, <0x0 0 0 3 &gic 0 0 0 284 4>, <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; + clocks = <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>; + clock-names = "pcie_aux", "pcie_apb_sys"; };
Signature · 1 line
2.31.1
RFC PATCH 5/7 bindings: phy: add bindings for Hikey 960 PCIe PHY
In reply to Mauro Carvalho ChehabDocument the bindings for Hikey 960 (hi3660) PCIe PHY interface, supported via the pcie-kirin driver.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
--- .../phy/hisilicon,phy-hi3660-pcie.yaml | 70 +++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +-- 2 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml new file +70 -0
@@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin960 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab <[email protected]> + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 960. + +properties: + compatible: + const: hisilicon,hi960-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe APB PHY clock + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_apb_phy + + reset-gpios: + description: PCI PERST reset GPIO(s) + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>; + clock-names = "pcie_phy_ref", "pcie_apb_phy"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + }; +...
arch/arm64/boot/dts/hisilicon/hi3660.dtsi +6 -5
@@ -1006,8 +1006,10 @@ pcie_phy: pcie-phy@f3f2000 { reg = <0x0 0xf3f20000 0x0 0x40000>; reg-names = "phy"; clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>; - clock-names = "pcie_phy_ref", "pcie_apb_phy"; + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_apb_phy", + "pcie_aclk"; reset-gpios = <&gpio11 1 0 >; #phy-cells = <0>; };
@@ -1040,9 +1042,8 @@ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_aux", "pcie_apb_sys", "pcie_aclk"; + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>; + clock-names = "pcie_aux", "pcie_apb_sys"; }; /* UFS */
Signature · 1 line
2.31.1
RFC PATCH 6/7 phy: add driver for Kirin 970 PCIe PHY
In reply to Mauro Carvalho ChehabThe Kirin 970 PHY is somewhat similar to the Kirin 960, but it does a lot more. Add the needed bits for PCIe to start working on Hikey 970 boards.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
--- .../devicetree/bindings/pci/kirin-pcie.txt | 1 + drivers/pci/controller/dwc/pcie-kirin.c | 5 + drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3670-pcie.c | 844 ++++++++++++++++++ 5 files changed, 861 insertions(+) create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
Documentation/devicetree/bindings/pci/kirin-pcie.txt +1 -0
@@ -10,6 +10,7 @@ Additional properties are described here: Required properties - compatible: "hisilicon,kirin960-pcie" + "hisilicon,kirin970-pcie" - reg: Should contain rc_dbi, apb, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers;
drivers/pci/controller/dwc/pcie-kirin.c +5 -0
@@ -98,6 +98,10 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,if (IS_ERR (kirin_pcie->apb))return PTR_ERR (kirin_pcie->apb); +dev_info (dev,"pcie-kirin full name: %s\n" , + dev->of_node->full_name); + +return 0 ; }
@@ -336,6 +340,7 @@ static int __exit kirin_pcie_remove(struct platform_device *pdev)static const struct of_device_id kirin_pcie_match[] = { { .compatible ="hisilicon,kirin960-pcie" }, + { .compatible ="hisilicon,kirin970-pcie" }, {}, };
drivers/phy/hisilicon/Kconfig +10 -0
@@ -43,6 +43,16 @@ config PHY_HI3670_USB To compile this driver as a module, choose M here. +config PHY_HI3670_PCIE + tristate "hi3670 PCIe PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HISILICON HI3670 PCIe PHY. + + To compile this driver as a module, choose M here. + config PHY_HISTB_COMBPHY tristate "HiSilicon STB SoCs COMBPHY support" depends on (ARCH_HISI && ARM64) || COMPILE_TEST
drivers/phy/hisilicon/Makefile +1 -0
@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_HI3660_USB) += phy-hi3660-usb3.o obj-$(CONFIG_PHY_HI3660_PCIE) += phy-hi3660-pcie.o obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o +obj-$(CONFIG_PHY_HI3670_PCIE) += phy-hi3670-pcie.o obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
drivers/phy/hisilicon/phy-hi3670-pcie.c new file +844 -0
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2.31.1
RFC PATCH 7/7 arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware
In reply to Mauro Carvalho ChehabFrom: Manivannan Sadhasivam <[email protected]>
Add DTS bindings for the Hikey 970 board's PCIe hardware.
[[email protected]: fix merge conflicts]
Signed-off-by Manivannan Sadhasivam <[email protected]>
Signed-off-by Mauro Carvalho Chehab <[email protected]>
--- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 +++++++++++++++++++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - 2 files changed, 72 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/hisilicon/hi3670.dtsi +72 -0
@@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -660,6 +666,72 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + reg-names = "phy"; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + + clock-names = "pcie_phy_ref", "pcie_apb_phy", + "pcie_aclk"; + + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + eye_param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>; + clock-names = "pcie_aux", "pcie_apb_sys"; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +0 -1
@@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */
Signature · 1 line
2.31.1