soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Souradeep Chowdhury <[email protected]>

---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

Quoted 8 lines · Souradeep Chowdhury

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Souradeep Chowdhury <[email protected]>

---
  .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 44 ++++++++++++++++++++++
  1 file changed, 44 insertions(+)

Rebase your tree on some current Linux kernel (and use scripts/get_maintainers.pl).

Best regards,
Krzysztof

Quoted 5 lines · Souradeep Chowdhury

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Souradeep Chowdhury <[email protected]>

Quoted 3 lines

---
  .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 44 ++++++++++++++++++++++
  1 file changed, 44 insertions(+)

Rebase your tree on some current Linux kernel (and use scripts/get_maintainers.pl).

Best regards,
Krzysztof

Quoted 6 lines · Krzysztof Kozlowski

Quoted 5 lines · Souradeep Chowdhury

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Souradeep Chowdhury <[email protected]>

Souradeep, I will review v14 (of the code anyway--patch 3) when you send it.

                    -Alex

Quoted 12 lines

Quoted 5 lines

---
  .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 44
++++++++++++++++++++++

  1 file changed, 44 insertions(+)

Rebase your tree on some current Linux kernel (and use scripts/get_maintainers.pl).

Best regards,
Krzysztof

The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the

drivers/soc/qcom/dcc.c new file +31 -0

+
+#define DCC_RD_MOD_WR_ADDR              0xC105E
+
+/*DCC debugfs directory*/
+static struct dentry	*dcc_dbg;
+
+enum dcc_descriptor_type {
+	DCC_READ_TYPE,
+	DCC_LOOP_TYPE,
+	DCC_READ_WRITE_TYPE,
+	DCC_WRITE_TYPE
+};
+
+struct dcc_config_entry {
+	u32				base;
+	u32				offset;
+	u32				len;
+	u32				loop_cnt;
+	u32				write_val;
+	u32				mask;
+	bool				apb_bus;
+	enum dcc_descriptor_type	desc_type;
+	struct list_head		list;
+};
+
+/**
+ * struct dcc_drvdata - configuration information related to a dcc device
+ * @base:	      Base Address of the dcc device
+ * @dev:	      The device attached to the driver data
+ * @mutex:	      Lock to protect access and manipulation of dcc_drvdata
+ * @ram_base:         Base address for the SRAM dedicated for the dcc device

+ * @enable: This contains an array of linkedlist enable flags

drivers/soc/qcom/dcc.c new file +36 -0

+
+static int dcc_probe(struct platform_device *pdev)
+{
+	u32 val;
+	int ret = 0, i, size;
+	struct device *dev = &pdev->dev;
+	struct dcc_drvdata *dcc;
+	struct resource *res;
+
+	dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL);
+	if (!dcc)
+		return -ENOMEM;
+
+	dcc->dev = &pdev->dev;
+	platform_set_drvdata(pdev, dcc);
+
+	dcc->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dcc->base))
+		return PTR_ERR(dcc->base);
+
+	dcc->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
+	if (IS_ERR(dcc->ram_base))
+		return PTR_ERR(dcc->ram_base);
+
+	dcc->ram_size = resource_size(res);
+
+	dcc->ram_offset = (size_t)of_device_get_match_data(&pdev->dev);
+
+	val = dcc_readl(dcc, DCC_HW_INFO);
+
+	if (FIELD_GET(DCC_VER_INFO_MASK, val)) {
+		dcc->mem_map_ver = 3;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else if ((val & DCC_VER_MASK2) == DCC_VER_MASK2) {

drivers/soc/qcom/dcc.c new file +5 -0

+		dcc_sram_dev_exit(dcc);
+		return ret;
+	}
+
+	return 0;

drivers/soc/qcom/dcc.c new file +18 -0

+	dcc_config_reset(drvdata);
+
+	return 0;
+}
+
+static const struct of_device_id dcc_match_table[] = {
+	{ .compatible = "qcom,sm8150-dcc", .data = (void *)0x5000 },
+	{ .compatible = "qcom,sc7280-dcc", .data = (void *)0x12000 },
+	{ .compatible = "qcom,sc7180-dcc", .data = (void *)0x6000 },
+	{ .compatible = "qcom,sdm845-dcc", .data = (void *)0x6000 },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, dcc_match_table);
+
+static struct platform_driver dcc_driver = {
+	.probe = dcc_probe,
+	.remove	= dcc_remove,
+	.driver	= {

Quoted 4 lines · Souradeep Chowdhury

The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the

(...)

Quoted 34 lines

drivers/soc/qcom/dcc.c new file +34 -0

+
+#define DCC_RD_MOD_WR_ADDR              0xC105E
+
+/*DCC debugfs directory*/
+static struct dentry	*dcc_dbg;
+
+enum dcc_descriptor_type {
+	DCC_READ_TYPE,
+	DCC_LOOP_TYPE,
+	DCC_READ_WRITE_TYPE,
+	DCC_WRITE_TYPE
+};
+
+struct dcc_config_entry {
+	u32				base;
+	u32				offset;
+	u32				len;
+	u32				loop_cnt;
+	u32				write_val;
+	u32				mask;
+	bool				apb_bus;
+	enum dcc_descriptor_type	desc_type;
+	struct list_head		list;
+};
+
+/**
+ * struct dcc_drvdata - configuration information related to a dcc device
+ * @base:	      Base Address of the dcc device
+ * @dev:	      The device attached to the driver data
+ * @mutex:	      Lock to protect access and manipulation of dcc_drvdata
+ * @ram_base:         Base address for the SRAM dedicated for the dcc device
+ * @ram_size:         Total size of the SRAM dedicated for the dcc device
+ * @ram_offset:       Offset to the SRAM dedicated for dcc device
+ * @mem_map_ver:      Memory map version of DCC hardware

Quoted 7 lines

+ * @ram_cfg: Used for address limit calculation for dcc
+ * @ram_start: Starting address of DCC SRAM
+ * @sram_dev: Micellaneous device equivalent of dcc SRAM
+ * @cfg_head: Points to the head of the linked list of addresses

+ * @dbg_dir:          The dcc debugfs directory under which all the debugfs files are placed
+ * @nr_link_list:     Total number of linkedlists supported by the DCC configuration
+ * @loopoff:          Loop offset bits range for the addresses

All these entres have messed up spacing.

Quoted 2 lines

+ * @enable: This contains an array of linkedlist enable flags

No, this is not an array of linked lists... It's a pointer to bool. This is not way to store linked lists.

Quoted 42 lines

drivers/soc/qcom/dcc.c new file +40 -0

+
+static int dcc_probe(struct platform_device *pdev)
+{
+	u32 val;
+	int ret = 0, i, size;
+	struct device *dev = &pdev->dev;
+	struct dcc_drvdata *dcc;
+	struct resource *res;
+
+	dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL);
+	if (!dcc)
+		return -ENOMEM;
+
+	dcc->dev = &pdev->dev;
+	platform_set_drvdata(pdev, dcc);
+
+	dcc->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dcc->base))
+		return PTR_ERR(dcc->base);
+
+	dcc->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
+	if (IS_ERR(dcc->ram_base))
+		return PTR_ERR(dcc->ram_base);
+
+	dcc->ram_size = resource_size(res);
+
+	dcc->ram_offset = (size_t)of_device_get_match_data(&pdev->dev);
+
+	val = dcc_readl(dcc, DCC_HW_INFO);
+
+	if (FIELD_GET(DCC_VER_INFO_MASK, val)) {
+		dcc->mem_map_ver = 3;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;
+	} else if ((val & DCC_VER_MASK2) == DCC_VER_MASK2) {
+		dcc->mem_map_ver = 2;
+		dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO);
+		if (dcc->nr_link_list == 0)
+			return	-EINVAL;

drivers/soc/qcom/dcc.c line 1274

Quoted 6 lines

drivers/soc/qcom/dcc.c new file +6 -0

+	} else {
+		dcc->mem_map_ver = 1;
+		dcc->nr_link_list = DCC_MAX_LINK_LIST;
+	}
+
+	/* Either set the fixed loop offset or calculate it

Start with /*
(see coding style)

drivers/soc/qcom/dcc.c line 1286

Quoted 13 lines

drivers/soc/qcom/dcc.c new file +12 -0

+	 * from ram_size.Max consecutive addresses the
+	 * dcc can loop is equivalent to the ram size
+	 */
+	if (val & DCC_LOOP_OFFSET_MASK)
+		dcc->loopoff = DCC_FIX_LOOP_OFFSET;
+	else
+		dcc->loopoff = get_bitmask_order((dcc->ram_size +
+				dcc->ram_offset) / 4 - 1);
+
+	mutex_init(&dcc->mutex);
+	/* Allocate space for all entries at once */
+	size = sizeof(*dcc->enable) + sizeof(*dcc->cfg_head);

This is quite confusing way of handling lists - some parts of drvdata are list, some are not.

drivers/soc/qcom/dcc.c line 1292

Quoted 6 lines

drivers/soc/qcom/dcc.c new file +6 -0

+
+	dcc->enable = devm_kcalloc(dev, dcc->nr_link_list, size, GFP_KERNEL);
+	if (!dcc->enable)
+		return -ENOMEM;
+
+	dcc->cfg_head = (struct list_head *)(dcc->enable + dcc->nr_link_list);

That's unusual way to iterate over list...

Quoted 4 lines

drivers/soc/qcom/dcc.c new file +3 -0

+
+	for (i = 0; i < dcc->nr_link_list; i++)
+		INIT_LIST_HEAD(&dcc->cfg_head[i]);

drivers/soc/qcom/dcc.c line 1305

Quoted 10 lines

drivers/soc/qcom/dcc.c new file +10 -0

+
+	ret = dcc_sram_dev_init(dcc);
+	if (ret) {
+		dev_err(dcc->dev, "DCC: sram node not registered.\n");
+		return ret;
+	}
+
+	ret = dcc_create_debug_dir(dcc);
+	if (ret) {
+		dev_err(dcc->dev, "DCC: debugfs files not created.\n");

debugfs failures are not reasons to fail probe. Also no need to print errors.

Quoted 8 lines

drivers/soc/qcom/dcc.c new file +8 -0

+		dcc_sram_dev_exit(dcc);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dcc_remove(struct platform_device *pdev)

drivers/soc/qcom/dcc.c line 1320

Quoted 7 lines

drivers/soc/qcom/dcc.c new file +7 -0

+{
+	struct dcc_drvdata *drvdata = platform_get_drvdata(pdev);
+
+	dcc_delete_debug_dir(drvdata);
+
+	dcc_sram_dev_exit(drvdata);
+

No need for blank lines between each calls.

Quoted 19 lines

drivers/soc/qcom/dcc.c new file +18 -0

+	dcc_config_reset(drvdata);
+
+	return 0;
+}
+
+static const struct of_device_id dcc_match_table[] = {
+	{ .compatible = "qcom,sm8150-dcc", .data = (void *)0x5000 },
+	{ .compatible = "qcom,sc7280-dcc", .data = (void *)0x12000 },
+	{ .compatible = "qcom,sc7180-dcc", .data = (void *)0x6000 },
+	{ .compatible = "qcom,sdm845-dcc", .data = (void *)0x6000 },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, dcc_match_table);
+
+static struct platform_driver dcc_driver = {
+	.probe = dcc_probe,
+	.remove	= dcc_remove,
+	.driver	= {

drivers/soc/qcom/dcc.c line 1348

Quoted 10 lines

drivers/soc/qcom/dcc.c new file +10 -0

+		.name = "qcom-dcc",
+		.of_match_table	= dcc_match_table,
+	},
+};
+
+module_platform_driver(dcc_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver");
+

Best regards,
Krzysztof

The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the

Quoted 4 lines · Souradeep Chowdhury

The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the

Please wrap commit message according to Linux coding style / submission process:
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

Best regards,
Krzysztof

Added the entries for all the files added as a part of driver support for DCC(Data Capture and Compare).

+F: Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

Quoted 5 lines · Souradeep Chowdhury

Added the entries for all the files added as a part of driver support for DCC(Data Capture and Compare).

+F: Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

arm is only for top level nodes/properties. Please put your bindings in respective subsystem.

Best regards,
Krzysztof