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Enable IPQ9754 USB

PATCH Superseded Varadarajan Narayanan 4 participants 22 messages May 5, 2023 – May 8, 2023

Subsystems (7)
Device tree bindings USB Arm Qualcomm mailing list Common clk +3 more subsystems

v10 of 15 Superseded Latest is v15 →

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Varadarajan Narayanan

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#0 lore raw

v10 cover Enable IPQ9754 USB

This patch series adds the relevant phy and controller configurations for enabling USB on IPQ9754

Depends on:
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/lkml/[email protected]/T/

[v10]:
- Fix regulator definitions
- Address couple of other comments

[v9]:
- Update bindings to make power-domains as optional since IPQ9574 doesn't have GDSCs

[v8]:
- Update bindings for the clock name change
[v7]:
- com_aux -> cfg_ahb in patch 7

[v6]:
- Incorporated review comments
- Resolve make dtbs_check messages
- Fixed pcs_usb offset
- Board dts file name changed

[v5]:
- Incorporated review comments
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

- Move qmp phy DT node to newer specification

[v4]:
- Incorporated review comments
- Address all 'make dtbs_check' errors

[v3]:
- Incorporated review comments regarding coding style

[v2]:
- Incorporated review comments regarding coding style, maintaining sorted order of entries and unused phy register offsets
- Removed NOC clock entries from DT node (will be implemented later with interconnect support)
- Fixed 'make dtbs_check' errors/warnings

[v1]:

        https://lore.kernel.org/linux-arm-msm/[email protected]/T/

Varadarajan Narayanan (9):
dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
dt-bindings: usb: dwc3: Add IPQ9574 compatible
clk: qcom: gcc-ipq9574: Add USB related clocks
phy: qcom-qusb2: add QUSB2 support for IPQ9574
phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
arm64: dts: qcom: ipq9574: Add USB related nodes
arm64: dts: qcom: ipq9574: Add LDO regulator node
arm64: dts: qcom: ipq9574: Enable USB

 .../devicetree/bindings/phy/qcom,qusb2-phy.yaml    |   3 +-
 .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml        |  41 ++++++--
 .../devicetree/bindings/usb/qcom,dwc3.yaml         |   3 +-
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts        |  30 ++++++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi              | 104 +++++++++++++++++++
 drivers/clk/qcom/gcc-ipq9574.c                     |  37 +++++++
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c            | 115 +++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qusb2.c              |   3 +
 include/dt-bindings/clock/qcom,ipq9574-gcc.h       |   2 +
 9 files changed, 330 insertions(+), 8 deletions(-)
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#1 lore raw

PATCH v10 1/9 dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible

Document the compatible string used for the qusb2 phy in IPQ9574.

Acked-by Krzysztof Kozlowski <[email protected]>
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v5:
- Undo v4 changes

Changes in v4:
- Remove constraints not applicable to IPQ9574

Changes in v3:
- Maintain the proper sorted order

Changes in v2:
- Moved ipq6018 to the proper place and placed ipq9574 next to it as suggested by Dmitry

---
 Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +2 -1
index 543c1a2..95eecba 100644
@@ -18,13 +18,14 @@ properties:
     oneOf:
       - items:
           - enum:
+              - qcom,ipq6018-qusb2-phy
               - qcom,ipq8074-qusb2-phy
+              - qcom,ipq9574-qusb2-phy
               - qcom,msm8953-qusb2-phy
               - qcom,msm8996-qusb2-phy
               - qcom,msm8998-qusb2-phy
               - qcom,qcm2290-qusb2-phy
               - qcom,sdm660-qusb2-phy
-              - qcom,ipq6018-qusb2-phy
               - qcom,sm4250-qusb2-phy
               - qcom,sm6115-qusb2-phy
       - items:
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#2 lore raw

PATCH v10 2/9 dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY

In reply to Varadarajan Narayanan

* Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574

* Making power-domains as optional since IPQ9574 doesn't have GDSCs

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Remove maxItems for clocks as it is present in top level

Changes in v9:
- Move 'allOf' to the correct position

Changes in v8:
- Update clock names for ipq9574

Changes in v6:
- Made power-domains optional

Note: In the earlier patch sets, had used the (legacy) specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml

---
 .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml        | 41 ++++++++++++++++++----
 1 file changed, 35 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +35 -6
index 16fce10..6982ac3 100644
@@ -16,6 +16,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,ipq9574-qmp-usb3-phy
       - qcom,sc8280xp-qmp-usb3-uni-phy
 
   reg:

@@ -25,11 +26,7 @@ properties:
     maxItems: 4
 
   clock-names:
-    items:
-      - const: aux
-      - const: ref
-      - const: com_aux
-      - const: pipe
+    maxItems: 4
 
   power-domains:
     maxItems: 1

@@ -60,7 +57,6 @@ required:
   - reg
   - clocks
   - clock-names
-  - power-domains
   - resets
   - reset-names
   - vdda-phy-supply

@@ -69,6 +65,39 @@ required:
   - clock-output-names
   - "#phy-cells"
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq9574-qmp-usb3-phy
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: aux
+            - const: ref
+            - const: cfg_ahb
+            - const: pipe
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc8280xp-qmp-usb3-uni-phy
+    then:
+      properties:
+        clocks:
+          maxItems: 4
+        clock-names:
+          items:
+            - const: aux
+            - const: ref
+            - const: com_aux
+            - const: pipe
+
 additionalProperties: false
 
 examples:
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#3 lore raw

Re: [PATCH v10 2/9] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY

Quoted 29 lines · Varadarajan Narayanan

* Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574

* Making power-domains as optional since IPQ9574 doesn't have GDSCs

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +22 -0
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq9574-qmp-usb3-phy
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: aux
+            - const: ref
+            - const: cfg_ahb
+            - const: pipe
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc8280xp-qmp-usb3-uni-phy

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml required: · line 99

Quoted 10 lines
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +10 -0
+    then:
+      properties:
+        clocks:
+          maxItems: 4
+        clock-names:
+          items:
+            - const: aux
+            - const: ref
+            - const: com_aux
+            - const: pipe

required:
- power-domains

Best regards,
Krzysztof

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#4 lore raw

PATCH v10 3/9 dt-bindings: usb: dwc3: Add IPQ9574 compatible

In reply to Varadarajan Narayanan

* Document the IPQ9574 dwc3 compatible.

* Make power-domains as optional since IPQ9574 doesn't have GDSCs

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v9:
- Place ipq9574 alongwith similar SoCs instead of new entry
- Make power-domains as optional since IPQ9574 doesn't have GDSCs

Changes in v6:
- Made power-domains as optional
- Resolved all 'make dtbs_check' messages

Changes in v5:
- Restore removed constraints

Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574

---
 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +2 -1
index d842819..5c13229 100644
@@ -17,6 +17,7 @@ properties:
           - qcom,ipq6018-dwc3
           - qcom,ipq8064-dwc3
           - qcom,ipq8074-dwc3
+          - qcom,ipq9574-dwc3
           - qcom,msm8953-dwc3
           - qcom,msm8994-dwc3
           - qcom,msm8996-dwc3

@@ -133,7 +134,6 @@ required:
   - "#address-cells"
   - "#size-cells"
   - ranges
-  - power-domains
   - clocks
   - clock-names
   - interrupts

@@ -177,6 +177,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,ipq9574-dwc3
               - qcom,msm8953-dwc3
               - qcom,msm8996-dwc3
               - qcom,msm8998-dwc3
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#5 lore raw

PATCH v10 4/9 clk: qcom: gcc-ipq9574: Add USB related clocks

In reply to Varadarajan Narayanan

Add the clocks needed for enabling USB in IPQ9574

Reviewed-by Dmitry Baryshkov <[email protected]>
Acked-by Stephen Boyd <[email protected]>
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add 'const' for .hw.init = &(struct clk_init_data)

Changes in v2:
- Fixed coding style issues

---
 drivers/clk/qcom/gcc-ipq9574.c               | 37 ++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,ipq9574-gcc.h |  2 ++
 2 files changed, 39 insertions(+)
drivers/clk/qcom/gcc-ipq9574.c +37 -0
index a4cf750..6869e8e 100644
@@ -2025,6 +2025,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
 	},
 };
 
+static struct clk_branch gcc_usb0_pipe_clk = {
+	.halt_reg = 0x2c054,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x2c054,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data){
+			.name = "gcc_usb0_pipe_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+				&usb0_pipe_clk_src.clkr.hw
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+	.halt_reg = 0x2c058,
+	.clkr = {
+		.enable_reg = 0x2c058,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data){
+			.name = "gcc_usb0_sleep_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+				&gcc_sleep_clk_src.clkr.hw
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
 	F(144000, P_XO, 16, 12, 125),
 	F(400000, P_XO, 12, 1, 5),

@@ -3985,6 +4020,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
 	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
 	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
 	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
 	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
 	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
 	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
include/dt-bindings/clock/qcom,ipq9574-gcc.h +2 -0
index 2d7b460..2cb02f7 100644
@@ -214,4 +214,6 @@
 #define GCC_PCIE1_PIPE_CLK				205
 #define GCC_PCIE2_PIPE_CLK				206
 #define GCC_PCIE3_PIPE_CLK				207
+#define GCC_USB0_PIPE_CLK				208
+#define GCC_USB0_SLEEP_CLK				209
 #endif
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#6 lore raw

PATCH v10 5/9 phy: qcom-qusb2: add QUSB2 support for IPQ9574

In reply to Varadarajan Narayanan

Add the phy init sequence for the Super Speed ports found on IPQ9574.

Reviewed-by Dmitry Baryshkov <[email protected]>
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v2:
- Place the entry such that the list continues to be sorted

---
 drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/phy/qualcomm/phy-qcom-qusb2.c +3 -0
index 2ef638b..bec6e40 100644
@@ -912,6 +912,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
 		.compatible	= "qcom,ipq8074-qusb2-phy",
 		.data		= &msm8996_phy_cfg,
 	}, {
+		.compatible	= "qcom,ipq9574-qusb2-phy",
+		.data		= &ipq6018_phy_cfg,
+	}, {
 		.compatible	= "qcom,msm8953-qusb2-phy",
 		.data		= &msm8996_phy_cfg,
 	}, {
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#7 lore raw

PATCH v10 6/9 phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence

In reply to Varadarajan Narayanan

Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.

Signed-off-by Praveenkumar I <[email protected]>
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v6:
- Fix pcs_usb offset
- Use correct clock names array
Changes in v5:
- Fix additional review comments
- Use V3 register offsets
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order

---
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)
drivers/phy/qualcomm/phy-qcom-qmp-usb.c +115 -0
index a49711c..11a76a4 100644
@@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 };
 
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+	/* PLL and Loop filter settings */
+	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+	/* SSC settings */
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+	QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

@@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
 	"vdda-phy", "vdda-pll",
 };
 
+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
+	.serdes		= 0,
+	.pcs		= 0x800,
+	.pcs_usb	= 0x800,
+	.tx		= 0x200,
+	.rx		= 0x400,
+};
+
 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
 	.serdes		= 0,
 	.pcs		= 0x0200,

@@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
 	.regs			= qmp_v3_usb3phy_regs_layout,
 };
 
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+	.lanes			= 1,
+
+	.offsets		= &qmp_usb_offsets_ipq9574,
+
+	.serdes_tbl		= ipq9574_usb3_serdes_tbl,
+	.serdes_tbl_num		= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+	.tx_tbl			= ipq9574_usb3_tx_tbl,
+	.tx_tbl_num		= ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+	.rx_tbl			= ipq9574_usb3_rx_tbl,
+	.rx_tbl_num		= ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+	.pcs_tbl		= ipq9574_usb3_pcs_tbl,
+	.pcs_tbl_num		= ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+	.clk_list		= msm8996_phy_clk_l,
+	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
+	.reset_list		= qcm2290_usb3phy_reset_l,
+	.num_resets		= ARRAY_SIZE(qcm2290_usb3phy_reset_l),
+	.vreg_list		= qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
+	.regs			= qmp_v3_usb3phy_regs_layout,
+};
+
 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
 	.lanes			= 1,
 

@@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
 		.compatible = "qcom,ipq8074-qmp-usb3-phy",
 		.data = &ipq8074_usb3phy_cfg,
 	}, {
+		.compatible = "qcom,ipq9574-qmp-usb3-phy",
+		.data = &ipq9574_usb3phy_cfg,
+	}, {
 		.compatible = "qcom,msm8996-qmp-usb3-phy",
 		.data = &msm8996_usb3phy_cfg,
 	}, {
Signature · 7 lines
2.7.4


-- 
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Reviewed-by on v10 6/9
#8 lore raw

Re: [PATCH v10 6/9] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence

Quoted 21 lines · Varadarajan Narayanan

Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets.

Signed-off-by Praveenkumar I <[email protected]>
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v6:
- Fix pcs_usb offset
- Use correct clock names array
Changes in v5:
- Fix additional review comments
- Use V3 register offsets
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order

Quoted 4 lines
---
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)
Reviewed-by Dmitry Baryshkov <[email protected]>

--
With best wishes
Dmitry

author
#9 lore raw

PATCH v10 7/9 arm64: dts: qcom: ipq9574: Add USB related nodes

In reply to Varadarajan Narayanan

Add USB phy and controller related nodes

SS PHY need two supplies and HS PHY needs three supplies. 0.925V and 3.3V are from fixed regulators and 1.8V is generated from PMIC's LDO

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Fix regulator definitions
Changes in v8:
- Change clocks order to match the bindings
Changes in v7:
- Change com_aux -> cfg_ahb
Changes in v6:
- Introduce fixed regulators for the phy
- Resolved all 'make dtbs_check' messages

Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues

Changes in v3:
- Insert the nodes at proper location

Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)

---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 104 ++++++++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574.dtsi +104 -0
index 93b4ba9..84b80cc 100644
@@ -150,6 +150,24 @@
 		method = "smc";
 	};
 
+	fixed_3p3: s3300 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "fixed_3p3";
+	};
+
+	fixed_0p925: s0925 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <925000>;
+		regulator-max-microvolt = <925000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "fixed_0p925";
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -191,6 +209,45 @@
 			reg = <0x00060000 0x6000>;
 		};
 
+		usb_0_qusbphy: phy@7b000 {
+			compatible = "qcom,ipq9574-qusb2-phy";
+			reg = <0x0007b000 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&xo_board_clk>;
+			clock-names = "cfg_ahb",
+				      "ref";
+
+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+			status = "disabled";
+		};
+
+		usb_0_qmpphy: phy@7d000 {
+			compatible = "qcom,ipq9574-qmp-usb3-phy";
+			reg = <0x0007d000 0xa00>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB0_AUX_CLK>,
+				 <&xo_board_clk>,
+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB0_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "cfg_ahb",
+				      "pipe";
+
+			resets = <&gcc GCC_USB0_PHY_BCR>,
+				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_phy";
+
+			status = "disabled";
+
+			#clock-cells = <0>;
+			clock-output-names = "usb0_pipe_clk";
+		};
+
 		pcie0_phy: phy@84000 {
 			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
 			reg = <0x00084000 0x1000>;

@@ -560,6 +617,53 @@
 			status = "disabled";
 		};
 
+		usb3: usb@8a00000 {
+			compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+			reg = <0x08af8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_SNOC_USB_CLK>,
+				 <&gcc GCC_USB0_MASTER_CLK>,
+				 <&gcc GCC_ANOC_USB_AXI_CLK>,
+				 <&gcc GCC_USB0_SLEEP_CLK>,
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <200000000>,
+					       <24000000>;
+
+			interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event";
+
+			resets = <&gcc GCC_USB_BCR>;
+			status = "disabled";
+
+			dwc_0: usb@8a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x8a00000 0xcd00>;
+				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				clock-names = "ref";
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				dr_mode = "host";
+			};
+		};
+
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
 			reg = <0x0b000000 0x1000>,  /* GICD */
Signature · 7 lines
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-- 
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Reviewed-by on v10 7/9
#10 lore raw

Re: [PATCH v10 7/9] arm64: dts: qcom: ipq9574: Add USB related nodes

Quoted 146 lines · Varadarajan Narayanan

Add USB phy and controller related nodes

SS PHY need two supplies and HS PHY needs three supplies. 0.925V and 3.3V are from fixed regulators and 1.8V is generated from PMIC's LDO

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Fix regulator definitions
Changes in v8:
- Change clocks order to match the bindings
Changes in v7:
- Change com_aux -> cfg_ahb
Changes in v6:
- Introduce fixed regulators for the phy
- Resolved all 'make dtbs_check' messages

Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues

Changes in v3:
- Insert the nodes at proper location

Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)

---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 104 ++++++++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574.dtsi +78 -0
index 93b4ba9..84b80cc 100644
@@ -150,6 +150,24 @@
                method = "smc";
        };
 
+       fixed_3p3: s3300 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "fixed_3p3";
+       };
+
+       fixed_0p925: s0925 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <925000>;
+               regulator-max-microvolt = <925000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "fixed_0p925";
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;

@@ -191,6 +209,45 @@
                        reg = <0x00060000 0x6000>;
                };
 
+               usb_0_qusbphy: phy@7b000 {
+                       compatible = "qcom,ipq9574-qusb2-phy";
+                       reg = <0x0007b000 0x180>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&xo_board_clk>;
+                       clock-names = "cfg_ahb",
+                                     "ref";
+
+                       resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+                       status = "disabled";
+               };
+
+               usb_0_qmpphy: phy@7d000 {
+                       compatible = "qcom,ipq9574-qmp-usb3-phy";
+                       reg = <0x0007d000 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board_clk>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "cfg_ahb",
+                                     "pipe";
+
+                       resets = <&gcc GCC_USB0_PHY_BCR>,
+                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_phy";
+
+                       status = "disabled";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb0_pipe_clk";
+               };
+
                pcie0_phy: phy@84000 {
                        compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
                        reg = <0x00084000 0x1000>;

@@ -560,6 +617,53 @@
                        status = "disabled";
                };
 
+               usb3: usb@8a00000 {
+                       compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+                       reg = <0x08af8800 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       clocks = <&gcc GCC_SNOC_USB_CLK>,
+                                <&gcc GCC_USB0_MASTER_CLK>,
+                                <&gcc GCC_ANOC_USB_AXI_CLK>,
+                                <&gcc GCC_USB0_SLEEP_CLK>,
+                                <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+                       clock-names = "cfg_noc",
+                                     "core",
+                                     "iface",
+                                     "sleep",
+                                     "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+                                         <&gcc GCC_USB0_MOCK_UTMI_CLK>;

arch/arm64/boot/dts/qcom/ipq9574.dtsi line 650

Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +10 -0
+                       assigned-clock-rates = <200000000>,
+                                              <24000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event";
+
+                       resets = <&gcc GCC_USB_BCR>;
+                       status = "disabled";
+
+                       dwc_0: usb@8a00000 {

As I wrote in the other email, this better have the usb_0_dwc3 alias. With that fixed:

Reviewed-by Dmitry Baryshkov <[email protected]>
Quoted 22 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +16 -1
+                               compatible = "snps,dwc3";
+                               reg = <0x8a00000 0xcd00>;
+                               clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                               clock-names = "ref";
+                               interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               tx-fifo-resize;
+                               snps,is-utmi-l1-suspend;
+                               snps,hird-threshold = /bits/ 8 <0x0>;
+                               snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
+                               dr_mode = "host";
+                       };
+               };
+
                intc: interrupt-controller@b000000 {
                        compatible = "qcom,msm-qgic2";
                        reg = <0x0b000000 0x1000>,  /* GICD */
--

2.7.4

Signature · 2 lines
With best wishes
Dmitry
author
#11 lore raw

Re: [PATCH v10 7/9] arm64: dts: qcom: ipq9574: Add USB related nodes

Quoted 162 lines · Dmitry Baryshkov
Quoted 146 lines · Varadarajan Narayanan

Add USB phy and controller related nodes

SS PHY need two supplies and HS PHY needs three supplies. 0.925V and 3.3V are from fixed regulators and 1.8V is generated from PMIC's LDO

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Fix regulator definitions
Changes in v8:
- Change clocks order to match the bindings
Changes in v7:
- Change com_aux -> cfg_ahb
Changes in v6:
- Introduce fixed regulators for the phy
- Resolved all 'make dtbs_check' messages

Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok

/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues

Changes in v3:
- Insert the nodes at proper location

Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper interconnect support)

---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 104 ++++++++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574.dtsi +78 -0
index 93b4ba9..84b80cc 100644
@@ -150,6 +150,24 @@
                method = "smc";
        };
 
+       fixed_3p3: s3300 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "fixed_3p3";
+       };
+
+       fixed_0p925: s0925 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <925000>;
+               regulator-max-microvolt = <925000>;
+               regulator-boot-on;
+               regulator-always-on;
+               regulator-name = "fixed_0p925";
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;

@@ -191,6 +209,45 @@
                        reg = <0x00060000 0x6000>;
                };
 
+               usb_0_qusbphy: phy@7b000 {
+                       compatible = "qcom,ipq9574-qusb2-phy";
+                       reg = <0x0007b000 0x180>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&xo_board_clk>;
+                       clock-names = "cfg_ahb",
+                                     "ref";
+
+                       resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+                       status = "disabled";
+               };
+
+               usb_0_qmpphy: phy@7d000 {
+                       compatible = "qcom,ipq9574-qmp-usb3-phy";
+                       reg = <0x0007d000 0xa00>;
+                       #phy-cells = <0>;
+
+                       clocks = <&gcc GCC_USB0_AUX_CLK>,
+                                <&xo_board_clk>,
+                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                                <&gcc GCC_USB0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "cfg_ahb",
+                                     "pipe";
+
+                       resets = <&gcc GCC_USB0_PHY_BCR>,
+                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_phy";
+
+                       status = "disabled";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb0_pipe_clk";
+               };
+
                pcie0_phy: phy@84000 {
                        compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
                        reg = <0x00084000 0x1000>;

@@ -560,6 +617,53 @@
                        status = "disabled";
                };
 
+               usb3: usb@8a00000 {
+                       compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+                       reg = <0x08af8800 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       clocks = <&gcc GCC_SNOC_USB_CLK>,
+                                <&gcc GCC_USB0_MASTER_CLK>,
+                                <&gcc GCC_ANOC_USB_AXI_CLK>,
+                                <&gcc GCC_USB0_SLEEP_CLK>,
+                                <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+                       clock-names = "cfg_noc",
+                                     "core",
+                                     "iface",
+                                     "sleep",
+                                     "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+                                         <&gcc GCC_USB0_MOCK_UTMI_CLK>;

arch/arm64/boot/dts/qcom/ipq9574.dtsi line 650

Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +10 -0
+                       assigned-clock-rates = <200000000>,
+                                              <24000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event";
+
+                       resets = <&gcc GCC_USB_BCR>;
+                       status = "disabled";
+
+                       dwc_0: usb@8a00000 {

As I wrote in the other email, this better have the usb_0_dwc3 alias. With that fixed:

Quoted 1 line
Reviewed-by Dmitry Baryshkov <[email protected]>

Sure. Will rename it and send a revised version.

Thanks
Varada

Quoted 27 lines
Quoted 20 lines
arch/arm64/boot/dts/qcom/ipq9574.dtsi +16 -1
+                               compatible = "snps,dwc3";
+                               reg = <0x8a00000 0xcd00>;
+                               clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+                               clock-names = "ref";
+                               interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               tx-fifo-resize;
+                               snps,is-utmi-l1-suspend;
+                               snps,hird-threshold = /bits/ 8 <0x0>;
+                               snps,dis_u2_susphy_quirk;
+                               snps,dis_u3_susphy_quirk;
+                               dr_mode = "host";
+                       };
+               };
+
                intc: interrupt-controller@b000000 {
                        compatible = "qcom,msm-qgic2";
                        reg = <0x0b000000 0x1000>,  /* GICD */
--
Quoted 2 lines

2.7.4

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author
#12 lore raw

PATCH v10 8/9 arm64: dts: qcom: ipq9574: Add LDO regulator node

In reply to Varadarajan Narayanan

Add LDO regulator node

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -0
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
 			regulator-min-microvolt = <725000>;
 			regulator-max-microvolt = <1075000>;
 		};
+
+		mp5496_l2: l2 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
 	};
 };
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#13 lore raw

Re: [PATCH v10 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node

Quoted 2 lines · Varadarajan Narayanan

Add LDO regulator node

As this LDO is provided by the PMIC, it would be nice to know why it is modelled as an always-on regulator instead of the proper PMIC regulator. Up to now we were doing this only for the outstanding power rails like CX/MX or EBI.

Quoted 30 lines
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -1
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
                        regulator-min-microvolt = <725000>;
                        regulator-max-microvolt = <1075000>;
                };
+
+               mp5496_l2: l2 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
        };
 };
 
--

2.7.4

Signature · 2 lines
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#14 lore raw

Re: [PATCH v10 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node

Quoted 9 lines · Dmitry Baryshkov
Quoted 2 lines · Varadarajan Narayanan

Add LDO regulator node

As this LDO is provided by the PMIC, it would be nice to know why it is modelled as an always-on regulator instead of the proper PMIC regulator. Up to now we were doing this only for the outstanding power rails like CX/MX or EBI.

(which we then stopped registering as regulators and started to manage through rpm(h)pd drivers and the genpd framework)

Konrad

Quoted 33 lines
Quoted 31 lines
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -1
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
                        regulator-min-microvolt = <725000>;
                        regulator-max-microvolt = <1075000>;
                };
+
+               mp5496_l2: l2 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
        };
 };
 
--

2.7.4

#15 lore raw

Re: [PATCH v10 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node

Quoted 7 lines · Konrad Dybcio
Quoted 3 lines · Dmitry Baryshkov
Quoted 1 line · Varadarajan Narayanan
Quoted 8 lines
Quoted 6 lines
Quoted 1 line

Add LDO regulator node

As this LDO is provided by the PMIC, it would be nice to know why it is modelled as an always-on regulator instead of the proper PMIC regulator. Up to now we were doing this only for the outstanding power rails like CX/MX or EBI.

(which we then stopped registering as regulators and started to manage through rpm(h)pd drivers and the genpd framework)

I mean having regulator-fixed s4a on sm8250 in addition to the CX genpd, because some of the parts really expect to have a regulator. But anyway, we are getting away from the subj. Let's wait for the answer from Varadarajan.

Quoted 29 lines

Konrad

Quoted 27 lines
Quoted 27 lines
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -0
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
                        regulator-min-microvolt = <725000>;
                        regulator-max-microvolt = <1075000>;
                };
+
+               mp5496_l2: l2 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
        };
 };
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#16 lore raw

Re: [PATCH v10 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node

In reply to Dmitry Baryshkov
Quoted 9 lines · Dmitry Baryshkov
Quoted 2 lines · Varadarajan Narayanan

Add LDO regulator node

As this LDO is provided by the PMIC, it would be nice to know why it is modelled as an always-on regulator instead of the proper PMIC regulator. Up to now we were doing this only for the outstanding power rails like CX/MX or EBI.

These are always ON because USB phy doesn't support power collapse, and there is a chance that other IP blocks might be sharing the rail.

Thanks
Varada

Quoted 34 lines
Quoted 27 lines
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -1
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
                        regulator-min-microvolt = <725000>;
                        regulator-max-microvolt = <1075000>;
                };
+
+               mp5496_l2: l2 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
        };
 };
 
--
Quoted 2 lines

2.7.4

--
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#17 lore raw

Re: [PATCH v10 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node

Quoted 7 lines · Varadarajan Narayanan
Quoted 5 lines · Dmitry Baryshkov
Quoted 2 lines · Varadarajan Narayanan

Add LDO regulator node

Quoted 8 lines
Quoted 4 lines

As this LDO is provided by the PMIC, it would be nice to know why it is modelled as an always-on regulator instead of the proper PMIC regulator. Up to now we were doing this only for the outstanding power rails like CX/MX or EBI.

These are always ON because USB phy doesn't support power collapse, and there is a chance that other IP blocks might be sharing the rail.

You are describing the software side here. From the hardware point of view, it is an I2C regulator, which is probably also exported as an SMD_RPM regulator. Unless you have a good reason not to do so, there should be a node under rpm-requests, which describes mp5496 regulators exported via RPM. then USB should refer to those regulators.

Quoted 38 lines

Thanks
Varada

Quoted 34 lines
Quoted 27 lines
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -1
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
                        regulator-min-microvolt = <725000>;
                        regulator-max-microvolt = <1075000>;
                };
+
+               mp5496_l2: l2 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
        };
 };
 
--
Quoted 2 lines

2.7.4

--
With best wishes
Dmitry

Signature · 2 lines
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Dmitry
author
#18 lore raw

Re: [PATCH v10 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node

Quoted 18 lines · Dmitry Baryshkov
Quoted 7 lines · Varadarajan Narayanan
Quoted 5 lines · Dmitry Baryshkov
Quoted 2 lines · Varadarajan Narayanan

Add LDO regulator node

Quoted 8 lines
Quoted 4 lines

As this LDO is provided by the PMIC, it would be nice to know why it is modelled as an always-on regulator instead of the proper PMIC regulator. Up to now we were doing this only for the outstanding power rails like CX/MX or EBI.

These are always ON because USB phy doesn't support power collapse, and there is a chance that other IP blocks might be sharing the rail.

Quoted 5 lines

You are describing the software side here. From the hardware point of view, it is an I2C regulator, which is probably also exported as an SMD_RPM regulator. Unless you have a good reason not to do so, there should be a node under rpm-requests, which describes mp5496 regulators exported via RPM. then USB should refer to those regulators.

Yes. It is a part of rpm-requests. That is why have mentioned V10 is dependent on
https://lore.kernel.org/lkml/[email protected]/T/.
The 4th patch of the above series
(https://lore.kernel.org/lkml/[email protected]/T/#mea3f0ea37c53cf5e39e10cd6cf3bed5243cec629)
adds the rpm_requests node and this regulator definition is added to it. Hope that is ok.

Thanks
Varada

Quoted 40 lines
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -0
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
                        regulator-min-microvolt = <725000>;
                        regulator-max-microvolt = <1075000>;
                };
+
+               mp5496_l2: l2 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
        };
 };
Quoted 8 lines
Quoted 8 lines
Quoted 3 lines

--
2.7.4

--
With best wishes
Dmitry

--
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#19 lore raw

Re: [PATCH v10 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node

Quoted 26 lines · Varadarajan Narayanan
Quoted 18 lines · Dmitry Baryshkov
Quoted 7 lines · Varadarajan Narayanan
Quoted 5 lines · Dmitry Baryshkov
Quoted 2 lines · Varadarajan Narayanan

Add LDO regulator node

Quoted 8 lines
Quoted 4 lines

As this LDO is provided by the PMIC, it would be nice to know why it is modelled as an always-on regulator instead of the proper PMIC regulator. Up to now we were doing this only for the outstanding power rails like CX/MX or EBI.

These are always ON because USB phy doesn't support power collapse, and there is a chance that other IP blocks might be sharing the rail.

Quoted 5 lines

You are describing the software side here. From the hardware point of view, it is an I2C regulator, which is probably also exported as an SMD_RPM regulator. Unless you have a good reason not to do so, there should be a node under rpm-requests, which describes mp5496 regulators exported via RPM. then USB should refer to those regulators.

Quoted 7 lines

Yes. It is a part of rpm-requests. That is why have mentioned V10 is dependent on
https://lore.kernel.org/lkml/[email protected]/T/.
The 4th patch of the above series
(https://lore.kernel.org/lkml/[email protected]/T/#mea3f0ea37c53cf5e39e10cd6cf3bed5243cec629)
adds the rpm_requests node and this regulator definition is added to it. Hope that is ok.

It is fine. Most probably I was mistaken by the patch itself. Please excuse me. If this this is an RPM regulator, it's is fine and correct.

Quoted 44 lines

Thanks
Varada

Quoted 40 lines
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Add LDO regulator node

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +7 -0
index bdc1434..1f5d14f 100644
@@ -60,6 +60,13 @@
                        regulator-min-microvolt = <725000>;
                        regulator-max-microvolt = <1075000>;
                };
+
+               mp5496_l2: l2 {
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
        };
 };
Quoted 8 lines
Quoted 8 lines
Quoted 3 lines

--
2.7.4

--
With best wishes
Dmitry

--
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Dmitry

Signature · 2 lines
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Dmitry
author
#20 lore raw

PATCH v10 9/9 arm64: dts: qcom: ipq9574: Enable USB

In reply to Varadarajan Narayanan

Turn on USB related nodes
Provide vdd info

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Provide vdd info

Changes in v5:
- Move "host" mode specification to board dts
- Due to dependency with earlier patches board dts filename changed ipq9574-al02-c7.dts -> ipq9574-rdp433.dts

Changes in v2:
- Fix node placement and coding style
- "ok" -> "okay"

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +23 -0
index 1f5d14f..18d642c 100644
@@ -70,6 +70,10 @@
 	};
 };
 
+&dwc_0 {
+	dr_mode = "host";
+};
+
 &pcie1_phy {
 	status = "okay";
 };

@@ -122,6 +126,21 @@
 	clock-frequency = <32000>;
 };
 
+&usb_0_qmpphy {
+	vdda-pll-supply = <&mp5496_l2>;
+	vdda-phy-supply = <&fixed_0p925>;
+
+	status = "okay";
+};
+
+&usb_0_qusbphy {
+	vdd-supply = <&fixed_0p925>;
+	vdda-pll-supply = <&mp5496_l2>;
+	vdda-phy-dpdm-supply = <&fixed_3p3>;
+
+	status = "okay";
+};
+
 &tlmm {
 
 	pcie_1_pin: pcie-1-state {

@@ -188,6 +207,10 @@
 	};
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-frequency = <24000000>;
 };
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#21 lore raw

Re: [PATCH v10 9/9] arm64: dts: qcom: ipq9574: Enable USB

Quoted 26 lines · Varadarajan Narayanan

Turn on USB related nodes
Provide vdd info

Signed-off-by Varadarajan Narayanan <[email protected]>

---
Changes in v10:
- Provide vdd info

Changes in v5:
- Move "host" mode specification to board dts
- Due to dependency with earlier patches board dts filename changed ipq9574-al02-c7.dts -> ipq9574-rdp433.dts

Changes in v2:
- Fix node placement and coding style
- "ok" -> "okay"

---
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +0 -0
index 1f5d14f..18d642c 100644

arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts line 73

Quoted 4 lines
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +1 -0
@@ -70,6 +70,10 @@
        };
 };
 
+&dwc_0 {

If the node alias was usb_0_dwc3, it would have been next to the main usb_0 node. Could you please fix the alias.

Quoted 16 lines
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +9 -0
+       dr_mode = "host";
+};
+
 &pcie1_phy {
        status = "okay";
 };

@@ -122,6 +126,21 @@
        clock-frequency = <32000>;
 };
 
+&usb_0_qmpphy {
+       vdda-pll-supply = <&mp5496_l2>;
+       vdda-phy-supply = <&fixed_0p925>;
+
+       status = "okay";
+};

arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts line 144

Quoted 10 lines
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +9 -0
+
+&usb_0_qusbphy {
+       vdd-supply = <&fixed_0p925>;
+       vdda-pll-supply = <&mp5496_l2>;
+       vdda-phy-dpdm-supply = <&fixed_3p3>;
+
+       status = "okay";
+};
+
 &tlmm {

If sorted alphabetically, 'u' comes after 't', so these two chunks are out of order and should be fixed.

Quoted 16 lines
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +4 -1
        pcie_1_pin: pcie-1-state {

@@ -188,6 +207,10 @@
        };
 };
 
+&usb3 {
+       status = "okay";
+};
+
 &xo_board_clk {
        clock-frequency = <24000000>;
 };
--

2.7.4

Signature · 2 lines
With best wishes
Dmitry