Add Milk-V Pioneer RISC-V board support

The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V cores.

Reviewed-by Guo Ren <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

Acked-by Chao Wei <[email protected]>

Signed-off-by Chen Wang <[email protected]>

---
  arch/riscv/Kconfig.socs | 5 +++++
  1 file changed, 5 insertions(+)

arch/riscv/Kconfig.socs +5 -0

index 6833d01e2e70..d4df7b5d0f16 100644
@@ -22,6 +22,11 @@ config SOC_SIFIVE
  	help
  	  This enables support for SiFive SoC platform hardware.
 
+config ARCH_SOPHGO
+	bool "Sophgo SoCs"
+	help
+	  This enables support for Sophgo SoC platform hardware.
+
  config ARCH_STARFIVE
  	def_bool SOC_STARFIVE
 

From: Chen Wang <[email protected]>

Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2] in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.

Now only support basic uart drivers to boot up into a basic console.

Thanks,
Chen

---

Changes in v4:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [6].
- Update bindings files for sg2042 clint as per intput from reviewers:
- rename filename from sophgo,sg2042-clint-mswi/sg2042-clint-mtimer to thead,c900-aclint-mswi/thead,c900-aclint-mtimer.
- rename compatible strings accordingly.
- Update dts as per input from reviewers: don't use macro for cpus's isa properties; use new compatible strings for mtimer/mswi of clint.
- Use only one email-address for SoB.

Changes in v3 [v3]:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.

Changes in v2 [v2]:
The patch series is based on v6.6-rc1. You can simply review or test the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may add it later if really needed.

Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread, I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or test the patches at the link [3].

[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[6]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v4
[v1-0/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-1/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-2/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-3/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-4/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-5/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-6/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-7/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-8/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-9/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-10/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-11/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v1-12/12]:https://lore.kernel.org/linux-riscv/[email protected]/ [v2]:https://lore.kernel.org/linux-riscv/[email protected]/ [v3]:https://lore.kernel.org/linux-riscv/[email protected]/

---

Chen Wang (8):
riscv: Add SOPHGO SOC family Kconfig support
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoC

Inochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi

 .../sifive,plic-1.0.0.yaml                    |    1 +
 .../thead,c900-aclint-mswi.yaml               |   43 +
 .../devicetree/bindings/riscv/cpus.yaml       |    1 +
 .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
 .../timer/thead,c900-aclint-mtimer.yaml       |   43 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
 MAINTAINERS                                   |    7 +
 arch/riscv/Kconfig.socs                       |    5 +
 arch/riscv/boot/dts/Makefile                  |    1 +
 arch/riscv/boot/dts/sophgo/Makefile           |    3 +
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 2000 +++++++++++++++++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  325 +++
 arch/riscv/configs/defconfig                  |    1 +
 14 files changed, 2481 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d --
2.25.1

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