arm64: zynqmp: Some DT alignment
Subsystems (2)
Michal Simek
maintainercover arm64: zynqmp: Some DT alignment
Hi,
I am sending couple of patches to update DTs for current ZynqMP boards. All should be aligned with the latest DT binding and should also solve all build issues reported by W=1.
Thanks,
Michal
Ilias Apalodimas (1):
arm64: zynqmp: Add an OP-TEE node to the device tree
Michal Simek (9):
arm64: xilinx: Move address/size-cells to proper locations
arm64: zynqmp: Setup default si570 frequency to 156.25MHz
arm64: zynqmp: Describe assigned-clocks for uarts
arm64: zynqmp: Fix comment to be aligned with board name.
arm64: zynqmp: Introduce u-boot options node with bootscr-address
arm64: zynqmp: Remove incorrect comment from kv260s
arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp
arm64: zynqmp: Comment all smmu entries
arm64: zynqmp: Align usb clock nodes with binding
Neal Frager (1):
arm64: zynqmp: Add output-enable pins to SOMs
Srinivas Neeli (1):
arm64: zynqmp: Add resets property for CAN nodes
Tejas Bhumkar (1):
arm64: zynqmp: Disable Tri-state for MIO38 Pin
Thippeswamy Havalige (1):
arm64: zynqmp: Update ECAM size to discover up to 256 buses
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 16 ++- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 36 ++++++- .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 37 ++++++- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 6 ++ .../boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 + .../boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 + .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 6 +- .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 10 +- .../dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 2 + .../dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 + .../dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 12 ++- .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 6 +- .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 6 +- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 12 ++- .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 10 +- .../boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 4 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 97 ++++++++++--------- 19 files changed, 204 insertions(+), 70 deletions(-)
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 1/14 arm64: xilinx: Move address/size-cells to proper locations
Move cells to board dtsi files from generic zynqmp.dtsi. Changes are related to qspi, spi, nand, i2c and ethernet
address cells
make -j8 W=1 dtbs
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 ++ .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 ++++ .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 8 ++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 2 ++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 14 -------------- 15 files changed, 56 insertions(+), 14 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +6 -0
@@ -129,6 +129,8 @@ mux { }; &qspi { /* MIO 0-5 - U143 */ + #address-cells = <1>; + #size-cells = <0>; status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ compatible = "jedec,spi-nor"; /* 64MB */
@@ -240,6 +242,8 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ }; &spi1 { /* MIO6, 9-11 */ + #address-cells = <1>; + #size-cells = <0>; status = "okay"; label = "TPM"; num-cs = <1>;
@@ -251,6 +255,8 @@ tpm@0 { /* slm9670 - U144 */ }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; bootph-all; clock-frequency = <400000>;
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +2 -0
@@ -38,6 +38,8 @@ &dcc { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +2 -0
@@ -39,6 +39,8 @@ &dcc { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +4 -0
@@ -118,6 +118,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -353,6 +355,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +8 -0
@@ -109,6 +109,8 @@ &gpio { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -132,6 +134,8 @@ rtc@68 { }; &nand0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>;
@@ -444,6 +448,8 @@ &rtc { }; &spi0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; num-cs = <1>; pinctrl-names = "default";
@@ -464,6 +470,8 @@ partition@0 { }; &spi1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; num-cs = <1>; pinctrl-names = "default";
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +2 -0
@@ -103,6 +103,8 @@ &gpio { /* just eeprom here */ &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>;
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +2 -0
@@ -171,6 +171,8 @@ &i2c1 { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +2 -0
@@ -176,6 +176,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>;
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +6 -0
@@ -228,6 +228,8 @@ &gpu { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -492,6 +494,8 @@ max20751@73 { /* u96 */ }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -951,6 +955,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +4 -0
@@ -135,6 +135,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -438,6 +440,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +4 -0
@@ -140,6 +140,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -450,6 +452,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +6 -0
@@ -240,6 +240,8 @@ &gpu { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -503,6 +505,8 @@ max20751@73 { /* u96 */ }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -958,6 +962,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +6 -0
@@ -200,6 +200,8 @@ &gpu { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -380,6 +382,8 @@ i2c@3 { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio";
@@ -788,6 +792,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +2 -0
@@ -43,6 +43,8 @@ &gpio { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor";
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +0 -14
@@ -571,8 +571,6 @@ nand0: nand-controller@ff100000 { clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; };
@@ -653,8 +651,6 @@ i2c0: i2c@ff020000 { interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; };
@@ -665,8 +661,6 @@ i2c1: i2c@ff030000 { interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; };
@@ -718,8 +712,6 @@ qspi: spi@ff0f0000 { num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; };
@@ -819,8 +811,6 @@ spi0: spi@ff040000 { interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; };
@@ -831,8 +821,6 @@ spi1: spi@ff050000 { interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; };
@@ -1005,8 +993,6 @@ ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; - #address-cells = <1>; - #size-cells = <0>; }; };
Signature · 1 line
2.36.1
Re: [PATCH 01/14] arm64: xilinx: Move address/size-cells to proper locations
Quoted 6 lines · Michal Simek
Move cells to board dtsi files from generic
zynqmp.dtsi. Changes are related to qspi, spi, nand, i2c and ethernet
address cellsmake -j8 W=1 dtbs
I don't think this is an improvement. The warnings are guidance, not 100% rule.
Quoted 20 lines
Signed-off-by Michal Simek <[email protected]>---
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 ++ .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 ++++ .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 8 ++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 2 ++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 14 -------------- 15 files changed, 56 insertions(+), 14 deletions(-)
Michal Simek
maintainerPATCH 2/14 arm64: zynqmp: Add output-enable pins to SOMs
In reply to Michal SimekFrom: Neal Frager <[email protected]>
Now that the zynqmp pinctrl driver supports the tri-state registers, make sure that the pins requiring output-enable are configured appropriately for SOMs.
Without it, all tristate setting for MIOs, which are not related to SOM itself, are using default configuration which is not correct setting. It means SDs, USBs, ethernet, etc. are not working properly.
In past it was fixed through calling tristate configuration via bootcmd:
usb_init=mw 0xFF180208 2020
kv260_gem3=mw 0xFF18020C 0xFC0 && gpio toggle gpio@ff0a000038 && \
gpio toggle gpio@ff0a000038
Signed-off-by Neal Frager <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 5 +++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 5 +++++ 2 files changed, 10 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +5 -0
@@ -185,6 +185,7 @@ conf-rx { conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux {
@@ -236,6 +237,7 @@ conf-rx { conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; };
@@ -243,6 +245,7 @@ conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; };
@@ -251,6 +254,7 @@ conf-mdio { slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; mux-mdio {
@@ -281,6 +285,7 @@ conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; };
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +5 -0
@@ -168,6 +168,7 @@ conf-rx { conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux {
@@ -219,6 +220,7 @@ conf-rx { conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; };
@@ -226,6 +228,7 @@ conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; };
@@ -234,6 +237,7 @@ conf-mdio { slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; mux-mdio {
@@ -264,6 +268,7 @@ conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; };
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 3/14 arm64: zynqmp: Add an OP-TEE node to the device tree
In reply to Michal SimekFrom: Ilias Apalodimas <[email protected]>
Since the zynqmp boards can run upstream OP-TEE, and having the DT node present doesn't cause any side effects add it in case someone tries to load OP-TEE.
Signed-off-by Ilias Apalodimas <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +5 -0
@@ -180,6 +180,11 @@ psci { }; firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>;
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 4/14 arm64: zynqmp: Add resets property for CAN nodes
In reply to Michal SimekFrom: Srinivas Neeli <[email protected]>
Added resets property for CAN nodes.
Signed-off-by Srinivas Neeli <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +2 -0
@@ -286,6 +286,7 @@ can0: can@ff060000 { interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; };
@@ -298,6 +299,7 @@ can1: can@ff070000 { interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; };
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 5/14 arm64: zynqmp: Setup default si570 frequency to 156.25MHz
In reply to Michal SimekAll si570 mgt chips have factory default 156.25MHz but DT changed it to 148.5MHz. After tracking it is pretty much c&p fault taken from Zynq zc702/zc706 boards where 148.5MHz was setup as default because it was requirement for AD7511 chip available on these boards.
ZynqMP board don't contain this chip that's why factory default frequency can be used.
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +1 -1
@@ -607,7 +607,7 @@ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; };
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +1 -1
@@ -609,7 +609,7 @@ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; };
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 6/14 arm64: zynqmp: Describe assigned-clocks for uarts
In reply to Michal SimekDescribe assigned-clocks for both uarts. SOM is using this functionality.
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +2 -0
@@ -230,10 +230,12 @@ &ttc3 { &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART0_REF>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART1_REF>; }; &dwc3_0 {
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 7/14 arm64: zynqmp: Update ECAM size to discover up to 256 buses
In reply to Michal SimekFrom: Thippeswamy Havalige <[email protected]>
Update ECAM size to discover up to 256 buses.
Signed-off-by Thippeswamy Havalige <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +1 -1
@@ -690,7 +690,7 @@ pcie: pcie@fd0e0000 { msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 8/14 arm64: zynqmp: Fix comment to be aligned with board name.
In reply to Michal SimekThe board was renamed from zc1275 to zcu1275 but name in comment wasn't updated.
Fixes 370b0e900fb0 ("arm64: zynqmp: Change zc1275 board name to zcu1275")
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +1 -1
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * dts file for Xilinx ZynqMP ZC1275 + * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017 - 2021, Xilinx, Inc. *
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 9/14 arm64: zynqmp: Introduce u-boot options node with bootscr-address
In reply to Michal SimekAdd u-boot options node with details about bootscr-address. c&p description from dtschema/schemas/options/u-boot.yaml:
"Holds the full address of the boot script file. It helps in making automated flow easier by fetching the 64bit address directly from DT. Value should be automatically copied to the U-Boot 'scriptaddr' variable. When it is defined, bootscr-ram-offset property should be ignored. Actually only one of them should be present in the DT."
Address is generic for all zynqmp boards because all of them have DDR starting from 0. Custom boards should revisit the location and aligned it based on their needs.
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +7 -0
@@ -24,6 +24,13 @@ / { #address-cells = <2>; #size-cells = <2>; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>;
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 10/14 arm64: zynqmp: Remove incorrect comment from kv260s
In reply to Michal SimekRemove incorrect comment about required nodes by spec. In past gem3 was the part of SOM specification but it has been revisit by introducting KR260.
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +2 -2
@@ -139,7 +139,7 @@ &sdhci1 { /* on CC with tuned parameters */ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>;
@@ -166,7 +166,7 @@ phy0: ethernet-phy@1 { }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default {
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +2 -2
@@ -122,7 +122,7 @@ &sdhci1 { /* on CC with tuned parameters */ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>;
@@ -149,7 +149,7 @@ phy0: ethernet-phy@1 { }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default {
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 11/14 arm64: zynqmp: Disable Tri-state for MIO38 Pin
In reply to Michal SimekFrom: Tejas Bhumkar <[email protected]>
gpio38 is used in SOM's kv260 to reset the Ethernet PHY. At present, HW reset is not working properly as Tri-state is enabled for MIO38, causing inappropriate PHY register reads.
Disabled Tri-state for MIO38 to make HW reset work.
Tri-state disable :
ZynqMP> md 0xFF180208 2ff180208: 00bfe7a3 00000540
Tri-state enable :
ZynqMP> md 0xFF180208 2ff180208: 00bfe7e3 00000540
Signed-off-by Tejas Bhumkar <[email protected]>
Signed-off-by Michal Simek <[email protected]>
---
.../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 25 +++++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 25 +++++++++++++++++++ 2 files changed, 50 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +25 -0
@@ -169,6 +169,25 @@ phy0: ethernet-phy@1 { &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp";
@@ -324,6 +343,12 @@ mux { }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default";
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +25 -0
@@ -152,6 +152,25 @@ phy0: ethernet-phy@1 { &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp";
@@ -307,6 +326,12 @@ mux { }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default";
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 12/14 arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp
In reply to Michal SimekAnything ending with gpio/gpios is taken as gpio phande/description which is reported as the issue coming from gpio-consumer.yaml schema. That's why rename the gpio suffix to gpio-grp to avoid name collision.
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 ++-- 11 files changed, 15 insertions(+), 15 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +1 -1
@@ -227,7 +227,7 @@ mux { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = <SLEW_RATE_SLOW>;
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +1 -1
@@ -210,7 +210,7 @@ mux { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = <SLEW_RATE_SLOW>;
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +1 -1
@@ -150,7 +150,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +1 -1
@@ -223,7 +223,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +2 -2
@@ -125,7 +125,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_74_grp", "gpio0_75_grp"; function = "gpio0";
@@ -152,7 +152,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_76_grp", "gpio0_77_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +1 -1
@@ -277,7 +277,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +2 -2
@@ -693,7 +693,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0";
@@ -720,7 +720,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +1 -1
@@ -274,7 +274,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +1 -1
@@ -286,7 +286,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +2 -2
@@ -704,7 +704,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0";
@@ -731,7 +731,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0";
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +2 -2
@@ -593,7 +593,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0";
@@ -620,7 +620,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0";
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 13/14 arm64: zynqmp: Comment all smmu entries
In reply to Michal SimekSMMU is disabled by default and not all masters can be enabled at the same time because of limited number of entries. That's why comment all iommu properties but keep them for reference in DT. In XEN case they should be added back and Xen should have SMMU enabled by default.
Also add IDs for DP and DPDMA.
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59 +++++++++++++------------- 1 file changed, 30 insertions(+), 29 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +30 -29
@@ -340,7 +340,7 @@ fpd_dma_chan1: dma-controller@fd500000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e8>; + /* iommus = <&smmu 0x14e8>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -353,7 +353,7 @@ fpd_dma_chan2: dma-controller@fd510000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e9>; + /* iommus = <&smmu 0x14e9>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -366,7 +366,7 @@ fpd_dma_chan3: dma-controller@fd520000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ea>; + /* iommus = <&smmu 0x14ea>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -379,7 +379,7 @@ fpd_dma_chan4: dma-controller@fd530000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14eb>; + /* iommus = <&smmu 0x14eb>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -392,7 +392,7 @@ fpd_dma_chan5: dma-controller@fd540000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ec>; + /* iommus = <&smmu 0x14ec>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -405,7 +405,7 @@ fpd_dma_chan6: dma-controller@fd550000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ed>; + /* iommus = <&smmu 0x14ed>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -418,7 +418,7 @@ fpd_dma_chan7: dma-controller@fd560000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ee>; + /* iommus = <&smmu 0x14ee>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -431,7 +431,7 @@ fpd_dma_chan8: dma-controller@fd570000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ef>; + /* iommus = <&smmu 0x14ef>; */ power-domains = <&zynqmp_firmware PD_GDMA>; };
@@ -476,7 +476,7 @@ lpd_dma_chan1: dma-controller@ffa80000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x868>; + /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -489,7 +489,7 @@ lpd_dma_chan2: dma-controller@ffa90000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x869>; + /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -502,7 +502,7 @@ lpd_dma_chan3: dma-controller@ffaa0000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86a>; + /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -515,7 +515,7 @@ lpd_dma_chan4: dma-controller@ffab0000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86b>; + /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -528,7 +528,7 @@ lpd_dma_chan5: dma-controller@ffac0000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86c>; + /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -541,7 +541,7 @@ lpd_dma_chan6: dma-controller@ffad0000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86d>; + /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -554,7 +554,7 @@ lpd_dma_chan7: dma-controller@ffae0000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86e>; + /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -567,7 +567,7 @@ lpd_dma_chan8: dma-controller@ffaf0000 { clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86f>; + /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; };
@@ -585,7 +585,7 @@ nand0: nand-controller@ff100000 { clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&smmu 0x872>; + /* iommus = <&smmu 0x872>; */ power-domains = <&zynqmp_firmware PD_NAND>; };
@@ -597,7 +597,7 @@ gem0: ethernet@ff0b0000 { <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x874>; + /* iommus = <&smmu 0x874>; */ power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst";
@@ -611,7 +611,7 @@ gem1: ethernet@ff0c0000 { <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x875>; + /* iommus = <&smmu 0x875>; */ power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst";
@@ -625,7 +625,7 @@ gem2: ethernet@ff0d0000 { <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x876>; + /* iommus = <&smmu 0x876>; */ power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst";
@@ -639,7 +639,7 @@ gem3: ethernet@ff0e0000 { <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x877>; + /* iommus = <&smmu 0x877>; */ power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst";
@@ -707,7 +707,7 @@ pcie: pcie@fd0e0000 { <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - iommus = <&smmu 0x4d0>; + /* iommus = <&smmu 0x4d0>; */ power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller;
@@ -726,7 +726,7 @@ qspi: spi@ff0f0000 { num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; - iommus = <&smmu 0x873>; + /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; };
@@ -758,8 +758,7 @@ sata: ahci@fd0c0000 { interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, - <&smmu 0x4c2>, <&smmu 0x4c3>; + /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ }; sdhci0: mmc@ff160000 {
@@ -770,7 +769,7 @@ sdhci0: mmc@ff160000 { interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x870>; + /* iommus = <&smmu 0x870>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>;
@@ -785,7 +784,7 @@ sdhci1: mmc@ff170000 { interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x871>; + /* iommus = <&smmu 0x871>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>;
@@ -931,7 +930,7 @@ dwc3_0: usb@fe200000 { <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clock-names = "bus_early", "ref"; - iommus = <&smmu 0x860>; + /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */
@@ -960,7 +959,7 @@ dwc3_1: usb@fe300000 { <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-names = "bus_early", "ref"; - iommus = <&smmu 0x861>; + /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */
@@ -1018,6 +1017,7 @@ zynqmp_dpdma: dma-controller@fd4c0000 { interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; + /* iommus = <&smmu 0xce4>; */ #dma-cells = <1>; };
@@ -1032,6 +1032,7 @@ zynqmp_dpsub: display@fd4a0000 { reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; + /* iommus = <&smmu 0xce3>; */ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>;
Signature · 1 line
2.36.1
Michal Simek
maintainerPATCH 14/14 arm64: zynqmp: Align usb clock nodes with binding
In reply to Michal Simekdwc3-xilinx.yaml defines 2 clocks which are not defined that's why define them (bus_early clock is moved to bus_clk in glue logic). With also describing kv260 assigned clock rates with assigned clocks. Also add missing status property to standard dwc3 core.
Signed-off-by Michal Simek <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 14 ++++++++++++-- .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++-- 3 files changed, 19 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +12 -2
@@ -238,12 +238,22 @@ &uart1 { assigned-clocks = <&zynqmp_clk UART1_REF>; }; -&dwc3_0 { +&usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; -&dwc3_1 { +&dwc3_0 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; +}; + +&usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&dwc3_1 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 {
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +1 -0
@@ -94,6 +94,7 @@ &usb0 { pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + assigned-clock-rates = <250000000>, <20000000>; }; &dwc3_0 {
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +6 -2
@@ -913,6 +913,7 @@ usb0: usb@ff9d0000 { status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
@@ -923,13 +924,14 @@ usb0: usb@ff9d0000 { dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "bus_early", "ref"; + clock-names = "ref"; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations;
@@ -943,6 +945,7 @@ usb1: usb@ff9e0000 { status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
@@ -952,13 +955,14 @@ usb1: usb@ff9e0000 { dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "bus_early", "ref"; + clock-names = "ref"; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations;
Signature · 1 line
2.36.1
Michal Simek
maintainerQuoted 48 lines · Michal Simek
Hi,
I am sending couple of patches to update DTs for current ZynqMP boards. All should be aligned with the latest DT binding and should also solve all build issues reported by W=1.
Thanks,
MichalIlias Apalodimas (1):
arm64: zynqmp: Add an OP-TEE node to the device treeMichal Simek (9):
arm64: xilinx: Move address/size-cells to proper locations
arm64: zynqmp: Setup default si570 frequency to 156.25MHz
arm64: zynqmp: Describe assigned-clocks for uarts
arm64: zynqmp: Fix comment to be aligned with board name.
arm64: zynqmp: Introduce u-boot options node with bootscr-address
arm64: zynqmp: Remove incorrect comment from kv260s
arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp
arm64: zynqmp: Comment all smmu entries
arm64: zynqmp: Align usb clock nodes with bindingNeal Frager (1):
arm64: zynqmp: Add output-enable pins to SOMsSrinivas Neeli (1):
arm64: zynqmp: Add resets property for CAN nodesTejas Bhumkar (1):
arm64: zynqmp: Disable Tri-state for MIO38 PinThippeswamy Havalige (1):
arm64: zynqmp: Update ECAM size to discover up to 256 buses.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 16 ++- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 36 ++++++- .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 37 ++++++- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 6 ++ .../boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 + .../boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 + .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 6 +- .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 10 +- .../dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 2 + .../dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 + .../dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
Quoted 9 lines
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 12 ++- .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 6 +- .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 6 +- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 12 ++- .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 10 +- .../boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 4 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 97 ++++++++++--------- 19 files changed, 204 insertions(+), 70 deletions(-)
Applied 2-14 patches. Patch 1 should be revisit based on discussion with Krzysztof here
https://lore.kernel.org/all/f2c1cae3b845d4609f8181f2dcb09a55f705667c.1704893723.git.michal.simek@amd.com/
Thanks,
Michal