Add R-Car fuse support

Hi all,

R-Car Gen3/Gen4 SoCs contain fuses indicating hardware support or hardware parameters. Unfortunately the various SoCs require different mechanisms to read the state of the fuses:
- On R-Car Gen3, the fuse monitor registers are in the middle of the Pin Function Controller (PFC) register block,
- On R-Car V3U and S4-8, the E-FUSE non-volatile memory is accessible through a separate register block in the PFC,
- On R-Car V4H and V4M, the E-FUSE non-volatile memory is accessible through the second register block of OTP_MEM.

This patch series adds support for all 3 variants. It provides an in-kernel API to read the fuses' states, as well as userspace access through the nvmem subsystem and sysfs:
- R-Car Gen3: /sys/bus/platform/devices/rcar_fuse/fuse/nvmem
- R-Car V3U/S4: /sys/bus/platform/devices/e6078800.fuse/fuse/nvmem
- R-Car V4H/V4M: /sys/bus/platform/devices/e61be000.otp/fuse/nvmem

This has been tested on R-Car H3 ES2.0, M3-W and M3-W+, M3-N, V3M, V3H and V3H2, D3, E3, V3U, S4-8 ES1.0 and ES1.2, V4H, and V4M.

For SoCs where E-FUSE is accessed through the PFC, it is not clear from the documentation if any PFC module clock needs to be enabled for fuse access. According to experiments on R-Car S4-8, the module clock and reset only impact the GPIO functionality of the PFC, not the pinmux or fuse monitor functionalities. So perhaps the clock/power-domains/resets properties should be dropped from the DT bindings and DTS, as well as the Runtime PM handling from the driver?

Changes compared to v1[1]:
- Drop RFC state and broaden audience,
- Fix typo in one-line summary,
- Add Reviewed-by.

Thanks for your comments!

[1] https://lore.kernel.org/r/[email protected]

Geert Uytterhoeven (8):
dt-bindings: fuse: Document R-Car E-FUSE / PFC
dt-bindings: fuse: Document R-Car E-FUSE / OTP_MEM
soc: renesas: Add R-Car fuse driver
pinctrl: renesas: Add R-Car Gen3 fuse support
arm64: dts: renesas: r8a779a0: Add E-FUSE node
arm64: dts: renesas: r8a779f0: Add E-FUSE node
arm64: dts: renesas: r8a779g0: Add OTP_MEM node
arm64: dts: renesas: r8a779h0: Add OTP_MEM node

 .../bindings/fuse/renesas,rcar-efuse.yaml     |  55 +++++
 .../bindings/fuse/renesas,rcar-otp.yaml       |  38 ++++
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi     |   8 +
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi     |   8 +
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi     |   5 +
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi     |   5 +
 drivers/pinctrl/renesas/core.c                |  18 ++
 drivers/pinctrl/renesas/pfc-r8a77951.c        |   2 +
 drivers/pinctrl/renesas/pfc-r8a7796.c         |   4 +
 drivers/pinctrl/renesas/pfc-r8a77965.c        |   2 +
 drivers/pinctrl/renesas/pfc-r8a77970.c        |   2 +
 drivers/pinctrl/renesas/pfc-r8a77980.c        |  14 +-
 drivers/pinctrl/renesas/pfc-r8a77990.c        |   2 +
 drivers/pinctrl/renesas/pfc-r8a77995.c        |   2 +
 drivers/pinctrl/renesas/sh_pfc.h              |   4 +-
 drivers/soc/renesas/Kconfig                   |   8 +
 drivers/soc/renesas/Makefile                  |   1 +
 drivers/soc/renesas/rcar-fuse.c               | 201 ++++++++++++++++++
 include/linux/platform_data/rcar_fuse.h       |  11 +
 include/linux/soc/renesas/rcar-fuse.h         |  41 ++++
 20 files changed, 429 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml
 create mode 100644 Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml
 create mode 100644 drivers/soc/renesas/rcar-fuse.c
 create mode 100644 include/linux/platform_data/rcar_fuse.h
 create mode 100644 include/linux/soc/renesas/rcar-fuse.h

2.34.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Document support for E-FUSE non-volatile memory accessible through PFC on R-Car V3U and S4-8.

---
v2:
- Add Reviewed-by.

---
 .../bindings/fuse/renesas,rcar-efuse.yaml     | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fuse/renesas,rcar-efuse.yaml

new file mode 100644
index 0000000000000000..d7e289244e72cce1
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fuse/renesas,rcar-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: R-Car E-FUSE connected to PFC
+
+maintainers:
+  - Geert Uytterhoeven <[email protected]>
+
+description:
+  The E-FUSE is a type of non-volatile memory, which is accessible through the
+  Pin Function Controller (PFC) on some R-Car Gen4 SoCs.
+
+properties:
+  compatible:
+    enum:
+      - renesas,r8a779a0-efuse # R-Car V3U
+      - renesas,r8a779f0-efuse # R-Car S4-8
+
+  reg:
+    maxItems: 1
+    description: PFC System Group Fuse Control and Monitor register block
+
+  clocks:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
+    #include <dt-bindings/power/r8a779a0-sysc.h>
+
+    fuse: fuse@e6078800 {
+            compatible = "renesas,r8a779a0-efuse";
+            reg = <0xe6078800 0x100>;
+            clocks = <&cpg CPG_MOD 916>;
+            power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+            resets = <&cpg 916>;
+    };

2.34.1

Document support for E-FUSE non-volatile memory accessible through OTP_MEM on R-Car V4H and V4M.

---
v2:
- Add Reviewed-by.

---
 .../bindings/fuse/renesas,rcar-otp.yaml       | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fuse/renesas,rcar-otp.yaml

new file mode 100644
index 0000000000000000..d74872ae9ff378f9
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: R-Car E-FUSE connected to OTP_MEM
+
+maintainers:
+  - Geert Uytterhoeven <[email protected]>
+
+description:
+  The E-FUSE is a type of non-volatile memory, which is accessible through the
+  One-Time Programmable Memory (OTP_MEM) module on some R-Car Gen4 SoCs.
+
+properties:
+  compatible:
+    enum:
+      - renesas,r8a779g0-otp # R-CarV4H
+      - renesas,r8a779h0-otp # R-CarV4M
+
+  reg:
+    items:
+      - description: OTP_MEM_0
+      - description: OTP_MEM_1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    otp: otp@e61be000 {
+            compatible = "renesas,r8a779g0-otp";
+            reg = <0xe61be000 0x1000>, <0xe61bf000 0x1000>;
+    };

2.34.1

R-Car Gen3/Gen4 SoCs contain fuses indicating hardware support or hardware parameters. Add a driver to access the state of the fuses. This supports three type of hardware fuse provides:
1. E-FUSE non-volatile memory accessible through the Pin Function Controller on R-Car V3U and S4-8,
2. E-FUSE non-volatile memory accessible through OTP_MEM on R-Car V4H and V4M,
3. Fuses tightly integrated with the Pin Function Controller on R-Car Gen3 SoCs.

Types 1 and 2 use hardware descriptions in DT.
Type 3 relies on a platform device with accompanying platform data, to be provided by the PFC driver.

Two APIs are provided to read the state of the fuses:
- An kernelspace API (rcar_fuse_read()), to be used by e.g. the Renesas UFSHCD driver,
Symbolic register indices are provided for convenience.
- A userspace API, using the NVMEM framework.

---
v2:
- Add Reviewed-by.

Questions:
- Should the NVMEM support be made optional, relaxing the dependency on NVMEM?
- Currently, the NVMEM access is restricted to the root user. Should his be relaxed?
- On R-Car S4, the full space from RCAR_FUSE_MON0 to RCAR_LTM0_MON2 is exposed. Should this be split into separate blocks?

---
 drivers/soc/renesas/Kconfig             |   8 +
 drivers/soc/renesas/Makefile            |   1 +
 drivers/soc/renesas/rcar-fuse.c         | 201 ++++++++++++++++++++++++
 include/linux/platform_data/rcar_fuse.h |  11 ++
 include/linux/soc/renesas/rcar-fuse.h   |  41 +++++
 5 files changed, 262 insertions(+)
 create mode 100644 drivers/soc/renesas/rcar-fuse.c
 create mode 100644 include/linux/platform_data/rcar_fuse.h
 create mode 100644 include/linux/soc/renesas/rcar-fuse.h

index 3125ab575b60b8d1..13aadcf1dec7b8b8 100644
@@ -376,6 +376,14 @@ config ARCH_R9A07G043
 
 endif # RISCV
 
+config FUSE_RCAR
+	tristate "R-Car Fuse support"
+	depends on (ARCH_RENESAS && ARM64) || COMPILE_TEST
+	depends on NVMEM
+	help
+	  Enable support for reading the fuses in the PFC, E-FUSE or OTP
+	  non-volatile memory block on R-Car Gen3/Gen4 SoCs.
+
 config PWC_RZV2M
 	bool "Renesas RZ/V2M PWC support" if COMPILE_TEST
 

index 725eedd9d73ceae7..8ff382a82ac94496 100644
@@ -8,5 +8,6 @@ obj-$(CONFIG_ARCH_R9A06G032)	+= r9a06g032-smp.o
 endif
 
 # Family
+obj-$(CONFIG_FUSE_RCAR)		+= rcar-fuse.o
 obj-$(CONFIG_PWC_RZV2M)		+= pwc-rzv2m.o
 obj-$(CONFIG_RST_RCAR)		+= rcar-rst.o

new file mode 100644
index 0000000000000000..07933336b5f4e668
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __LINUX_PLATFORM_DATA_RCAR_FUSE_H__
+#define __LINUX_PLATFORM_DATA_RCAR_FUSE_H__
+
+struct rcar_fuse_platform_data {
+	void __iomem *base;
+	unsigned int offset;
+	unsigned int nregs;
+};
+
+#endif /* __LINUX_PLATFORM_DATA_RCAR_FUSE_H__ */

2.34.1

On R-Car Gen3 SoCs, the fuse registers are tightly integrated into the Pin Function Controller. Add support for them by providing the rcar-fuse driver with all needed info through a platform device and platform data.

Note that the number of fuse registers on R-Car V3H and V3H2 differs, while their PFC blocks use the same compatible value, hence this is handled by checking the top-level compatible value.

---
v2:
- Add Reviewed-by.

FUSE_MON[1-3] on R-Car V3M were only briefly documented in Hardware User's Manual Rev. 0.52/0.53

---
 drivers/pinctrl/renesas/core.c         | 18 ++++++++++++++++++
 drivers/pinctrl/renesas/pfc-r8a77951.c |  2 ++
 drivers/pinctrl/renesas/pfc-r8a7796.c  |  4 ++++
 drivers/pinctrl/renesas/pfc-r8a77965.c |  2 ++
 drivers/pinctrl/renesas/pfc-r8a77970.c |  2 ++
 drivers/pinctrl/renesas/pfc-r8a77980.c | 14 +++++++++++++-
 drivers/pinctrl/renesas/pfc-r8a77990.c |  2 ++
 drivers/pinctrl/renesas/pfc-r8a77995.c |  2 ++
 drivers/pinctrl/renesas/sh_pfc.h       |  4 +++-
 9 files changed, 48 insertions(+), 2 deletions(-)

index 96d6040a8871419b..1c8447fcfb1180e3 100644
@@ -20,6 +20,7 @@
 #include <linux/math.h>
 #include <linux/of.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/rcar_fuse.h>
 #include <linux/platform_device.h>
 #include <linux/psci.h>
 #include <linux/slab.h>

@@ -27,6 +28,8 @@
 
 #include "core.h"
 
+#define FUSE_MON0	0x3e4		/* R-Car Gen3 */
+
 static int sh_pfc_map_resources(struct sh_pfc *pfc,
 				struct platform_device *pdev)
 {

@@ -1372,6 +1375,21 @@ static int sh_pfc_probe(struct platform_device *pdev)
 	}
 #endif
 
+	if (pfc->info->nr_fuse_regs) {
+		struct rcar_fuse_platform_data pdata = {
+			.base = pfc->windows[0].virt,
+			.offset = FUSE_MON0,
+			.nregs = pfc->info->nr_fuse_regs,
+		};
+		struct platform_device *fdev;
+
+		fdev = platform_device_register_data(pfc->dev, "rcar_fuse", -1,
+						     &pdata, sizeof(pdata));
+		if (IS_ERR(fdev))
+			dev_err_probe(pfc->dev, PTR_ERR(fdev),
+				      "failed to register fuses, ignoring\n");
+	}
+
 	platform_set_drvdata(pdev, pfc);
 
 	dev_info(pfc->dev, "%s support registered\n", info->name);

index a1d74f61fd8cce64..ae60bc5f70f0c223 100644
@@ -6187,5 +6187,7 @@ const struct sh_pfc_soc_info r8a77951_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 1,
 };
 #endif

index 807834f319f07d8c..b1ebd9a0b612e5b8 100644
@@ -6139,6 +6139,8 @@ const struct sh_pfc_soc_info r8a77960_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 1,
 };
 #endif
 

@@ -6166,5 +6168,7 @@ const struct sh_pfc_soc_info r8a77961_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 1,
 };
 #endif

index e7c88a5d983f4343..47f9843a336225ac 100644
@@ -6380,5 +6380,7 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 1,
 };
 #endif

index e1b3e3b38ec3b864..688fe31c5b98ac14 100644
@@ -2557,4 +2557,6 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 4,
 };

index 877134d78c7e50c6..085eb6090420d013 100644
@@ -15,6 +15,7 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of.h>
 
 #include "sh_pfc.h"
 

@@ -3048,13 +3049,22 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
 	{ /* sentinel */ }
 };
 
+static int r8a77980_pinmux_init(struct sh_pfc *pfc)
+{
+	if (of_machine_is_compatible("renesas,r8a77980a"))
+		r8a77980_pinmux_info.nr_fuse_regs = 5;
+
+	return 0;
+}
+
 static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
+	.init = r8a77980_pinmux_init,
 	.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
 	.get_bias = rcar_pinmux_get_bias,
 	.set_bias = rcar_pinmux_set_bias,
 };
 
-const struct sh_pfc_soc_info r8a77980_pinmux_info = {
+struct sh_pfc_soc_info r8a77980_pinmux_info = {
 	.name = "r8a77980_pfc",
 	.ops = &r8a77980_pfc_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */

@@ -3074,4 +3084,6 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 1,
 };

index 262390dd7d67a101..748b9198d1efd820 100644
@@ -5336,5 +5336,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 1,
 };
 #endif

index 298e7a07e4934e67..f9003b8236a8881e 100644
@@ -3193,4 +3193,6 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+
+	.nr_fuse_regs = 1,
 };

index 0061e96400598e49..ce9b591a275ffbd3 100644
@@ -290,6 +290,8 @@ struct sh_pfc_soc_info {
 	unsigned int pinmux_data_size;
 
 	u32 unlock_reg;		/* can be literal address or mask */
+
+	unsigned int nr_fuse_regs;
 };
 
 extern const struct sh_pfc_soc_info emev2_pinmux_info;

@@ -316,7 +318,7 @@ extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
-extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
+extern struct sh_pfc_soc_info r8a77980_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
 extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;

2.34.1

In case this needs to go through some other tree than mine.

Yours,
Linus Walleij

Add a device node for the System Group Fuse Control and Monitor block of the Pin Function Controller (PFC) on the R-Car V3U (R8A779A0) SoC, which provides E-FUSE services.

---
v2:
- Add Reviewed-by.

Assuming the Fuse Control and Monitor block is driven by the same module clock as GPIO Group 0.

---
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

index cfa70b441e329a0b..1abe92c98358eddb 100644
@@ -245,6 +245,14 @@ gpio9: gpio@e6069980 {
 			#interrupt-cells = <2>;
 		};
 
+		fuse: fuse@e6078800 {
+			compatible = "renesas,r8a779a0-efuse";
+			reg = <0 0xe6078800 0 0x100>;
+			clocks = <&cpg CPG_MOD 916>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 916>;
+		};
+
 		cmt0: timer@e60f0000 {
 			compatible = "renesas,r8a779a0-cmt0",
 				     "renesas,rcar-gen4-cmt0";

2.34.1

Add a device node for the System Group Fuse Control and Monitor block of the Pin Function Controller (PFC) on the R-Car S4-8 (R8A779F0) SoC, which provides E-FUSE services.

---
v2:
- s/r8a779g0/r8a779f0/ in one-line summary,
- Add Reviewed-by.

Assuming the Fuse Control and Monitor block is driven by the same module clock as GPIO Group 0.

---
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

index 72cf30341fc4d63e..48390654e172bd5d 100644
@@ -377,6 +377,14 @@ gpio3: gpio@e6051980 {
 			#interrupt-cells = <2>;
 		};
 
+		fuse: fuse@e6078800 {
+			compatible = "renesas,r8a779f0-efuse";
+			reg = <0 0xe6078800 0 0x100>;
+			clocks = <&cpg CPG_MOD 915>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 915>;
+		};
+
 		cmt0: timer@e60f0000 {
 			compatible = "renesas,r8a779f0-cmt0",
 				     "renesas,rcar-gen4-cmt0";

2.34.1

Add a device node for the OTP non-volatile memory on the R-Car V4H (R8A779G0) SoC, which provides E-FUSE services.

---
v2:
- Add Reviewed-by.

---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index 2ee306305d834315..aaeebf736f3f74f6 100644
@@ -463,6 +463,11 @@ tsc: thermal@e6198000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		otp: otp@e61be000 {
+			compatible = "renesas,r8a779g0-otp";
+			reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>;
+		};
+
 		intc_ex: interrupt-controller@e61c0000 {
 			compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
 			#interrupt-cells = <2>;

2.34.1

Add a device node for the OTP non-volatile memory on the R-Car V4M (R8A779H0) SoC, which provides E-FUSE services.

---
v2:
- Add Reviewed-by.

---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index 28ac930e7db1f234..3766652623fd8e5e 100644
@@ -411,6 +411,11 @@ tsc: thermal@e6198000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		otp: otp@e61be000 {
+			compatible = "renesas,r8a779h0-otp";
+			reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>;
+		};
+
 		intc_ex: interrupt-controller@e61c0000 {
 			compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc";
 			#interrupt-cells = <2>;

2.34.1

I plan to queue these in renesas-devel/pinctrl for v6.11.

Gr{oetje,eeting}s,

Geert

Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Hi Srinivas,

Arnd pointed out on IRC this should probably be an nvmem driver instead of an soc driver. I had mimicked this after the Tegra fuse driver, which is also an soc driver. The in-kernel user would be its main user. The nvmem interface exists just because the tegra driver did the same.

After some investigation, it looks like this should use Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml instead, and handle it like e.g. Documentation/devicetree/bindings/nvmem/sprd-efuse.txt?

Thanks for your guidance!

Link to this series:
https://lore.kernel.org/all/[email protected]/

Gr{oetje,eeting}s,

Geert

Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds