staging: rtl8723bs: Remove unused macros starting with hal_com_h2c.h

index 24cd9415fa95..a59d13090565 100644
@@ -9,86 +9,10 @@
 
 #define H2C_RSVDPAGE_LOC_LEN		5
 #define H2C_MEDIA_STATUS_RPT_LEN		3
-#define H2C_KEEP_ALIVE_CTRL_LEN	2
-#define H2C_DISCON_DECISION_LEN		3
-#define H2C_AP_OFFLOAD_LEN		3
-#define H2C_AP_WOW_GPIO_CTRL_LEN	4
-#define H2C_AP_PS_LEN			2
 #define H2C_PWRMODE_LEN			7
 #define H2C_PSTUNEPARAM_LEN			4
 #define H2C_MACID_CFG_LEN		7
-#define H2C_BTMP_OPER_LEN			4
-#define H2C_WOWLAN_LEN			4
-#define H2C_REMOTE_WAKE_CTRL_LEN	3
-#define H2C_AOAC_GLOBAL_INFO_LEN	2
-#define H2C_AOAC_RSVDPAGE_LOC_LEN	7
-#define H2C_SCAN_OFFLOAD_CTRL_LEN	4
-#define H2C_BT_FW_PATCH_LEN			6
 #define H2C_RSSI_SETTING_LEN		4
-#define H2C_AP_REQ_TXRPT_LEN		2
-#define H2C_FORCE_BT_TXPWR_LEN		3
-#define H2C_BCN_RSVDPAGE_LEN		5
-#define H2C_PROBERSP_RSVDPAGE_LEN	5
-
-/* _RSVDPAGE_LOC_CMD_0x00 */
-#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
-#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
-#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
-#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
-#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
-
-/* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */
-#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
-#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value)
-
-/* _KEEP_ALIVE_CMD_0x03 */
-#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
-
-/* _DISCONNECT_DECISION_CMD_0x04 */
-#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
-#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value)
-
-/*  _WoWLAN PARAM_CMD_0x80 */
-#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
-#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
-#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
-#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
-#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
-/* define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value) */
-#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
-
-/*  _REMOTE_WAKEUP_CMD_0x81 */
-#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
-#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
-
-/*  AOAC_GLOBAL_INFO_0x82 */
-#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
-#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
-
-/*  AOAC_RSVDPAGE_LOC_0x83 */
-#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd), 0, 8, __Value)
-#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
-#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
-#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
-#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
 
 /*  */
 /*     Structure    -------------------------------------------------- */

index 1527d8be2d7a..54fadb92334c 100644
@@ -63,43 +63,21 @@ enum {
 
 #define	LDPC_HT_ENABLE_RX			BIT0
 #define	LDPC_HT_ENABLE_TX			BIT1
-#define	LDPC_HT_TEST_TX_ENABLE		BIT2
 #define	LDPC_HT_CAP_TX				BIT3
 
 #define	STBC_HT_ENABLE_RX			BIT0
 #define	STBC_HT_ENABLE_TX			BIT1
-#define	STBC_HT_TEST_TX_ENABLE		BIT2
 #define	STBC_HT_CAP_TX				BIT3
 
 #define	BEAMFORMING_HT_BEAMFORMER_ENABLE	BIT0	/*  Declare our NIC supports beamformer */
 #define	BEAMFORMING_HT_BEAMFORMEE_ENABLE	BIT1	/*  Declare our NIC supports beamformee */
-#define	BEAMFORMING_HT_BEAMFORMER_TEST		BIT2	/*  Transmiting Beamforming no matter the target supports it or not */
-
-/*  */
-/*  The HT Control field */
-/*  */
-#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val)					SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _val)
-#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1, _val)
-#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+3, 0, 1)
 
 /*  20/40 BSS Coexist */
 #define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE((_pEleStart), 0, 1, _val)
-#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart), 0, 1)
-
 
 #define GET_HT_CAPABILITY_ELE_LDPC_CAP(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 0, 1)
 #define GET_HT_CAPABILITY_ELE_TX_STBC(_pEleStart)					LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
 
 #define GET_HT_CAPABILITY_ELE_RX_STBC(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 2)
 
-/* TXBF Capabilities */
-#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val)					SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
-#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
-#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val)		SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
-#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val)		SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
-#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
-
-#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart)			LE_BITS_TO_4BYTE((_pEleStart)+21, 10, 1)
-#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart)			LE_BITS_TO_4BYTE((_pEleStart)+21, 15, 2)
-
 #endif	/* _RTL871X_HT_H_ */

index d8d03752dc2e..9a02ae69d7a4 100644
@@ -7,91 +7,34 @@
 #ifndef __HAL_COMMON_REG_H__
 #define __HAL_COMMON_REG_H__
 
-
-#define MAC_ADDR_LEN				6
-
-#define HAL_NAV_UPPER_UNIT		128		/*  micro-second */
-
-/*  8188E PKT_BUFF_ACCESS_CTRL value */
-#define TXPKT_BUF_SELECT				0x69
-#define RXPKT_BUF_SELECT				0xA5
-#define DISABLE_TRXPKT_BUF_ACCESS		0x0
-
-/*  */
-/*  */
-/*  */
-
 /*  */
 /*  */
 /* 	0x0000h ~ 0x00FFh	System Configuration */
 /*  */
 /*  */
-#define REG_SYS_ISO_CTRL				0x0000
 #define REG_SYS_FUNC_EN				0x0002
 #define REG_APS_FSMCO					0x0004
 #define REG_SYS_CLKR					0x0008
 #define REG_9346CR						0x000A
 #define REG_SYS_EEPROM_CTRL			0x000A
-#define REG_EE_VPD						0x000C
-#define REG_AFE_MISC					0x0010
-#define REG_SPS0_CTRL					0x0011
-#define REG_SPS0_CTRL_6					0x0016
-#define REG_POWER_OFF_IN_PROCESS		0x0017
-#define REG_SPS_OCP_CFG				0x0018
 #define REG_RSV_CTRL					0x001C
 #define REG_RF_CTRL						0x001F
-#define REG_LDOA15_CTRL				0x0020
-#define REG_LDOV12D_CTRL				0x0021
-#define REG_LDOHCI12_CTRL				0x0022
-#define REG_LPLDO_CTRL					0x0023
 #define REG_AFE_XTAL_CTRL				0x0024
-#define REG_AFE_LDO_CTRL				0x0027 /*  1.5v for 8188EE test chip, 1.4v for MP chip */
-#define REG_AFE_PLL_CTRL				0x0028
 #define REG_MAC_PHY_CTRL				0x002c /* for 92d, DMDP, SMSP, DMSP contrl */
-#define REG_APE_PLL_CTRL_EXT			0x002c
 #define REG_EFUSE_CTRL					0x0030
 #define REG_EFUSE_TEST					0x0034
 #define REG_PWR_DATA					0x0038
-#define REG_CAL_TIMER					0x003C
-#define REG_ACLK_MON					0x003E
 #define REG_GPIO_MUXCFG				0x0040
-#define REG_GPIO_IO_SEL					0x0042
-#define REG_MAC_PINMUX_CFG			0x0043
-#define REG_GPIO_PIN_CTRL				0x0044
 #define REG_GPIO_INTM					0x0048
 #define REG_LEDCFG0						0x004C
-#define REG_LEDCFG1						0x004D
 #define REG_LEDCFG2						0x004E
-#define REG_LEDCFG3						0x004F
-#define REG_FSIMR						0x0050
-#define REG_FSISR						0x0054
 #define REG_HSIMR						0x0058
-#define REG_HSISR						0x005c
-#define REG_GPIO_PIN_CTRL_2			0x0060 /*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
 #define REG_GPIO_IO_SEL_2				0x0062 /*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
 #define REG_MULTI_FUNC_CTRL			0x0068 /*  RTL8723 WIFI/BT/GPS Multi-Function control source. */
-#define REG_GSSR						0x006c
-#define REG_AFE_XTAL_CTRL_EXT			0x0078 /* RTL8188E */
 #define REG_MCUFWDL					0x0080
-#define REG_MCUTSTCFG					0x0084
-#define REG_FDHM0						0x0088
 #define REG_EFUSE_ACCESS				0x00CF	/*  Efuse access protection for RTL8723 */
-#define REG_BIST_SCAN					0x00D0
-#define REG_BIST_RPT					0x00D4
-#define REG_BIST_ROM_RPT				0x00D8
-#define REG_USB_SIE_INTF				0x00E0
-#define REG_PCIE_MIO_INTF				0x00E4
-#define REG_PCIE_MIO_INTD				0x00E8
-#define REG_HPON_FSM					0x00EC
 #define REG_SYS_CFG						0x00F0
 #define REG_GPIO_OUTSTS				0x00F4	/*  For RTL8723 only. */
-#define REG_TYPE_ID						0x00FC
-
-/*  */
-/*  2010/12/29 MH Add for 92D */
-/*  */
-#define REG_MAC_PHY_CTRL_NORMAL		0x00f8
-
 
 /*  */
 /*  */

@@ -100,44 +43,15 @@
 /*  */
 #define REG_CR							0x0100
 #define REG_PBP							0x0104
-#define REG_PKT_BUFF_ACCESS_CTRL		0x0106
 #define REG_TRXDMA_CTRL				0x010C
 #define REG_TRXFF_BNDY					0x0114
-#define REG_TRXFF_STATUS				0x0118
-#define REG_RXFF_PTR					0x011C
 #define REG_HIMR						0x0120
 #define REG_HISR						0x0124
-#define REG_HIMRE						0x0128
-#define REG_HISRE						0x012C
-#define REG_CPWM						0x012F
-#define REG_FWIMR						0x0130
-#define REG_FWISR						0x0134
-#define REG_FTIMR						0x0138
-#define REG_PKTBUF_DBG_CTRL			0x0140
-#define REG_RXPKTBUF_CTRL				(REG_PKTBUF_DBG_CTRL+2)
-#define REG_PKTBUF_DBG_DATA_L			0x0144
-#define REG_PKTBUF_DBG_DATA_H		0x0148
-
-#define REG_TC0_CTRL					0x0150
-#define REG_TC1_CTRL					0x0154
-#define REG_TC2_CTRL					0x0158
-#define REG_TC3_CTRL					0x015C
-#define REG_TC4_CTRL					0x0160
-#define REG_TCUNIT_BASE				0x0164
-#define REG_MBIST_START				0x0174
-#define REG_MBIST_DONE					0x0178
-#define REG_MBIST_FAIL					0x017C
+
 #define REG_C2HEVT_MSG_NORMAL		0x01A0
 #define REG_C2HEVT_CLEAR				0x01AF
-#define REG_MCUTST_1					0x01c0
-#define REG_FMETHR						0x01C8
 #define REG_HMETFR						0x01CC
 #define REG_HMEBOX_0					0x01D0
-#define REG_HMEBOX_1					0x01D4
-#define REG_HMEBOX_2					0x01D8
-#define REG_HMEBOX_3					0x01DC
-#define REG_LLT_INIT					0x01E0
-
 
 /*  */
 /*  */

@@ -145,9 +59,7 @@
 /*  */
 /*  */
 #define REG_RQPN						0x0200
-#define REG_FIFOPAGE					0x0204
 #define REG_TDECTRL						0x0208
-#define REG_TXDMA_OFFSET_CHK			0x020C
 #define REG_TXDMA_STATUS				0x0210
 #define REG_RQPN_NPQ					0x0214
 #define REG_AUTO_LLT					0x0224

@@ -160,109 +72,25 @@
 /*  */
 #define REG_RXDMA_AGG_PG_TH			0x0280
 #define REG_RXPKT_NUM					0x0284
-#define REG_RXDMA_STATUS				0x0288
-
-/*  */
-/*  */
-/* 	0x0300h ~ 0x03FFh	PCIe */
-/*  */
-/*  */
-#define REG_PCIE_CTRL_REG				0x0300
-#define REG_INT_MIG						0x0304	/*  Interrupt Migration */
-#define REG_BCNQ_DESA					0x0308	/*  TX Beacon Descriptor Address */
-#define REG_HQ_DESA					0x0310	/*  TX High Queue Descriptor Address */
-#define REG_MGQ_DESA					0x0318	/*  TX Manage Queue Descriptor Address */
-#define REG_VOQ_DESA					0x0320	/*  TX VO Queue Descriptor Address */
-#define REG_VIQ_DESA					0x0328	/*  TX VI Queue Descriptor Address */
-#define REG_BEQ_DESA					0x0330	/*  TX BE Queue Descriptor Address */
-#define REG_BKQ_DESA					0x0338	/*  TX BK Queue Descriptor Address */
-#define REG_RX_DESA						0x0340	/*  RX Queue	Descriptor Address */
-/* sherry added for DBI Read/Write  20091126 */
-#define REG_DBI_WDATA					0x0348	/*  Backdoor REG for Access Configuration */
-#define REG_DBI_RDATA				0x034C	/* Backdoor REG for Access Configuration */
-#define REG_DBI_CTRL					0x0350	/* Backdoor REG for Access Configuration */
-#define REG_DBI_FLAG					0x0352	/* Backdoor REG for Access Configuration */
-#define REG_MDIO						0x0354	/*  MDIO for Access PCIE PHY */
-#define REG_DBG_SEL						0x0360	/*  Debug Selection Register */
-#define REG_PCIE_HRPWM					0x0361	/* PCIe RPWM */
-#define REG_PCIE_HCPWM					0x0363	/* PCIe CPWM */
-#define REG_WATCH_DOG					0x0368
-
-/*  RTL8723 series ------------------------------- */
-#define REG_PCIE_HISR_EN				0x0394	/* PCIE Local Interrupt Enable Register */
-#define REG_PCIE_HISR					0x03A0
-#define REG_PCIE_HISRE					0x03A4
-#define REG_PCIE_HIMR					0x03A8
-#define REG_PCIE_HIMRE					0x03AC
-
-#define REG_USB_HIMR					0xFE38
-#define REG_USB_HIMRE					0xFE3C
-#define REG_USB_HISR					0xFE78
-#define REG_USB_HISRE					0xFE7C
-
 
 /*  */
 /*  */
 /* 	0x0400h ~ 0x047Fh	Protocol Configuration */
 /*  */
 /*  */
-#define REG_VOQ_INFORMATION			0x0400
-#define REG_VIQ_INFORMATION			0x0404
-#define REG_BEQ_INFORMATION			0x0408
-#define REG_BKQ_INFORMATION			0x040C
-#define REG_MGQ_INFORMATION			0x0410
-#define REG_HGQ_INFORMATION			0x0414
-#define REG_BCNQ_INFORMATION			0x0418
 #define REG_TXPKT_EMPTY				0x041A
-#define REG_CPU_MGQ_INFORMATION		0x041C
 #define REG_FWHW_TXQ_CTRL				0x0420
 #define REG_HWSEQ_CTRL					0x0423
-#define REG_BCNQ_BDNY					0x0424
-#define REG_MGQ_BDNY					0x0425
-#define REG_LIFETIME_CTRL				0x0426
-#define REG_MULTI_BCNQ_OFFSET			0x0427
 #define REG_SPEC_SIFS					0x0428
 #define REG_RL							0x042A
-#define REG_DARFRC						0x0430
-#define REG_RARFRC						0x0438
 #define REG_RRSR						0x0440
-#define REG_ARFR0						0x0444
-#define REG_ARFR1						0x0448
-#define REG_ARFR2						0x044C
-#define REG_ARFR3						0x0450
-#define REG_BCNQ1_BDNY					0x0457
-
-#define REG_AGGLEN_LMT					0x0458
-#define REG_AMPDU_MIN_SPACE			0x045C
-#define REG_WMAC_LBK_BF_HD			0x045D
-#define REG_FAST_EDCA_CTRL				0x0460
-#define REG_RD_RESP_PKT_TH				0x0463
-
-#define REG_INIRTS_RATE_SEL				0x0480
-#define REG_INIDATA_RATE_SEL			0x0484
-
-#define REG_POWER_STAGE1				0x04B4
-#define REG_POWER_STAGE2				0x04B8
+
 #define REG_PKT_VO_VI_LIFE_TIME		0x04C0
 #define REG_PKT_BE_BK_LIFE_TIME		0x04C2
-#define REG_STBC_SETTING				0x04C4
-#define REG_QUEUE_CTRL					0x04C6
-#define REG_SINGLE_AMPDU_CTRL			0x04c7
-#define REG_PROT_MODE_CTRL			0x04C8
-#define REG_MAX_AGGR_NUM				0x04CA
-#define REG_RTS_MAX_AGGR_NUM			0x04CB
 #define REG_BAR_MODE_CTRL				0x04CC
-#define REG_RA_TRY_RATE_AGG_LMT		0x04CF
 #define REG_EARLY_MODE_CONTROL		0x04D0
 #define REG_MACID_SLEEP				0x04D4
 #define REG_NQOS_SEQ					0x04DC
-#define REG_QOS_SEQ					0x04DE
-#define REG_NEED_CPU_HANDLE			0x04E0
-#define REG_PKT_LOSE_RPT				0x04E1
-#define REG_PTCL_ERR_STATUS			0x04E2
-#define REG_TX_RPT_CTRL					0x04EC
-#define REG_TX_RPT_TIME					0x04F0	/*  2 byte */
-#define REG_DUMMY						0x04FC
 
 /*  */
 /*  */

@@ -274,16 +102,11 @@
 #define REG_EDCA_BE_PARAM				0x0508
 #define REG_EDCA_BK_PARAM				0x050C
 #define REG_BCNTCFG						0x0510
-#define REG_PIFS							0x0512
-#define REG_RDG_PIFS					0x0513
 #define REG_SIFS_CTX					0x0514
 #define REG_SIFS_TRX					0x0516
 #define REG_TSFTR_SYN_OFFSET			0x0518
-#define REG_AGGR_BREAK_TIME			0x051A
 #define REG_SLOT						0x051B
-#define REG_TX_PTCL_CTRL				0x0520
 #define REG_TXPAUSE						0x0522
-#define REG_DIS_TXREQ_CLR				0x0523
 #define REG_RD_CTRL						0x0524
 /*  */
 /*  Format for offset 540h-542h: */

@@ -301,90 +124,39 @@
 /*  Described by Designer Tim and Bruce, 2011-01-14. */
 /*  */
 #define REG_TBTT_PROHIBIT				0x0540
-#define REG_RD_NAV_NXT					0x0544
-#define REG_NAV_PROT_LEN				0x0546
 #define REG_BCN_CTRL					0x0550
 #define REG_BCN_CTRL_1					0x0551
-#define REG_MBID_NUM					0x0552
 #define REG_DUAL_TSF_RST				0x0553
 #define REG_BCN_INTERVAL				0x0554	/*  The same as REG_MBSSID_BCN_SPACE */
 #define REG_DRVERLYINT					0x0558
 #define REG_BCNDMATIM					0x0559
 #define REG_ATIMWND					0x055A
-#define REG_USTIME_TSF					0x055C
 #define REG_BCN_MAX_ERR				0x055D
 #define REG_RXTSF_OFFSET_CCK			0x055E
 #define REG_RXTSF_OFFSET_OFDM			0x055F
 #define REG_TSFTR						0x0560
-#define REG_TSFTR1						0x0568	/*  HW Port 1 TSF Register */
-#define REG_ATIMWND_1					0x0570
-#define REG_P2P_CTWIN					0x0572 /*  1 Byte long (in unit of TU) */
-#define REG_PSTIMER						0x0580
-#define REG_TIMER0						0x0584
-#define REG_TIMER1						0x0588
 #define REG_ACMHWCTRL					0x05C0
-#define REG_NOA_DESC_SEL				0x05CF
-#define REG_NOA_DESC_DURATION		0x05E0
-#define REG_NOA_DESC_INTERVAL			0x05E4
-#define REG_NOA_DESC_START			0x05E8
-#define REG_NOA_DESC_COUNT			0x05EC
-
-#define REG_DMC							0x05F0	/* Dual MAC Co-Existence Register */
-#define REG_SCH_TX_CMD					0x05F8
-
-#define REG_FW_RESET_TSF_CNT_1		0x05FC
-#define REG_FW_RESET_TSF_CNT_0		0x05FD
-#define REG_FW_BCN_DIS_CNT			0x05FE
 
 /*  */
 /*  */
 /* 	0x0600h ~ 0x07FFh	WMAC Configuration */
 /*  */
 /*  */
-#define REG_APSD_CTRL					0x0600
 #define REG_BWOPMODE					0x0603
 #define REG_TCR							0x0604
 #define REG_RCR							0x0608
-#define REG_RX_PKT_LIMIT				0x060C
-#define REG_RX_DLK_TIME				0x060D
 #define REG_RX_DRVINFO_SZ				0x060F
 
 #define REG_MACID						0x0610
 #define REG_BSSID						0x0618
 #define REG_MAR							0x0620
-#define REG_MBIDCAMCFG					0x0628
 
-#define REG_PNO_STATUS					0x0631
-#define REG_USTIME_EDCA				0x0638
 #define REG_MAC_SPEC_SIFS				0x063A
 /*  20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
 #define REG_RESP_SIFS_CCK				0x063C	/*  [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
 #define REG_RESP_SIFS_OFDM                    0x063E	/*  [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
 
 #define REG_ACKTO						0x0640
-#define REG_CTS2TO						0x0641
-#define REG_EIFS							0x0642
-
-
-/* RXERR_RPT */
-#define RXERR_TYPE_OFDM_PPDU			0
-#define RXERR_TYPE_OFDMfalse_ALARM	1
-#define RXERR_TYPE_OFDM_MPDU_OK			2
-#define RXERR_TYPE_OFDM_MPDU_FAIL	3
-#define RXERR_TYPE_CCK_PPDU			4
-#define RXERR_TYPE_CCKfalse_ALARM	5
-#define RXERR_TYPE_CCK_MPDU_OK		6
-#define RXERR_TYPE_CCK_MPDU_FAIL		7
-#define RXERR_TYPE_HT_PPDU				8
-#define RXERR_TYPE_HTfalse_ALARM	9
-#define RXERR_TYPE_HT_MPDU_TOTAL		10
-#define RXERR_TYPE_HT_MPDU_OK			11
-#define RXERR_TYPE_HT_MPDU_FAIL			12
-#define RXERR_TYPE_RX_FULL_DROP			15
-
-#define RXERR_COUNTER_MASK			0xFFFFF
-#define RXERR_RPT_RST					BIT(27)
-#define _RXERR_RPT_SEL(type)			((type) << 28)
 
 /*  */
 /*  Note: */

@@ -398,81 +170,19 @@
 #define REG_NAV_UPPER					0x0652	/*  unit of 128 */
 
 /* WMA, BA, CCX */
-#define REG_NAV_CTRL					0x0650
-#define REG_BACAMCMD					0x0654
-#define REG_BACAMCONTENT				0x0658
-#define REG_LBDLY						0x0660
-#define REG_FWDLY						0x0661
 #define REG_RXERR_RPT					0x0664
-#define REG_WMAC_TRXPTCL_CTL			0x0668
 
 /*  Security */
 #define REG_CAMCMD						0x0670
 #define REG_CAMWRITE					0x0674
 #define REG_CAMREAD					0x0678
-#define REG_CAMDBG						0x067C
 #define REG_SECCFG						0x0680
 
 /*  Power */
-#define REG_WOW_CTRL					0x0690
-#define REG_PS_RX_INFO					0x0692
-#define REG_UAPSD_TID					0x0693
-#define REG_WKFMCAM_CMD				0x0698
-#define REG_WKFMCAM_NUM				REG_WKFMCAM_CMD
-#define REG_WKFMCAM_RWD				0x069C
 #define REG_RXFLTMAP0					0x06A0
 #define REG_RXFLTMAP1					0x06A2
 #define REG_RXFLTMAP2					0x06A4
 #define REG_BCN_PSR_RPT				0x06A8
-#define REG_BT_COEX_TABLE				0x06C0
-
-/*  Hardware Port 2 */
-#define REG_MACID1						0x0700
-#define REG_BSSID1						0x0708
-
-
-/*  */
-/*  */
-/* 	0xFE00h ~ 0xFE55h	USB Configuration */
-/*  */
-/*  */
-#define REG_USB_INFO					0xFE17
-#define REG_USB_SPECIAL_OPTION		0xFE55
-#define REG_USB_DMA_AGG_TO			0xFE5B
-#define REG_USB_AGG_TO					0xFE5C
-#define REG_USB_AGG_TH					0xFE5D
-
-#define REG_USB_HRPWM					0xFE58
-#define REG_USB_HCPWM					0xFE57
-
-/*  for 92DU high_Queue low_Queue Normal_Queue select */
-#define REG_USB_High_NORMAL_Queue_Select_MAC0	0xFE44
-/* define REG_USB_LOW_Queue_Select_MAC0		0xFE45 */
-#define REG_USB_High_NORMAL_Queue_Select_MAC1	0xFE47
-/* define REG_USB_LOW_Queue_Select_MAC1		0xFE48 */
-
-/*  For test chip */
-#define REG_TEST_USB_TXQS				0xFE48
-#define REG_TEST_SIE_VID				0xFE60		/*  0xFE60~0xFE61 */
-#define REG_TEST_SIE_PID				0xFE62		/*  0xFE62~0xFE63 */
-#define REG_TEST_SIE_OPTIONAL			0xFE64
-#define REG_TEST_SIE_CHIRP_K			0xFE65
-#define REG_TEST_SIE_PHY				0xFE66		/*  0xFE66~0xFE6B */
-#define REG_TEST_SIE_MAC_ADDR			0xFE70		/*  0xFE70~0xFE75 */
-#define REG_TEST_SIE_STRING			0xFE80		/*  0xFE80~0xFEB9 */
-
-
-/*  For normal chip */
-#define REG_NORMAL_SIE_VID				0xFE60		/*  0xFE60~0xFE61 */
-#define REG_NORMAL_SIE_PID				0xFE62		/*  0xFE62~0xFE63 */
-#define REG_NORMAL_SIE_OPTIONAL		0xFE64
-#define REG_NORMAL_SIE_EP				0xFE65		/*  0xFE65~0xFE67 */
-#define REG_NORMAL_SIE_PHY			0xFE68		/*  0xFE68~0xFE6B */
-#define REG_NORMAL_SIE_OPTIONAL2		0xFE6C
-#define REG_NORMAL_SIE_GPS_EP			0xFE6D		/*  0xFE6D, for RTL8723 only. */
-#define REG_NORMAL_SIE_MAC_ADDR		0xFE70		/*  0xFE70~0xFE75 */
-#define REG_NORMAL_SIE_STRING			0xFE80		/*  0xFE80~0xFEDF */
-
 
 /*  */
 /*  */

@@ -486,37 +196,14 @@
 #define EFUSE_CTRL				REG_EFUSE_CTRL		/*  E-Fuse Control. */
 #define EFUSE_TEST				REG_EFUSE_TEST		/*  E-Fuse Test. */
 #define MSR						(REG_CR + 2)		/*  Media Status register */
-/* define ISR						REG_HISR */
-
-#define TSFR						REG_TSFTR			/*  Timing Sync Function Timer Register. */
-#define TSFR1					REG_TSFTR1			/*  HW Port 1 TSF Register */
 
 #define PBP						REG_PBP
 
-/*  Redifine MACID register, to compatible prior ICs. */
-#define IDR0						REG_MACID			/*  MAC ID Register, Offset 0x0050-0x0053 */
-#define IDR4						(REG_MACID + 4)		/*  MAC ID Register, Offset 0x0054-0x0055 */
-
-
 /*  */
 /*  9. Security Control Registers	(Offset:) */
 /*  */
 #define RWCAM					REG_CAMCMD		/* IN 8190 Data Sheet is called CAMcmd */
 #define WCAMI					REG_CAMWRITE	/*  Software write CAM input content */
-#define RCAMO					REG_CAMREAD		/*  Software read/write CAM config */
-#define CAMDBG					REG_CAMDBG
-#define SECR						REG_SECCFG		/* Security Configuration Register */
-
-/*  Unused register */
-#define UnusedRegister			0x1BF
-#define DCAM					UnusedRegister
-#define PSR						UnusedRegister
-#define BBAddr					UnusedRegister
-#define PhyDataR					UnusedRegister
-
-/*  Min Spacing related settings. */
-#define MAX_MSS_DENSITY_2T			0x13
-#define MAX_MSS_DENSITY_1T			0x0A
 
 /*  */
 /*        8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */

@@ -527,20 +214,6 @@
 #define HSISR_PDNINT					BIT7
 #define HSISR_GPIO9_INT					BIT25
 
-/*  */
-/*        USB INTR CONTENT */
-/*  */
-#define USB_C2H_CMDID_OFFSET					0
-#define USB_C2H_SEQ_OFFSET					1
-#define USB_C2H_EVENT_OFFSET					2
-#define USB_INTR_CPWM_OFFSET					16
-#define USB_INTR_CONTENT_C2H_OFFSET			0
-#define USB_INTR_CONTENT_CPWM1_OFFSET		16
-#define USB_INTR_CONTENT_CPWM2_OFFSET		20
-#define USB_INTR_CONTENT_HISR_OFFSET			48
-#define USB_INTR_CONTENT_HISRE_OFFSET		52
-#define USB_INTR_CONTENT_LENGTH				56
-
 /*  */
 /*        Response Rate Set Register	(offset 0x440, 24bits) */
 /*  */

@@ -549,59 +222,14 @@
 #define RRSR_5_5M				BIT2
 #define RRSR_11M				BIT3
 #define RRSR_6M					BIT4
-#define RRSR_9M					BIT5
 #define RRSR_12M				BIT6
-#define RRSR_18M				BIT7
 #define RRSR_24M				BIT8
-#define RRSR_36M				BIT9
-#define RRSR_48M				BIT10
-#define RRSR_54M				BIT11
-#define RRSR_MCS0				BIT12
-#define RRSR_MCS1				BIT13
-#define RRSR_MCS2				BIT14
-#define RRSR_MCS3				BIT15
-#define RRSR_MCS4				BIT16
-#define RRSR_MCS5				BIT17
-#define RRSR_MCS6				BIT18
-#define RRSR_MCS7				BIT19
 
 #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M)
-#define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M)
-
-/*  WOL bit information */
-#define HAL92C_WOL_PTK_UPDATE_EVENT		BIT0
-#define HAL92C_WOL_GTK_UPDATE_EVENT		BIT1
-#define HAL92C_WOL_DISASSOC_EVENT		BIT2
-#define HAL92C_WOL_DEAUTH_EVENT			BIT3
-#define HAL92C_WOL_FW_DISCONNECT_EVENT	BIT4
 
 /*  */
 /*        Rate Definition */
 /*  */
-/* CCK */
-#define	RATR_1M					0x00000001
-#define	RATR_2M					0x00000002
-#define	RATR_55M					0x00000004
-#define	RATR_11M					0x00000008
-/* OFDM */
-#define	RATR_6M					0x00000010
-#define	RATR_9M					0x00000020
-#define	RATR_12M					0x00000040
-#define	RATR_18M					0x00000080
-#define	RATR_24M					0x00000100
-#define	RATR_36M					0x00000200
-#define	RATR_48M					0x00000400
-#define	RATR_54M					0x00000800
-/* MCS 1 Spatial Stream */
-#define	RATR_MCS0					0x00001000
-#define	RATR_MCS1					0x00002000
-#define	RATR_MCS2					0x00004000
-#define	RATR_MCS3					0x00008000
-#define	RATR_MCS4					0x00010000
-#define	RATR_MCS5					0x00020000
-#define	RATR_MCS6					0x00040000
-#define	RATR_MCS7					0x00080000
-
 /* CCK */
 #define RATE_1M					BIT(0)
 #define RATE_2M					BIT(1)

@@ -616,22 +244,12 @@
 #define RATE_36M				BIT(9)
 #define RATE_48M				BIT(10)
 #define RATE_54M				BIT(11)
-/* MCS 1 Spatial Stream */
-#define RATE_MCS0				BIT(12)
-#define RATE_MCS1				BIT(13)
-#define RATE_MCS2				BIT(14)
-#define RATE_MCS3				BIT(15)
-#define RATE_MCS4				BIT(16)
-#define RATE_MCS5				BIT(17)
-#define RATE_MCS6				BIT(18)
-#define RATE_MCS7				BIT(19)
 
 /*  ALL CCK Rate */
 #define RATE_BITMAP_ALL			0xFFFFF
 
 /*  Only use CCK 1M rate for ACK */
 #define RATE_RRSR_CCK_ONLY_1M		0xFFFF1
-#define RATE_RRSR_WITHOUT_CCK		0xFFFF0
 
 /*  */
 /*        BW_OPMODE bits				(Offset 0x603, 8bit) */

@@ -642,88 +260,19 @@
 /*        CAM Config Setting (offset 0x680, 1 byte) */
 /*  */
 #define CAM_VALID				BIT15
-#define CAM_NOTVALID			0x0000
-#define CAM_USEDK				BIT5
 
 #define CAM_CONTENT_COUNT	8
 
-#define CAM_NONE				0x0
-#define CAM_WEP40				0x01
-#define CAM_TKIP				0x02
 #define CAM_AES					0x04
-#define CAM_WEP104				0x05
-#define CAM_SMS4				0x6
 
 #define TOTAL_CAM_ENTRY		32
-#define HALF_CAM_ENTRY			16
-
-#define CAM_CONFIG_USEDK		true
-#define CAM_CONFIG_NO_USEDK	false
 
 #define CAM_WRITE				BIT16
-#define CAM_READ				0x00000000
 #define CAM_POLLINIG			BIT31
 
-/*  */
-/*  10. Power Save Control Registers */
-/*  */
-#define WOW_PMEN				BIT0 /*  Power management Enable. */
-#define WOW_WOMEN				BIT1 /*  WoW function on or off. */
-#define WOW_MAGIC				BIT2 /*  Magic packet */
-#define WOW_UWF				BIT3 /*  Unicast Wakeup frame. */
-
 /*  */
 /*  12. Host Interrupt Status Registers */
 /*  */
-/*  */
-/*       8190 IMR/ISR bits */
-/*  */
-#define IMR8190_DISABLED		0x0
-#define IMR_DISABLED			0x0
-/*  IMR DW0 Bit 0-31 */
-#define IMR_BCNDMAINT6			BIT31		/*  Beacon DMA Interrupt 6 */
-#define IMR_BCNDMAINT5			BIT30		/*  Beacon DMA Interrupt 5 */
-#define IMR_BCNDMAINT4			BIT29		/*  Beacon DMA Interrupt 4 */
-#define IMR_BCNDMAINT3			BIT28		/*  Beacon DMA Interrupt 3 */
-#define IMR_BCNDMAINT2			BIT27		/*  Beacon DMA Interrupt 2 */
-#define IMR_BCNDMAINT1			BIT26		/*  Beacon DMA Interrupt 1 */
-#define IMR_BCNDOK8				BIT25		/*  Beacon Queue DMA OK Interrupt 8 */
-#define IMR_BCNDOK7				BIT24		/*  Beacon Queue DMA OK Interrupt 7 */
-#define IMR_BCNDOK6				BIT23		/*  Beacon Queue DMA OK Interrupt 6 */
-#define IMR_BCNDOK5				BIT22		/*  Beacon Queue DMA OK Interrupt 5 */
-#define IMR_BCNDOK4				BIT21		/*  Beacon Queue DMA OK Interrupt 4 */
-#define IMR_BCNDOK3				BIT20		/*  Beacon Queue DMA OK Interrupt 3 */
-#define IMR_BCNDOK2				BIT19		/*  Beacon Queue DMA OK Interrupt 2 */
-#define IMR_BCNDOK1				BIT18		/*  Beacon Queue DMA OK Interrupt 1 */
-#define IMR_TIMEOUT2			BIT17		/*  Timeout interrupt 2 */
-#define IMR_TIMEOUT1			BIT16		/*  Timeout interrupt 1 */
-#define IMR_TXFOVW				BIT15		/*  Transmit FIFO Overflow */
-#define IMR_PSTIMEOUT			BIT14		/*  Power save time out interrupt */
-#define IMR_BcnInt				BIT13		/*  Beacon DMA Interrupt 0 */
-#define IMR_RXFOVW				BIT12		/*  Receive FIFO Overflow */
-#define IMR_RDU					BIT11		/*  Receive Descriptor Unavailable */
-#define IMR_ATIMEND				BIT10		/*  For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */
-#define IMR_BDOK				BIT9		/*  Beacon Queue DMA OK Interrupt */
-#define IMR_HIGHDOK				BIT8		/*  High Queue DMA OK Interrupt */
-#define IMR_TBDOK				BIT7		/*  Transmit Beacon OK interrupt */
-#define IMR_MGNTDOK			BIT6		/*  Management Queue DMA OK Interrupt */
-#define IMR_TBDER				BIT5		/*  For 92C, Transmit Beacon Error Interrupt */
-#define IMR_BKDOK				BIT4		/*  AC_BK DMA OK Interrupt */
-#define IMR_BEDOK				BIT3		/*  AC_BE DMA OK Interrupt */
-#define IMR_VIDOK				BIT2		/*  AC_VI DMA OK Interrupt */
-#define IMR_VODOK				BIT1		/*  AC_VO DMA Interrupt */
-#define IMR_ROK					BIT0		/*  Receive DMA OK Interrupt */
-
-/*  13. Host Interrupt Status Extension Register	 (Offset: 0x012C-012Eh) */
-#define IMR_TSF_BIT32_TOGGLE	BIT15
-#define IMR_BcnInt_E				BIT12
-#define IMR_TXERR				BIT11
-#define IMR_RXERR				BIT10
-#define IMR_C2HCMD				BIT9
-#define IMR_CPWM				BIT8
-/* RSVD [2-7] */
-#define IMR_OCPINT				BIT1
-#define IMR_WLANOFF			BIT0
 
 /*  */
 /*        8192C (RCR) Receive Configuration Register	(Offset 0x608, 32 bits) */

@@ -733,34 +282,15 @@
 #define RCR_APP_ICV				BIT29	/*  MACRX will retain the ICV at the bottom of the packet. */
 #define RCR_APP_PHYST_RXFF		BIT28	/*  PHY Status is appended before RX packet in RXFF */
 #define RCR_APP_BA_SSN			BIT27	/*  SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */
-#define RCR_NONQOS_VHT			BIT26	/*  Reserved */
-#define RCR_RSVD_BIT25			BIT25	/*  Reserved */
-#define RCR_ENMBID				BIT24	/*  Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */
-#define RCR_LSIGEN				BIT23	/*  Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */
-#define RCR_MFBEN				BIT22	/*  Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */
-#define RCR_RSVD_BIT21			BIT21	/*  Reserved */
-#define RCR_RSVD_BIT20			BIT20	/*  Reserved */
-#define RCR_RSVD_BIT19			BIT19	/*  Reserved */
-#define RCR_TIM_PARSER_EN		BIT18	/*  RX Beacon TIM Parser. */
-#define RCR_BM_DATA_EN			BIT17	/*  Broadcast data packet interrupt enable. */
-#define RCR_UC_DATA_EN			BIT16	/*  Unicast data packet interrupt enable. */
-#define RCR_RSVD_BIT15			BIT15	/*  Reserved */
 #define RCR_HTC_LOC_CTRL		BIT14	/*  MFC<--HTC = 1 MFC-->HTC = 0 */
 #define RCR_AMF					BIT13	/*  Accept management type frame */
-#define RCR_ACF					BIT12	/*  Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
 #define RCR_ADF					BIT11	/*  Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */
-#define RCR_RSVD_BIT10			BIT10	/*  Reserved */
-#define RCR_AICV					BIT9		/*  Accept ICV error packet */
 #define RCR_ACRC32				BIT8		/*  Accept CRC32 error packet */
 #define RCR_CBSSID_BCN			BIT7		/*  Accept BSSID match packet (Rx beacon, probe rsp) */
 #define RCR_CBSSID_DATA		BIT6		/*  Accept BSSID match packet (Data) */
-#define RCR_CBSSID				RCR_CBSSID_DATA	/*  Accept BSSID match packet */
-#define RCR_APWRMGT			BIT5		/*  Accept power management packet */
-#define RCR_ADD3				BIT4		/*  Accept address 3 match packet */
 #define RCR_AB					BIT3		/*  Accept broadcast packet */
 #define RCR_AM					BIT2		/*  Accept multicast packet */
 #define RCR_APM					BIT1		/*  Accept physical match packet */
-#define RCR_AAP					BIT0		/*  Accept all unicast packet */
 
 
 /*  */

@@ -769,76 +299,25 @@
 /*  */
 /*  */
 
-/* 2 SYS_ISO_CTRL */
-#define ISO_MD2PP				BIT(0)
-#define ISO_UA2USB				BIT(1)
-#define ISO_UD2CORE				BIT(2)
-#define ISO_PA2PCIE				BIT(3)
-#define ISO_PD2CORE				BIT(4)
-#define ISO_IP2MAC				BIT(5)
-#define ISO_DIOP					BIT(6)
-#define ISO_DIOE					BIT(7)
-#define ISO_EB2CORE				BIT(8)
-#define ISO_DIOR					BIT(9)
-#define PWC_EV12V				BIT(15)
-
-
 /* 2 SYS_FUNC_EN */
 #define FEN_BBRSTB				BIT(0)
 #define FEN_BB_GLB_RSTn		BIT(1)
-#define FEN_USBA				BIT(2)
-#define FEN_UPLL				BIT(3)
-#define FEN_USBD				BIT(4)
 #define FEN_DIO_PCIE			BIT(5)
 #define FEN_PCIEA				BIT(6)
 #define FEN_PPLL					BIT(7)
-#define FEN_PCIED				BIT(8)
-#define FEN_DIOE				BIT(9)
 #define FEN_CPUEN				BIT(10)
-#define FEN_DCORE				BIT(11)
 #define FEN_ELDR				BIT(12)
-#define FEN_EN_25_1				BIT(13)
-#define FEN_HWPDN				BIT(14)
-#define FEN_MREGEN				BIT(15)
 
 /* 2 APS_FSMCO */
-#define PFM_LDALL				BIT(0)
-#define PFM_ALDN				BIT(1)
-#define PFM_LDKP				BIT(2)
-#define PFM_WOWL				BIT(3)
 #define EnPDN					BIT(4)
-#define PDN_PL					BIT(5)
-#define APFM_ONMAC				BIT(8)
-#define APFM_OFF				BIT(9)
-#define APFM_RSM				BIT(10)
-#define AFSM_HSUS				BIT(11)
-#define AFSM_PCIE				BIT(12)
-#define APDM_MAC				BIT(13)
-#define APDM_HOST				BIT(14)
-#define APDM_HPDN				BIT(15)
-#define RDY_MACON				BIT(16)
-#define SUS_HOST				BIT(17)
-#define ROP_ALD					BIT(20)
-#define ROP_PWR					BIT(21)
-#define ROP_SPS					BIT(22)
-#define SOP_MRST				BIT(25)
-#define SOP_FUSE				BIT(26)
-#define SOP_ABG					BIT(27)
-#define SOP_AMB					BIT(28)
-#define SOP_RCK					BIT(29)
-#define SOP_A8M					BIT(30)
-#define XOP_BTCK				BIT(31)
 
 /* 2 SYS_CLKR */
-#define ANAD16V_EN				BIT(0)
 #define ANA8M					BIT(1)
-#define MACSLP					BIT(4)
 #define LOADER_CLK_EN			BIT(5)
 
 
 /* 2 9346CR /REG_SYS_EEPROM_CTRL */
 #define BOOT_FROM_EEPROM		BIT(4)
-#define EEPROMSEL				BIT(4)
 #define EEPROM_EN				BIT(5)
 
 

@@ -847,20 +326,7 @@
 #define RF_RSTB					BIT(1)
 #define RF_SDMRSTB				BIT(2)
 
-
-/* 2 LDOV12D_CTRL */
-#define LDV12_EN				BIT(0)
-#define LDV12_SDBY				BIT(1)
-#define LPLDO_HSM				BIT(2)
-#define LPLDO_LSM_DIS			BIT(3)
-#define _LDV12_VADJ(x)			(((x) & 0xF) << 4)
-
-
-
 /* 2 EFUSE_TEST (For RTL8723 partially) */
-#define EF_TRPT					BIT(7)
-#define EF_CELL_SEL				(BIT(8)|BIT(9)) /*  00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
-#define LDOE25_EN				BIT(31)
 #define EFUSE_SEL(x)				(((x) & 0x3) << 8)
 #define EFUSE_SEL_MASK			0x300
 #define EFUSE_WIFI_SEL_0		0x0

@@ -871,41 +337,13 @@
 
 /* 2 8051FWDL */
 /* 2 MCUFWDL */
-#define MCUFWDL_EN				BIT(0)
 #define MCUFWDL_RDY			BIT(1)
 #define FWDL_ChkSum_rpt		BIT(2)
-#define MACINI_RDY				BIT(3)
-#define BBINI_RDY				BIT(4)
-#define RFINI_RDY				BIT(5)
 #define WINTINI_RDY				BIT(6)
 #define RAM_DL_SEL				BIT(7)
-#define ROM_DLEN				BIT(19)
-#define CPRST					BIT(23)
-
 
 /* 2 REG_SYS_CFG */
-#define XCLK_VLD				BIT(0)
-#define ACLK_VLD				BIT(1)
-#define UCLK_VLD				BIT(2)
-#define PCLK_VLD				BIT(3)
-#define PCIRSTB					BIT(4)
-#define V15_VLD					BIT(5)
-#define SW_OFFLOAD_EN			BIT(7)
-#define SIC_IDLE					BIT(8)
-#define BD_MAC2					BIT(9)
-#define BD_MAC1					BIT(10)
-#define IC_MACPHY_MODE		BIT(11)
-#define CHIP_VER				(BIT(12)|BIT(13)|BIT(14)|BIT(15))
-#define BT_FUNC					BIT(16)
 #define VENDOR_ID				BIT(19)
-#define EXT_VENDOR_ID			(BIT(18)|BIT(19)) /* Currently only for RTL8723B */
-#define PAD_HWPD_IDN			BIT(22)
-#define TRP_VAUX_EN				BIT(23)	/*  RTL ID */
-#define TRP_BT_EN				BIT(24)
-#define BD_PKG_SEL				BIT(25)
-#define BD_HCI_SEL				BIT(26)
-#define TYPE_ID					BIT(27)
-#define RF_TYPE_ID				BIT(27)
 
 #define RTL_ID					BIT(23) /*  TestChip ID, 1:Test(RLE); 0:MP(RL) */
 #define SPS_SEL					BIT(24) /*  1:LDO regulator mode; 0:Switching regulator mode */

@@ -913,31 +351,10 @@
 
 #define CHIP_VER_RTL_MASK		0xF000	/* Bit 12 ~ 15 */
 #define CHIP_VER_RTL_SHIFT		12
-#define EXT_VENDOR_ID_SHIFT	18
 
 /* 2 REG_GPIO_OUTSTS (For RTL8723 only) */
-#define EFS_HCI_SEL				(BIT(0)|BIT(1))
-#define PAD_HCI_SEL				(BIT(2)|BIT(3))
-#define HCI_SEL					(BIT(4)|BIT(5))
-#define PKG_SEL_HCI				BIT(6)
-#define FEN_GPS					BIT(7)
-#define FEN_BT					BIT(8)
-#define FEN_WL					BIT(9)
-#define FEN_PCI					BIT(10)
-#define FEN_USB					BIT(11)
-#define BTRF_HWPDN_N			BIT(12)
-#define WLRF_HWPDN_N			BIT(13)
-#define PDN_BT_N				BIT(14)
-#define PDN_GPS_N				BIT(15)
-#define BT_CTL_HWPDN			BIT(16)
-#define GPS_CTL_HWPDN			BIT(17)
-#define PPHY_SUSB				BIT(20)
-#define UPHY_SUSB				BIT(21)
-#define PCI_SUSEN				BIT(22)
-#define USB_SUSEN				BIT(23)
 #define RF_RL_ID					(BIT(31)|BIT(30)|BIT(29)|BIT(28))
 
-
 /*  */
 /*  */
 /* 	0x0100h ~ 0x01FFh	MACTOP General Configuration */

@@ -961,46 +378,19 @@
 /*  Network type */
 #define _NETTYPE(x)				(((x) & 0x3) << 16)
 #define MASK_NETTYPE			0x30000
-#define NT_NO_LINK				0x0
 #define NT_LINK_AD_HOC			0x1
 #define NT_LINK_AP				0x2
-#define NT_AS_AP				0x3
 
 /* 2 PBP - Page Size Register */
-#define GET_RX_PAGE_SIZE(value)			((value) & 0xF)
-#define GET_TX_PAGE_SIZE(value)			(((value) & 0xF0) >> 4)
-#define _PSRX_MASK				0xF
-#define _PSTX_MASK				0xF0
 #define _PSRX(x)				(x)
 #define _PSTX(x)				((x) << 4)
 
-#define PBP_64					0x0
 #define PBP_128					0x1
-#define PBP_256					0x2
-#define PBP_512					0x3
-#define PBP_1024				0x4
-
 
 /* 2 TX/RXDMA */
-#define RXDMA_ARBBW_EN		BIT(0)
-#define RXSHFT_EN				BIT(1)
 #define RXDMA_AGG_EN			BIT(2)
-#define QS_VO_QUEUE			BIT(8)
-#define QS_VI_QUEUE				BIT(9)
-#define QS_BE_QUEUE			BIT(10)
-#define QS_BK_QUEUE			BIT(11)
-#define QS_MANAGER_QUEUE		BIT(12)
-#define QS_HIGH_QUEUE			BIT(13)
-
-#define HQSEL_VOQ				BIT(0)
-#define HQSEL_VIQ				BIT(1)
-#define HQSEL_BEQ				BIT(2)
-#define HQSEL_BKQ				BIT(3)
-#define HQSEL_MGTQ				BIT(4)
-#define HQSEL_HIQ				BIT(5)
 
 /*  For normal driver, 0x10C */
-#define _TXDMA_CMQ_MAP(x)			(((x)&0x3) << 16)
 #define _TXDMA_HIQ_MAP(x)			(((x)&0x3) << 14)
 #define _TXDMA_MGQ_MAP(x)			(((x)&0x3) << 12)
 #define _TXDMA_BKQ_MAP(x)			(((x)&0x3) << 10)

@@ -1008,26 +398,10 @@
 #define _TXDMA_VIQ_MAP(x)			(((x)&0x3) << 6)
 #define _TXDMA_VOQ_MAP(x)			(((x)&0x3) << 4)
 
-#define QUEUE_EXTRA				0
 #define QUEUE_LOW				1
 #define QUEUE_NORMAL			2
 #define QUEUE_HIGH				3
 
-
-/* 2 TRXFF_BNDY */
-
-
-/* 2 LLT_INIT */
-#define _LLT_NO_ACTIVE				0x0
-#define _LLT_WRITE_ACCESS			0x1
-#define _LLT_READ_ACCESS			0x2
-
-#define _LLT_INIT_DATA(x)			((x) & 0xFF)
-#define _LLT_INIT_ADDR(x)			(((x) & 0xFF) << 8)
-#define _LLT_OP(x)					(((x) & 0x3) << 30)
-#define _LLT_OP_VALUE(x)			(((x) >> 30) & 0x3)
-
-
 /*  */
 /*  */
 /* 	0x0200h ~ 0x027Fh	TXDMA Configuration */

@@ -1038,35 +412,12 @@
 #define _LPQ(x)					(((x) & 0xFF) << 8)
 #define _PUBQ(x)					(((x) & 0xFF) << 16)
 #define _NPQ(x)					((x) & 0xFF)			/*  NOTE: in RQPN_NPQ register */
-#define _EPQ(x)					(((x) & 0xFF) << 16)	/*  NOTE: in RQPN_EPQ register */
-
 
-#define HPQ_PUBLIC_DIS			BIT(24)
-#define LPQ_PUBLIC_DIS			BIT(25)
 #define LD_RQPN					BIT(31)
 
-
-/* 2 TDECTL */
-#define BLK_DESC_NUM_SHIFT			4
-#define BLK_DESC_NUM_MASK			0xF
-
-
-/* 2 TXDMA_OFFSET_CHK */
-#define DROP_DATA_EN				BIT(9)
-
 /* 2 AUTO_LLT */
-#define BIT_SHIFT_TXPKTNUM 24
-#define BIT_MASK_TXPKTNUM 0xff
-#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
-
-#define BIT_TDE_DBG_SEL BIT(23)
 #define BIT_AUTO_INIT_LLT BIT(16)
 
-#define BIT_SHIFT_Tx_OQT_free_space 8
-#define BIT_MASK_Tx_OQT_free_space 0xff
-#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
-
-
 /*  */
 /*  */
 /* 	0x0280h ~ 0x028Bh	RX DMA Configuration */

@@ -1112,13 +463,6 @@
 /*  */
 /*  */
 
-/* 2 EDCA setting */
-#define AC_PARAM_TXOP_LIMIT_OFFSET		16
-#define AC_PARAM_ECW_MAX_OFFSET			12
-#define AC_PARAM_ECW_MIN_OFFSET			8
-#define AC_PARAM_AIFS_OFFSET				0
-
-
 #define _LRL(x)					((x) & 0x3F)
 #define _SRL(x)					(((x) & 0x3F) << 8)
 

@@ -1126,33 +470,16 @@
 /* 2 BCN_CTRL */
 #define EN_TXBCN_RPT			BIT(2)
 #define EN_BCN_FUNCTION		BIT(3)
-#define STOP_BCNQ				BIT(6)
-#define DIS_RX_BSSID_FIT		BIT(6)
 
 #define DIS_ATIM					BIT(0)
 #define DIS_BCNQ_SUB			BIT(1)
 #define DIS_TSF_UDT				BIT(4)
 
-/*  The same function but different bit field. */
-#define DIS_TSF_UDT0_NORMAL_CHIP	BIT(4)
-#define DIS_TSF_UDT0_TEST_CHIP	BIT(5)
-
-
 /* 2 ACMHWCTRL */
 #define AcmHw_HwEn				BIT(0)
 #define AcmHw_BeqEn			BIT(1)
 #define AcmHw_ViqEn				BIT(2)
 #define AcmHw_VoqEn			BIT(3)
-#define AcmHw_BeqStatus		BIT(4)
-#define AcmHw_ViqStatus			BIT(5)
-#define AcmHw_VoqStatus		BIT(6)
-
-/* 2 REG_DUAL_TSF_RST (0x553) */
-#define DUAL_TSF_RST_P2P		BIT(4)
-
-/* 2  REG_NOA_DESC_SEL (0x5CF) */
-#define NOA_DESC_SEL_0			0
-#define NOA_DESC_SEL_1			BIT(4)
 
 /*  */
 /*  */

@@ -1160,56 +487,17 @@
 /*  */
 /*  */
 
-/* 2 APSD_CTRL */
-#define APSDOFF					BIT(6)
-
 /* 2 TCR */
 #define TSFRST					BIT(0)
-#define DIS_GCLK					BIT(1)
-#define PAD_SEL					BIT(2)
-#define PWR_ST					BIT(6)
-#define PWRBIT_OW_EN			BIT(7)
-#define ACRC						BIT(8)
-#define CFENDFORM				BIT(9)
-#define ICV						BIT(10)
-
 
 /* 2 RCR */
-#define AAP						BIT(0)
-#define APM						BIT(1)
-#define AM						BIT(2)
 #define AB						BIT(3)
-#define ADD3						BIT(4)
-#define APWRMGT				BIT(5)
-#define CBSSID					BIT(6)
-#define CBSSID_DATA				BIT(6)
-#define CBSSID_BCN				BIT(7)
-#define ACRC32					BIT(8)
-#define AICV						BIT(9)
-#define ADF						BIT(11)
-#define ACF						BIT(12)
-#define AMF						BIT(13)
-#define HTC_LOC_CTRL			BIT(14)
-#define UC_DATA_EN				BIT(16)
-#define BM_DATA_EN				BIT(17)
-#define MFBEN					BIT(22)
-#define LSIGEN					BIT(23)
-#define EnMBID					BIT(24)
-#define FORCEACK				BIT(26)
-#define APP_BASSN				BIT(27)
-#define APP_PHYSTS				BIT(28)
-#define APP_ICV					BIT(29)
-#define APP_MIC					BIT(30)
-#define APP_FCS					BIT(31)
-
 
 /* 2 SECCFG */
 #define SCR_TxUseDK				BIT(0)			/* Force Tx Use Default Key */
 #define SCR_RxUseDK				BIT(1)			/* Force Rx Use Default Key */
 #define SCR_TxEncEnable			BIT(2)			/* Enable Tx Encryption */
 #define SCR_RxDecEnable			BIT(3)			/* Enable Rx Decryption */
-#define SCR_SKByA2				BIT(4)			/* Search kEY BY A2 */
-#define SCR_NoSKMC				BIT(5)			/* No Key Search Multicast */
 #define SCR_TXBCUSEDK			BIT(6)			/*  Force Tx Broadcast packets Use Default Key */
 #define SCR_RXBCUSEDK			BIT(7)			/*  Force Rx Broadcast packets Use Default Key */
 #define SCR_CHK_KEYID			BIT(8)

@@ -1222,13 +510,6 @@
 
 /*  I/O bus domain address mapping */
 #define SDIO_LOCAL_BASE		0x10250000
-#define WLAN_IOREG_BASE		0x10260000
-#define FIRMWARE_FIFO_BASE	0x10270000
-#define TX_HIQ_BASE				0x10310000
-#define TX_MIQ_BASE				0x10320000
-#define TX_LOQ_BASE				0x10330000
-#define TX_EPQ_BASE				0x10350000
-#define RX_RX0FF_BASE			0x10340000
 
 /* SDIO host local register space mapping. */
 #define SDIO_LOCAL_MSK				0x0FFF

@@ -1236,12 +517,10 @@
 #define WLAN_FIFO_MSK				0x1FFF	/*  Aggregation Length[12:0] */
 #define WLAN_RX0FF_MSK				0x0003
 
-#define SDIO_WITHOUT_REF_DEVICE_ID	0	/*  Without reference to the SDIO Device ID */
 #define SDIO_LOCAL_DEVICE_ID			0	/*  0b[16], 000b[15:13] */
 #define WLAN_TX_HIQ_DEVICE_ID			4	/*  0b[16], 100b[15:13] */
 #define WLAN_TX_MIQ_DEVICE_ID		5	/*  0b[16], 101b[15:13] */
 #define WLAN_TX_LOQ_DEVICE_ID		6	/*  0b[16], 110b[15:13] */
-#define WLAN_TX_EXQ_DEVICE_ID		3	/*  0b[16], 011b[15:13] */
 #define WLAN_RX0FF_DEVICE_ID			7	/*  0b[16], 111b[15:13] */
 #define WLAN_IOREG_DEVICE_ID			8	/*  1b[16] */
 

@@ -1252,49 +531,21 @@
 #define PUBLIC_QUEUE_IDX			3
 
 #define SDIO_MAX_TX_QUEUE			3		/*  HIQ, MIQ and LOQ */
-#define SDIO_MAX_RX_QUEUE			1
 
 #define SDIO_REG_TX_CTRL			0x0000 /*  SDIO Tx Control */
 #define SDIO_REG_HIMR				0x0014 /*  SDIO Host Interrupt Mask */
 #define SDIO_REG_HISR				0x0018 /*  SDIO Host Interrupt Service Routine */
-#define SDIO_REG_HCPWM			0x0019 /*  HCI Current Power Mode */
 #define SDIO_REG_RX0_REQ_LEN		0x001C /*  RXDMA Request Length */
 #define SDIO_REG_OQT_FREE_PG		0x001E /*  OQT Free Page */
 #define SDIO_REG_FREE_TXPG			0x0020 /*  Free Tx Buffer Page */
-#define SDIO_REG_HCPWM1			0x0024 /*  HCI Current Power Mode 1 */
-#define SDIO_REG_HCPWM2			0x0026 /*  HCI Current Power Mode 2 */
-#define SDIO_REG_FREE_TXPG_SEQ	0x0028 /*  Free Tx Page Sequence */
-#define SDIO_REG_HTSFR_INFO		0x0030 /*  HTSF Informaion */
 #define SDIO_REG_HRPWM1			0x0080 /*  HCI Request Power Mode 1 */
-#define SDIO_REG_HRPWM2			0x0082 /*  HCI Request Power Mode 2 */
-#define SDIO_REG_HPS_CLKR			0x0084 /*  HCI Power Save Clock */
 #define SDIO_REG_HSUS_CTRL			0x0086 /*  SDIO HCI Suspend Control */
-#define SDIO_REG_HIMR_ON			0x0090 /* SDIO Host Extension Interrupt Mask Always */
-#define SDIO_REG_HISR_ON			0x0091 /* SDIO Host Extension Interrupt Status Always */
 
 #define SDIO_HIMR_DISABLED			0
 
 /*  RTL8723/RTL8188E SDIO Host Interrupt Mask Register */
 #define SDIO_HIMR_RX_REQUEST_MSK		BIT0
 #define SDIO_HIMR_AVAL_MSK			BIT1
-#define SDIO_HIMR_TXERR_MSK			BIT2
-#define SDIO_HIMR_RXERR_MSK			BIT3
-#define SDIO_HIMR_TXFOVW_MSK			BIT4
-#define SDIO_HIMR_RXFOVW_MSK			BIT5
-#define SDIO_HIMR_TXBCNOK_MSK			BIT6
-#define SDIO_HIMR_TXBCNERR_MSK		BIT7
-#define SDIO_HIMR_BCNERLY_INT_MSK		BIT16
-#define SDIO_HIMR_C2HCMD_MSK			BIT17
-#define SDIO_HIMR_CPWM1_MSK			BIT18
-#define SDIO_HIMR_CPWM2_MSK			BIT19
-#define SDIO_HIMR_HSISR_IND_MSK		BIT20
-#define SDIO_HIMR_GTINT3_IND_MSK		BIT21
-#define SDIO_HIMR_GTINT4_IND_MSK		BIT22
-#define SDIO_HIMR_PSTIMEOUT_MSK		BIT23
-#define SDIO_HIMR_OCPINT_MSK			BIT24
-#define SDIO_HIMR_ATIMEND_MSK			BIT25
-#define SDIO_HIMR_ATIMEND_E_MSK		BIT26
-#define SDIO_HIMR_CTWEND_MSK			BIT27
 
 /*  SDIO Host Interrupt Service Routine */
 #define SDIO_HISR_RX_REQUEST			BIT0

@@ -1305,7 +556,6 @@
 #define SDIO_HISR_RXFOVW				BIT5
 #define SDIO_HISR_TXBCNOK				BIT6
 #define SDIO_HISR_TXBCNERR				BIT7
-#define SDIO_HISR_BCNERLY_INT			BIT16
 #define SDIO_HISR_C2HCMD				BIT17
 #define SDIO_HISR_CPWM1				BIT18
 #define SDIO_HISR_CPWM2				BIT19

@@ -1314,9 +564,6 @@
 #define SDIO_HISR_GTINT4_IND			BIT22
 #define SDIO_HISR_PSTIMEOUT			BIT23
 #define SDIO_HISR_OCPINT				BIT24
-#define SDIO_HISR_ATIMEND				BIT25
-#define SDIO_HISR_ATIMEND_E			BIT26
-#define SDIO_HISR_CTWEND				BIT27
 
 #define MASK_SDIO_HISR_CLEAR		(SDIO_HISR_TXERR |\
 									SDIO_HISR_RXERR |\

@@ -1333,15 +580,8 @@
 									SDIO_HISR_PSTIMEOUT |\
 									SDIO_HISR_OCPINT)
 
-/*  SDIO HCI Suspend Control Register */
-#define HCI_RESUME_PWR_RDY			BIT1
-#define HCI_SUS_CTRL					BIT0
-
 /*  SDIO Tx FIFO related */
 #define SDIO_TX_FREE_PG_QUEUE			4	/*  The number of Tx FIFO free page */
-#define SDIO_TX_FIFO_PAGE_SZ			128
-
-#define MAX_TX_AGG_PACKET_NUMBER	0x8
 
 /*  */
 /*  */

@@ -1349,46 +589,14 @@
 /*  */
 /*  */
 
-/* 2 USB Information (0xFE17) */
-#define USB_IS_HIGH_SPEED			0
-#define USB_IS_FULL_SPEED			1
-#define USB_SPEED_MASK				BIT(5)
-
-#define USB_NORMAL_SIE_EP_MASK	0xF
-#define USB_NORMAL_SIE_EP_SHIFT	4
-
-/* 2 Special Option */
-#define USB_AGG_EN				BIT(3)
-
-/*  0; Use interrupt endpoint to upload interrupt pkt */
-/*  1; Use bulk endpoint to upload interrupt pkt, */
-#define INT_BULK_SEL			BIT(4)
-
 /* 2REG_C2HEVT_CLEAR */
 #define C2H_EVT_HOST_CLOSE		0x00	/*  Set by driver and notify FW that the driver has read the C2H command message */
 #define C2H_EVT_FW_CLOSE		0xFF	/*  Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */
 
-
 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
-#define WL_HWPDN_EN			BIT0	/*  Enable GPIO[9] as WiFi HW PDn source */
 #define WL_HWPDN_SL			BIT1	/*  WiFi HW PDn polarity control */
 #define WL_FUNC_EN				BIT2	/*  WiFi function enable */
-#define WL_HWROF_EN			BIT3	/*  Enable GPIO[9] as WiFi RF HW PDn source */
-#define BT_HWPDN_EN			BIT16	/*  Enable GPIO[11] as BT HW PDn source */
-#define BT_HWPDN_SL			BIT17	/*  BT HW PDn polarity control */
 #define BT_FUNC_EN				BIT18	/*  BT function enable */
-#define BT_HWROF_EN			BIT19	/*  Enable GPIO[11] as BT/GPS RF HW PDn source */
-#define GPS_HWPDN_EN			BIT20	/*  Enable GPIO[10] as GPS HW PDn source */
-#define GPS_HWPDN_SL			BIT21	/*  GPS HW PDn polarity control */
 #define GPS_FUNC_EN			BIT22	/*  GPS function enable */
 
-/*  */
-/*  General definitions */
-/*  */
-
-#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B		255
-
-#define POLLING_LLT_THRESHOLD				20
-#define POLLING_READY_TIMEOUT_COUNT		1000
-
 #endif /* __HAL_COMMON_H__ */

index b0b1ac1090fc..0791b85b7c57 100644
@@ -14,56 +14,5 @@
 /*  4. Page9(0x900) */
 /*  */
 #define rDPDT_control				0x92c
-#define rfe_ctrl_anta_src				0x930
-#define rS0S1_PathSwitch			0x948
-#define AGC_table_select				0xb2c
-
-/*  */
-/*  PageB(0xB00) */
-/*  */
-#define rPdp_AntA						0xb00
-#define rPdp_AntA_4						0xb04
-#define rPdp_AntA_8						0xb08
-#define rPdp_AntA_C						0xb0c
-#define rPdp_AntA_10					0xb10
-#define rPdp_AntA_14					0xb14
-#define rPdp_AntA_18					0xb18
-#define rPdp_AntA_1C					0xb1c
-#define rPdp_AntA_20					0xb20
-#define rPdp_AntA_24					0xb24
-
-#define rConfig_Pmpd_AntA				0xb28
-#define rConfig_ram64x16				0xb2c
-
-#define rBndA							0xb30
-#define rHssiPar						0xb34
-
-#define rConfig_AntA					0xb68
-#define rConfig_AntB					0xb6c
-
-#define rPdp_AntB						0xb70
-#define rPdp_AntB_4						0xb74
-#define rPdp_AntB_8						0xb78
-#define rPdp_AntB_C						0xb7c
-#define rPdp_AntB_10					0xb80
-#define rPdp_AntB_14					0xb84
-#define rPdp_AntB_18					0xb88
-#define rPdp_AntB_1C					0xb8c
-#define rPdp_AntB_20					0xb90
-#define rPdp_AntB_24					0xb94
-
-#define rConfig_Pmpd_AntB				0xb98
-
-#define rBndB							0xba0
-
-#define rAPK							0xbd8
-#define rPm_Rx0_AntA					0xbdc
-#define rPm_Rx1_AntA					0xbe0
-#define rPm_Rx2_AntA					0xbe4
-#define rPm_Rx3_AntA					0xbe8
-#define rPm_Rx0_AntB					0xbec
-#define rPm_Rx1_AntB					0xbf0
-#define rPm_Rx2_AntB					0xbf4
-#define rPm_Rx3_AntB					0xbf8
 
 #endif

index 586a3dabc5ca..292c18b62537 100644
@@ -1108,5 +1108,6 @@
 
 /*--------------------------Define Parameters-------------------------------*/
 
+#define rDPDT_control				0x92c
 
 #endif	/* __INC_HAL8192SPHYREG_H */

index 0791b85b7c57..da549b773243 100644
@@ -9,10 +9,5 @@
 
 #include <Hal8192CPhyReg.h>
 
-/*  BB Register Definition */
-/*  */
-/*  4. Page9(0x900) */
-/*  */
-#define rDPDT_control				0x92c
 
 #endif

deleted file mode 100644
index da549b773243..000000000000
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __INC_HAL8723BPHYREG_H__
-#define __INC_HAL8723BPHYREG_H__
-
-#include <Hal8192CPhyReg.h>
-
-
-#endif

index c1d7249e3e9d..f9ecd9047d52 100644
@@ -17,7 +17,7 @@
 #include "rtl8723b_cmd.h"
 #include "rtw_mp.h"
 #include "hal_pwr_seq.h"
-#include "hal_phy_reg_8723b.h"
+#include "Hal8192CPhyReg.h"
 #include "hal_phy_cfg.h"
 
 /*  */

index 292c18b62537..f8cf2aee5157 100644
@@ -46,59 +46,11 @@
 /*  5. Other definition for BB/RF R/W */
 /*  */
 
-
-/*  */
-/*  1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
-/*  1. Page1(0x100) */
-/*  */
-#define		rPMAC_Reset					0x100
-#define		rPMAC_TxStart					0x104
-#define		rPMAC_TxLegacySIG				0x108
-#define		rPMAC_TxHTSIG1				0x10c
-#define		rPMAC_TxHTSIG2				0x110
-#define		rPMAC_PHYDebug				0x114
-#define		rPMAC_TxPacketNum				0x118
-#define		rPMAC_TxIdle					0x11c
-#define		rPMAC_TxMACHeader0			0x120
-#define		rPMAC_TxMACHeader1			0x124
-#define		rPMAC_TxMACHeader2			0x128
-#define		rPMAC_TxMACHeader3			0x12c
-#define		rPMAC_TxMACHeader4			0x130
-#define		rPMAC_TxMACHeader5			0x134
-#define		rPMAC_TxDataType				0x138
-#define		rPMAC_TxRandomSeed			0x13c
-#define		rPMAC_CCKPLCPPreamble			0x140
-#define		rPMAC_CCKPLCPHeader			0x144
-#define		rPMAC_CCKCRC16				0x148
-#define		rPMAC_OFDMRxCRC32OK			0x170
-#define		rPMAC_OFDMRxCRC32Er			0x174
-#define		rPMAC_OFDMRxParityEr			0x178
-#define		rPMAC_OFDMRxCRC8Er			0x17c
-#define		rPMAC_CCKCRxRC16Er			0x180
-#define		rPMAC_CCKCRxRC32Er			0x184
-#define		rPMAC_CCKCRxRC32OK			0x188
-#define		rPMAC_TxStatus					0x18c
-
-/*  */
-/*  2. Page2(0x200) */
-/*  */
-/*  The following two definition are only used for USB interface. */
-#define		RF_BB_CMD_ADDR				0x02c0	/*  RF/BB read/write command address. */
-#define		RF_BB_CMD_DATA				0x02c4	/*  RF/BB read/write command data. */
-
 /*  */
 /*  3. Page8(0x800) */
 /*  */
 #define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC  RF BW Setting?? */
 
-#define		rFPGA0_TxInfo				0x804	/*  Status report?? */
-#define		rFPGA0_PSDFunction			0x808
-
-#define		rFPGA0_TxGainStage			0x80c	/*  Set TX PWR init gain? */
-
-#define		rFPGA0_RFTiming1			0x810	/*  Useless now */
-#define		rFPGA0_RFTiming2			0x814
-
 #define		rFPGA0_XA_HSSIParameter1		0x820	/*  RF 3 wire register */
 #define		rFPGA0_XA_HSSIParameter2		0x824
 #define		rFPGA0_XB_HSSIParameter1		0x828

@@ -113,10 +65,6 @@
 #define		rFPGA0_XA_LSSIParameter		0x840
 #define		rFPGA0_XB_LSSIParameter		0x844
 
-#define		rFPGA0_RFWakeUpParameter		0x850	/*  Useless now */
-#define		rFPGA0_RFSleepUpParameter		0x854
-
-#define		rFPGA0_XAB_SwitchControl		0x858	/*  RF Channel switch */
 #define		rFPGA0_XCD_SwitchControl		0x85c
 
 #define		rFPGA0_XA_RFInterfaceOE		0x860	/*  RF Channel switch */

@@ -127,33 +75,17 @@
 #define		rFPGA0_XAB_RFInterfaceSW		0x870	/*  RF Interface Software Control */
 #define		rFPGA0_XCD_RFInterfaceSW		0x874
 
-#define		rFPGA0_XAB_RFParameter		0x878	/*  RF Parameter */
-#define		rFPGA0_XCD_RFParameter		0x87c
-
-#define		rFPGA0_AnalogParameter1		0x880	/*  Crystal cap setting RF-R/W protection for parameter4?? */
-#define		rFPGA0_AnalogParameter2		0x884
-#define		rFPGA0_AnalogParameter3		0x888	/*  Useless now */
-#define		rFPGA0_AnalogParameter4		0x88c
-
 #define		rFPGA0_XA_LSSIReadBack		0x8a0	/*  Transceiver LSSI Readback */
 #define		rFPGA0_XB_LSSIReadBack		0x8a4
-#define		rFPGA0_XC_LSSIReadBack		0x8a8
-#define		rFPGA0_XD_LSSIReadBack		0x8ac
 
-#define		rFPGA0_PSDReport				0x8b4	/*  Useless now */
 #define		TransceiverA_HSPI_Readback	0x8b8	/*  Transceiver A HSPI Readback */
 #define		TransceiverB_HSPI_Readback	0x8bc	/*  Transceiver B HSPI Readback */
-#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/*  Useless now  RF Interface Readback Value */
-#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/*  Useless now */
 
 /*  */
 /*  4. Page9(0x900) */
 /*  */
 #define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC  RF BW Setting?? */
 
-#define		rFPGA1_TxBlock				0x904	/*  Useless now */
-#define		rFPGA1_DebugSelect			0x908	/*  Useless now */
-#define		rFPGA1_TxInfo				0x90c	/*  Useless now  Status report?? */
 #define		rS0S1_PathSwitch			0x948
 
 /*  */

@@ -163,135 +95,39 @@
 #define		rCCK0_System				0xa00
 
 #define		rCCK0_AFESetting			0xa04	/*  Disable init gain now Select RX path by RSSI */
-#define		rCCK0_CCA					0xa08	/*  Disable init gain now Init gain */
-
-#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-
-#define		rCCK0_RxHP					0xa14
 
-#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-
-#define		rCCK0_TxFilter1				0xa20
-#define		rCCK0_TxFilter2				0xa24
-#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-#define		rCCK0_TRSSIReport			0xa50
-#define		rCCK0_RxReport				0xa54  /* 0xa57 */
-#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
-#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
 /*  */
 /*  PageB(0xB00) */
 /*  */
-#define		rPdp_AntA				0xb00
-#define		rPdp_AntA_4				0xb04
-#define		rConfig_Pmpd_AntA			0xb28
 #define		rConfig_AntA				0xb68
 #define		rConfig_AntB				0xb6c
-#define		rPdp_AntB					0xb70
-#define		rPdp_AntB_4				0xb74
-#define		rConfig_Pmpd_AntB			0xb98
-#define		rAPK						0xbd8
 
 /*  */
 /*  6. PageC(0xC00) */
 /*  */
-#define		rOFDM0_LSTF				0xc00
-
 #define		rOFDM0_TRxPathEnable		0xc04
 #define		rOFDM0_TRMuxPar			0xc08
-#define		rOFDM0_TRSWIsolation		0xc0c
 
-#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
 #define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
-#define		rOFDM0_XBRxAFE				0xc18
 #define		rOFDM0_XBRxIQImbalance		0xc1c
-#define		rOFDM0_XCRxAFE				0xc20
-#define		rOFDM0_XCRxIQImbalance		0xc24
-#define		rOFDM0_XDRxAFE				0xc28
-#define		rOFDM0_XDRxIQImbalance		0xc2c
-
-#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	DM tune init gain */
-#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
 
 #define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
 #define		rOFDM0_ECCAThreshold		0xc4c /*  energy CCA */
 
-#define		rOFDM0_XAAGCCore1			0xc50	/*  DIG */
-#define		rOFDM0_XAAGCCore2			0xc54
-#define		rOFDM0_XBAGCCore1			0xc58
-#define		rOFDM0_XBAGCCore2			0xc5c
-#define		rOFDM0_XCAGCCore1			0xc60
-#define		rOFDM0_XCAGCCore2			0xc64
-#define		rOFDM0_XDAGCCore1			0xc68
-#define		rOFDM0_XDAGCCore2			0xc6c
-
-#define		rOFDM0_AGCParameter1			0xc70
-#define		rOFDM0_AGCParameter2			0xc74
 #define		rOFDM0_AGCRSSITable			0xc78
-#define		rOFDM0_HTSTFAGC				0xc7c
 
 #define		rOFDM0_XATxIQImbalance		0xc80	/*  TX PWR TRACK and DIG */
-#define		rOFDM0_XATxAFE				0xc84
 #define		rOFDM0_XBTxIQImbalance		0xc88
-#define		rOFDM0_XBTxAFE				0xc8c
-#define		rOFDM0_XCTxIQImbalance		0xc90
 #define		rOFDM0_XCTxAFE					0xc94
-#define		rOFDM0_XDTxIQImbalance		0xc98
 #define		rOFDM0_XDTxAFE				0xc9c
 
 #define		rOFDM0_RxIQExtAnta			0xca0
-#define		rOFDM0_TxCoeff1				0xca4
-#define		rOFDM0_TxCoeff2				0xca8
-#define		rOFDM0_TxCoeff3				0xcac
-#define		rOFDM0_TxCoeff4				0xcb0
-#define		rOFDM0_TxCoeff5				0xcb4
-#define		rOFDM0_TxCoeff6				0xcb8
-#define		rOFDM0_RxHPParameter			0xce0
 #define		rOFDM0_TxPseudoNoiseWgt		0xce4
-#define		rOFDM0_FrameSync				0xcf0
-#define		rOFDM0_DFSReport				0xcf4
 
 /*  */
 /*  7. PageD(0xD00) */
 /*  */
 #define		rOFDM1_LSTF					0xd00
-#define		rOFDM1_TRxPathEnable			0xd04
-
-#define		rOFDM1_CFO						0xd08	/*  No setting now */
-#define		rOFDM1_CSI1					0xd10
-#define		rOFDM1_SBD						0xd14
-#define		rOFDM1_CSI2					0xd18
-#define		rOFDM1_CFOTracking			0xd2c
-#define		rOFDM1_TRxMesaure1			0xd34
-#define		rOFDM1_IntfDet					0xd3c
-#define		rOFDM1_PseudoNoiseStateAB		0xd50
-#define		rOFDM1_PseudoNoiseStateCD		0xd54
-#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-
-#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-
-#define		rOFDM_ShortCFOAB				0xdac	/*  No setting now */
-#define		rOFDM_ShortCFOCD				0xdb0
-#define		rOFDM_LongCFOAB				0xdb4
-#define		rOFDM_LongCFOCD				0xdb8
-#define		rOFDM_TailCFOAB				0xdbc
-#define		rOFDM_TailCFOCD				0xdc0
-#define		rOFDM_PWMeasure1			0xdc4
-#define		rOFDM_PWMeasure2			0xdc8
-#define		rOFDM_BWReport				0xdcc
-#define		rOFDM_AGCReport				0xdd0
-#define		rOFDM_RxSNR					0xdd4
-#define		rOFDM_RxEVMCSI				0xdd8
-#define		rOFDM_SIGReport				0xddc
-
 
 /*  */
 /*  8. PageE(0xE00) */

@@ -316,7 +152,6 @@
 #define		rRx_IQK_Tone_B				0xe54
 #define		rTx_IQK_PI_B					0xe58
 #define		rRx_IQK_PI_B					0xe5c
-#define		rIQK_AGC_Cont				0xe60
 
 #define		rBlue_Tooth					0xe6c
 #define		rRx_Wait_CCA					0xe70

@@ -331,19 +166,9 @@
 #define		rTx_Power_Before_IQK_A		0xe94
 #define		rTx_Power_After_IQK_A			0xe9c
 
-#define		rRx_Power_Before_IQK_A		0xea0
 #define		rRx_Power_Before_IQK_A_2		0xea4
-#define		rRx_Power_After_IQK_A			0xea8
 #define		rRx_Power_After_IQK_A_2		0xeac
 
-#define		rTx_Power_Before_IQK_B		0xeb4
-#define		rTx_Power_After_IQK_B			0xebc
-
-#define		rRx_Power_Before_IQK_B		0xec0
-#define		rRx_Power_Before_IQK_B_2		0xec4
-#define		rRx_Power_After_IQK_B			0xec8
-#define		rRx_Power_After_IQK_B_2		0xecc
-
 #define		rRx_OFDM					0xed0
 #define		rRx_Wait_RIFS				0xed4
 #define		rRx_TO_Rx					0xed8

@@ -351,709 +176,43 @@
 #define		rSleep						0xee0
 #define		rPMPD_ANAEN				0xeec
 
-/*  */
-/*  7. RF Register 0x00-0x2E (RF 8256) */
-/*     RF-0222D 0x00-3F */
-/*  */
-/* Zebra1 */
-#define		rZebra1_HSSIEnable				0x0	/*  Useless now */
-#define		rZebra1_TRxEnable1				0x1
-#define		rZebra1_TRxEnable2				0x2
-#define		rZebra1_AGC					0x4
-#define		rZebra1_ChargePump			0x5
-#define		rZebra1_Channel				0x7	/*  RF channel switch */
-
-/* endif */
-#define		rZebra1_TxGain					0x8	/*  Useless now */
-#define		rZebra1_TxLPF					0x9
-#define		rZebra1_RxLPF					0xb
-#define		rZebra1_RxHPFCorner			0xc
-
-/* Zebra4 */
-#define		rGlobalCtrl						0	/*  Useless now */
-#define		rRTL8256_TxLPF					19
-#define		rRTL8256_RxLPF					11
-
-/* RTL8258 */
-#define		rRTL8258_TxLPF					0x11	/*  Useless now */
-#define		rRTL8258_RxLPF					0x13
-#define		rRTL8258_RSSILPF				0xa
-
 /*  */
 /*  RL6052 Register definition */
 /*  */
 #define		RF_AC						0x00	/*  */
 
-#define		RF_IQADJ_G1				0x01	/*  */
-#define		RF_IQADJ_G2				0x02	/*  */
-#define		RF_BS_PA_APSET_G1_G4		0x03
-#define		RF_BS_PA_APSET_G5_G8		0x04
-#define		RF_POW_TRSW				0x05	/*  */
-
-#define		RF_GAIN_RX					0x06	/*  */
-#define		RF_GAIN_TX					0x07	/*  */
-
 #define		RF_TXM_IDAC				0x08	/*  */
-#define		RF_IPA_G					0x09	/*  */
-#define		RF_TXBIAS_G				0x0A
-#define		RF_TXPA_AG					0x0B
-#define		RF_IPA_A					0x0C	/*  */
-#define		RF_TXBIAS_A				0x0D
-#define		RF_BS_PA_APSET_G9_G11	0x0E
-#define		RF_BS_IQGEN				0x0F	/*  */
 
-#define		RF_MODE1					0x10	/*  */
-#define		RF_MODE2					0x11	/*  */
-
-#define		RF_RX_AGC_HP				0x12	/*  */
-#define		RF_TX_AGC					0x13	/*  */
-#define		RF_BIAS						0x14	/*  */
-#define		RF_IPA						0x15	/*  */
-#define		RF_TXBIAS					0x16 /*  */
-#define		RF_POW_ABILITY			0x17	/*  */
-#define		RF_MODE_AG				0x18	/*  */
-#define		rRfChannel					0x18	/*  RF channel and BW switch */
 #define		RF_CHNLBW					0x18	/*  RF channel and BW switch */
-#define		RF_TOP						0x19	/*  */
-
-#define		RF_RX_G1					0x1A	/*  */
-#define		RF_RX_G2					0x1B	/*  */
-
-#define		RF_RX_BB2					0x1C	/*  */
-#define		RF_RX_BB1					0x1D	/*  */
-
-#define		RF_RCK1					0x1E	/*  */
-#define		RF_RCK2					0x1F	/*  */
-
-#define		RF_TX_G1					0x20	/*  */
-#define		RF_TX_G2					0x21	/*  */
-#define		RF_TX_G3					0x22	/*  */
-
-#define		RF_TX_BB1					0x23	/*  */
-
-#define		RF_T_METER					0x24	/*  */
-
-#define		RF_SYN_G1					0x25	/*  RF TX Power control */
-#define		RF_SYN_G2					0x26	/*  RF TX Power control */
-#define		RF_SYN_G3					0x27	/*  RF TX Power control */
-#define		RF_SYN_G4					0x28	/*  RF TX Power control */
-#define		RF_SYN_G5					0x29	/*  RF TX Power control */
-#define		RF_SYN_G6					0x2A	/*  RF TX Power control */
-#define		RF_SYN_G7					0x2B	/*  RF TX Power control */
-#define		RF_SYN_G8					0x2C	/*  RF TX Power control */
 
 #define		RF_RCK_OS					0x30	/*  RF TX PA control */
 
 #define		RF_TXPA_G1					0x31	/*  RF TX PA control */
 #define		RF_TXPA_G2					0x32	/*  RF TX PA control */
-#define		RF_TXPA_G3					0x33	/*  RF TX PA control */
-#define		RF_TX_BIAS_A				0x35
-#define		RF_TX_BIAS_D				0x36
-#define		RF_LOBF_9					0x38
-#define		RF_RXRF_A3					0x3C	/*  */
-#define		RF_TRSW						0x3F
 
-#define		RF_TXRF_A2					0x41
-#define		RF_TXPA_G4					0x46
-#define		RF_TXPA_A4					0x4B
-#define		RF_0x52						0x52
 #define		RF_WE_LUT					0xEF
-#define		RF_S0S1						0xB0
-
-/*  */
-/* Bit Mask */
-/*  */
-/*  1. Page1(0x100) */
-#define		bBBResetB						0x100	/*  Useless now? */
-#define		bGlobalResetB					0x200
-#define		bOFDMTxStart					0x4
-#define		bCCKTxStart						0x8
-#define		bCRC32Debug					0x100
-#define		bPMACLoopback					0x10
-#define		bTxLSIG							0xffffff
-#define		bOFDMTxRate					0xf
-#define		bOFDMTxReserved				0x10
-#define		bOFDMTxLength					0x1ffe0
-#define		bOFDMTxParity					0x20000
-#define		bTxHTSIG1						0xffffff
-#define		bTxHTMCSRate					0x7f
-#define		bTxHTBW						0x80
-#define		bTxHTLength					0xffff00
-#define		bTxHTSIG2						0xffffff
-#define		bTxHTSmoothing					0x1
-#define		bTxHTSounding					0x2
-#define		bTxHTReserved					0x4
-#define		bTxHTAggreation				0x8
-#define		bTxHTSTBC						0x30
-#define		bTxHTAdvanceCoding			0x40
-#define		bTxHTShortGI					0x80
-#define		bTxHTNumberHT_LTF			0x300
-#define		bTxHTCRC8						0x3fc00
-#define		bCounterReset					0x10000
-#define		bNumOfOFDMTx					0xffff
-#define		bNumOfCCKTx					0xffff0000
-#define		bTxIdleInterval					0xffff
-#define		bOFDMService					0xffff0000
-#define		bTxMACHeader					0xffffffff
-#define		bTxDataInit						0xff
-#define		bTxHTMode						0x100
-#define		bTxDataType					0x30000
-#define		bTxRandomSeed					0xffffffff
-#define		bCCKTxPreamble					0x1
-#define		bCCKTxSFD						0xffff0000
-#define		bCCKTxSIG						0xff
-#define		bCCKTxService					0xff00
-#define		bCCKLengthExt					0x8000
-#define		bCCKTxLength					0xffff0000
-#define		bCCKTxCRC16					0xffff
-#define		bCCKTxStatus					0x1
-#define		bOFDMTxStatus					0x2
-
-#define			IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
 
 /*  2. Page8(0x800) */
 #define		bRFMOD							0x1	/*  Reg 0x800 rFPGA0_RFMOD */
-#define		bJapanMode						0x2
-#define		bCCKTxSC						0x30
-#define		bCCKEn							0x1000000
-#define		bOFDMEn						0x2000000
-
-#define		bOFDMRxADCPhase				0x10000	/*  Useless now */
-#define		bOFDMTxDACPhase				0x40000
-#define		bXATxAGC					0x3f
-
-#define		bAntennaSelect				0x0300
-
-#define		bXBTxAGC					0xf00	/*  Reg 80c rFPGA0_TxGainStage */
-#define		bXCTxAGC					0xf000
-#define		bXDTxAGC					0xf0000
-
-#define		bPAStart					0xf0000000	/*  Useless now */
-#define		bTRStart					0x00f00000
-#define		bRFStart					0x0000f000
-#define		bBBStart					0x000000f0
-#define		bBBCCKStart				0x0000000f
-#define		bPAEnd						0xf          /* Reg0x814 */
-#define		bTREnd						0x0f000000
-#define		bRFEnd						0x000f0000
-#define		bCCAMask					0x000000f0   /* T2R */
-#define		bR2RCCAMask				0x00000f00
-#define		bHSSI_R2TDelay				0xf8000000
-#define		bHSSI_T2RDelay				0xf80000
-#define		bContTxHSSI				0x400     /* chane gain at continue Tx */
-#define		bIGFromCCK				0x200
-#define		bAGCAddress				0x3f
-#define		bRxHPTx						0x7000
-#define		bRxHPT2R					0x38000
-#define		bRxHPCCKIni				0xc0000
-#define		bAGCTxCode				0xc00000
-#define		bAGCRxCode				0x300000
 
 #define		b3WireDataLength			0x800	/*  Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
 #define		b3WireAddressLength			0x400
 
-#define		b3WireRFPowerDown			0x1	/*  Useless now */
-/* define bHWSISelect				0x8 */
-#define		b2GPAPEPolarity				0x80000000
-#define		bRFSW_TxDefaultAnt			0x3
-#define		bRFSW_TxOptionAnt			0x30
-#define		bRFSW_RxDefaultAnt			0x300
-#define		bRFSW_RxOptionAnt			0x3000
-#define		bRFSI_3WireData				0x1
-#define		bRFSI_3WireClock			0x2
-#define		bRFSI_3WireLoad				0x4
-#define		bRFSI_3WireRW				0x8
-#define		bRFSI_3Wire					0xf
-
 #define		bRFSI_RFENV				0x10	/*  Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
 
-#define		bRFSI_TRSW				0x20	/*  Useless now */
-#define		bRFSI_TRSWB				0x40
-#define		bRFSI_ANTSW				0x100
-#define		bRFSI_ANTSWB				0x200
-#define		bRFSI_PAPE					0x400
-#define		bBandSelect					0x1
-#define		bHTSIG2_GI					0x80
-#define		bHTSIG2_Smoothing			0x01
-#define		bHTSIG2_Sounding			0x02
-#define		bHTSIG2_Aggreaton			0x08
-#define		bHTSIG2_STBC				0x30
-#define		bHTSIG2_AdvCoding			0x40
-#define		bHTSIG2_NumOfHTLTF		0x300
-#define		bHTSIG2_CRC8				0x3fc
-#define		bHTSIG1_MCS				0x7f
-#define		bHTSIG1_BandWidth			0x80
-#define		bHTSIG1_HTLength			0xffff
-#define		bLSIG_Rate					0xf
-#define		bLSIG_Reserved				0x10
-#define		bLSIG_Length				0x1fffe
-#define		bLSIG_Parity					0x20
-#define		bCCKRxPhase				0x4
-
 #define		bLSSIReadAddress			0x7f800000   /*  T65 RF */
 
 #define		bLSSIReadEdge				0x80000000   /* LSSI "Read" edge signal */
 
 #define		bLSSIReadBackData			0xfffff		/*  T65 RF */
 
-#define		bLSSIReadOKFlag				0x1000	/*  Useless now */
-#define		bCCKSampleRate				0x8       /* 0: 44MHz, 1:88MHz */
-#define		bRegulator0Standby			0x1
-#define		bRegulatorPLLStandby			0x2
-#define		bRegulator1Standby			0x4
-#define		bPLLPowerUp				0x8
-#define		bDPLLPowerUp				0x10
-#define		bDA10PowerUp				0x20
-#define		bAD7PowerUp				0x200
-#define		bDA6PowerUp				0x2000
-#define		bXtalPowerUp				0x4000
-#define		b40MDClkPowerUP				0x8000
-#define		bDA6DebugMode				0x20000
-#define		bDA6Swing					0x380000
-
-#define		bADClkPhase				0x4000000	/*  Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-
-#define		b80MClkDelay				0x18000000	/*  Useless */
-#define		bAFEWatchDogEnable			0x20000000
-
-#define		bXtalCap01					0xc0000000	/*  Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-#define		bXtalCap23					0x3
-#define		bXtalCap92x					0x0f000000
-#define			bXtalCap					0x0f000000
-
-#define		bIntDifClkEnable			0x400	/*  Useless */
-#define		bExtSigClkEnable			0x800
-#define		bBandgapMbiasPowerUp		0x10000
-#define		bAD11SHGain				0xc0000
-#define		bAD11InputRange				0x700000
-#define		bAD11OPCurrent				0x3800000
-#define		bIPathLoopback				0x4000000
-#define		bQPathLoopback				0x8000000
-#define		bAFELoopback				0x10000000
-#define		bDA10Swing				0x7e0
-#define		bDA10Reverse				0x800
-#define		bDAClkSource				0x1000
-#define		bAD7InputRange				0x6000
-#define		bAD7Gain					0x38000
-#define		bAD7OutputCMMode			0x40000
-#define		bAD7InputCMMode				0x380000
-#define		bAD7Current					0xc00000
-#define		bRegulatorAdjust			0x7000000
-#define		bAD11PowerUpAtTx			0x1
-#define		bDA10PSAtTx				0x10
-#define		bAD11PowerUpAtRx			0x100
-#define		bDA10PSAtRx				0x1000
-#define		bCCKRxAGCFormat				0x200
-#define		bPSDFFTSamplepPoint			0xc000
-#define		bPSDAverageNum				0x3000
-#define		bIQPathControl				0xc00
-#define		bPSDFreq					0x3ff
-#define		bPSDAntennaPath				0x30
-#define		bPSDIQSwitch				0x40
-#define		bPSDRxTrigger				0x400000
-#define		bPSDTxTrigger				0x80000000
-#define		bPSDSineToneScale			0x7f000000
-#define		bPSDReport					0xffff
-
-/*  3. Page9(0x900) */
-#define		bOFDMTxSC				0x30000000	/*  Useless */
-#define		bCCKTxOn					0x1
-#define		bOFDMTxOn				0x2
-#define		bDebugPage				0xfff  /* reset debug page and also HWord, LWord */
-#define		bDebugItem				0xff   /* reset debug page and LWord */
-#define		bAntL					0x10
-#define		bAntNonHT					0x100
-#define		bAntHT1					0x1000
-#define		bAntHT2						0x10000
-#define		bAntHT1S1					0x100000
-#define		bAntNonHTS1				0x1000000
-
 /*  4. PageA(0xA00) */
-#define		bCCKBBMode				0x3	/*  Useless */
-#define		bCCKTxPowerSaving		0x80
-#define		bCCKRxPowerSaving		0x40
-
 #define		bCCKSideBand			0x10	/*  Reg 0xa00 rCCK0_System 20/40 switch */
 
-#define		bCCKScramble			0x8	/*  Useless */
-#define		bCCKAntDiversity		0x8000
-#define		bCCKCarrierRecovery		0x4000
-#define		bCCKTxRate				0x3000
-#define		bCCKDCCancel			0x0800
-#define		bCCKISICancel			0x0400
-#define		bCCKMatchFilter			0x0200
-#define		bCCKEqualizer			0x0100
-#define		bCCKPreambleDetect		0x800000
-#define		bCCKFastFalseCCA		0x400000
-#define		bCCKChEstStart			0x300000
-#define		bCCKCCACount			0x080000
-#define		bCCKcs_lim				0x070000
-#define		bCCKBistMode			0x80000000
-#define		bCCKCCAMask			0x40000000
-#define		bCCKTxDACPhase		0x4
-#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
-#define		bCCKr_cp_mode0		0x0100
-#define		bCCKTxDCOffset			0xf0
-#define		bCCKRxDCOffset			0xf
-#define		bCCKCCAMode			0xc000
-#define		bCCKFalseCS_lim			0x3f00
-#define		bCCKCS_ratio			0xc00000
-#define		bCCKCorgBit_sel			0x300000
-#define		bCCKPD_lim				0x0f0000
-#define		bCCKNewCCA			0x80000000
-#define		bCCKRxHPofIG			0x8000
-#define		bCCKRxIG				0x7f00
-#define		bCCKLNAPolarity			0x800000
-#define		bCCKRx1stGain			0x7f0000
-#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
-#define		bCCKRxAGCSatLevel		0x1f000000
-#define		bCCKRxAGCSatCount		0xe0
-#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
-#define		bCCKFixedRxAGC			0x8000
-#define		bCCKAntennaPolarity		0x2000
-#define		bCCKTxFilterType		0x0c00
-#define		bCCKRxAGCReportType	0x0300
-#define		bCCKRxDAGCEn			0x80000000
-#define		bCCKRxDAGCPeriod		0x20000000
-#define		bCCKRxDAGCSatLevel		0x1f000000
-#define		bCCKTimingRecovery		0x800000
-#define		bCCKTxC0				0x3f0000
-#define		bCCKTxC1				0x3f000000
-#define		bCCKTxC2				0x3f
-#define		bCCKTxC3				0x3f00
-#define		bCCKTxC4				0x3f0000
-#define		bCCKTxC5				0x3f000000
-#define		bCCKTxC6				0x3f
-#define		bCCKTxC7				0x3f00
-#define		bCCKDebugPort			0xff0000
-#define		bCCKDACDebug			0x0f000000
-#define		bCCKFalseAlarmEnable	0x8000
-#define		bCCKFalseAlarmRead		0x4000
-#define		bCCKTRSSI				0x7f
-#define		bCCKRxAGCReport		0xfe
-#define		bCCKRxReport_AntSel	0x80000000
-#define		bCCKRxReport_MFOff		0x40000000
-#define		bCCKRxRxReport_SQLoss	0x20000000
-#define		bCCKRxReport_Pktloss	0x10000000
-#define		bCCKRxReport_Lockedbit	0x08000000
-#define		bCCKRxReport_RateError	0x04000000
-#define		bCCKRxReport_RxRate	0x03000000
-#define		bCCKRxFACounterLower	0xff
-#define		bCCKRxFACounterUpper	0xff000000
-#define		bCCKRxHPAGCStart		0xe000
-#define		bCCKRxHPAGCFinal		0x1c00
-#define		bCCKRxFalseAlarmEnable	0x8000
-#define		bCCKFACounterFreeze	0x4000
-#define		bCCKTxPathSel			0x10000000
-#define		bCCKDefaultRxPath		0xc000000
-#define		bCCKOptionRxPath		0x3000000
-
-/*  5. PageC(0xC00) */
-#define		bNumOfSTF				0x3	/*  Useless */
-#define		bShift_L					0xc0
-#define		bGI_TH					0xc
-#define		bRxPathA				0x1
-#define		bRxPathB				0x2
-#define		bRxPathC				0x4
-#define		bRxPathD				0x8
-#define		bTxPathA				0x1
-#define		bTxPathB				0x2
-#define		bTxPathC				0x4
-#define		bTxPathD				0x8
-#define		bTRSSIFreq				0x200
-#define		bADCBackoff				0x3000
-#define		bDFIRBackoff			0xc000
-#define		bTRSSILatchPhase		0x10000
-#define		bRxIDCOffset			0xff
-#define		bRxQDCOffset			0xff00
-#define		bRxDFIRMode			0x1800000
-#define		bRxDCNFType			0xe000000
-#define		bRXIQImb_A				0x3ff
-#define		bRXIQImb_B				0xfc00
-#define		bRXIQImb_C				0x3f0000
-#define		bRXIQImb_D				0xffc00000
-#define		bDC_dc_Notch			0x60000
-#define		bRxNBINotch			0x1f000000
-#define		bPD_TH					0xf
-#define		bPD_TH_Opt2			0xc000
-#define		bPWED_TH				0x700
-#define		bIfMF_Win_L			0x800
-#define		bPD_Option				0x1000
-#define		bMF_Win_L				0xe000
-#define		bBW_Search_L			0x30000
-#define		bwin_enh_L				0xc0000
-#define		bBW_TH					0x700000
-#define		bED_TH2				0x3800000
-#define		bBW_option				0x4000000
-#define		bRatio_TH				0x18000000
-#define		bWindow_L				0xe0000000
-#define		bSBD_Option				0x1
-#define		bFrame_TH				0x1c
-#define		bFS_Option				0x60
-#define		bDC_Slope_check		0x80
-#define		bFGuard_Counter_DC_L	0xe00
-#define		bFrame_Weight_Short	0x7000
-#define		bSub_Tune				0xe00000
-#define		bFrame_DC_Length		0xe000000
-#define		bSBD_start_offset		0x30000000
-#define		bFrame_TH_2			0x7
-#define		bFrame_GI2_TH			0x38
-#define		bGI2_Sync_en			0x40
-#define		bSarch_Short_Early		0x300
-#define		bSarch_Short_Late		0xc00
-#define		bSarch_GI2_Late		0x70000
-#define		bCFOAntSum				0x1
-#define		bCFOAcc				0x2
-#define		bCFOStartOffset			0xc
-#define		bCFOLookBack			0x70
-#define		bCFOSumWeight			0x80
-#define		bDAGCEnable			0x10000
-#define		bTXIQImb_A				0x3ff
-#define		bTXIQImb_B				0xfc00
-#define		bTXIQImb_C				0x3f0000
-#define		bTXIQImb_D				0xffc00000
-#define		bTxIDCOffset			0xff
-#define		bTxQDCOffset			0xff00
-#define		bTxDFIRMode			0x10000
-#define		bTxPesudoNoiseOn		0x4000000
-#define		bTxPesudoNoise_A		0xff
-#define		bTxPesudoNoise_B		0xff00
-#define		bTxPesudoNoise_C		0xff0000
-#define		bTxPesudoNoise_D		0xff000000
-#define		bCCADropOption			0x20000
-#define		bCCADropThres			0xfff00000
-#define		bEDCCA_H				0xf
-#define		bEDCCA_L				0xf0
-#define		bLambda_ED			0x300
-#define		bRxInitialGain			0x7f
-#define		bRxAntDivEn				0x80
-#define		bRxAGCAddressForLNA	0x7f00
-#define		bRxHighPowerFlow		0x8000
-#define		bRxAGCFreezeThres		0xc0000
-#define		bRxFreezeStep_AGC1	0x300000
-#define		bRxFreezeStep_AGC2	0xc00000
-#define		bRxFreezeStep_AGC3	0x3000000
-#define		bRxFreezeStep_AGC0	0xc000000
-#define		bRxRssi_Cmp_En			0x10000000
-#define		bRxQuickAGCEn			0x20000000
-#define		bRxAGCFreezeThresMode	0x40000000
-#define		bRxOverFlowCheckType	0x80000000
-#define		bRxAGCShift				0x7f
-#define		bTRSW_Tri_Only			0x80
-#define		bPowerThres			0x300
-#define		bRxAGCEn				0x1
-#define		bRxAGCTogetherEn		0x2
-#define		bRxAGCMin				0x4
-#define		bRxHP_Ini				0x7
-#define		bRxHP_TRLNA			0x70
-#define		bRxHP_RSSI				0x700
-#define		bRxHP_BBP1				0x7000
-#define		bRxHP_BBP2				0x70000
-#define		bRxHP_BBP3				0x700000
-#define		bRSSI_H					0x7f0000     /* the threshold for high power */
-#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
-#define		bRxSettle_TRSW			0x7
-#define		bRxSettle_LNA			0x38
-#define		bRxSettle_RSSI			0x1c0
-#define		bRxSettle_BBP			0xe00
-#define		bRxSettle_RxHP			0x7000
-#define		bRxSettle_AntSW_RSSI	0x38000
-#define		bRxSettle_AntSW		0xc0000
-#define		bRxProcessTime_DAGC	0x300000
-#define		bRxSettle_HSSI			0x400000
-#define		bRxProcessTime_BBPPW	0x800000
-#define		bRxAntennaPowerShift	0x3000000
-#define		bRSSITableSelect		0xc000000
-#define		bRxHP_Final				0x7000000
-#define		bRxHTSettle_BBP			0x7
-#define		bRxHTSettle_HSSI		0x8
-#define		bRxHTSettle_RxHP		0x70
-#define		bRxHTSettle_BBPPW		0x80
-#define		bRxHTSettle_Idle		0x300
-#define		bRxHTSettle_Reserved	0x1c00
-#define		bRxHTRxHPEn			0x8000
-#define		bRxHTAGCFreezeThres	0x30000
-#define		bRxHTAGCTogetherEn	0x40000
-#define		bRxHTAGCMin			0x80000
-#define		bRxHTAGCEn				0x100000
-#define		bRxHTDAGCEn			0x200000
-#define		bRxHTRxHP_BBP			0x1c00000
-#define		bRxHTRxHP_Final		0xe0000000
-#define		bRxPWRatioTH			0x3
-#define		bRxPWRatioEn			0x4
-#define		bRxMFHold				0x3800
-#define		bRxPD_Delay_TH1		0x38
-#define		bRxPD_Delay_TH2		0x1c0
-#define		bRxPD_DC_COUNT_MAX	0x600
-/* define bRxMF_Hold               0x3800 */
-#define		bRxPD_Delay_TH			0x8000
-#define		bRxProcess_Delay		0xf0000
-#define		bRxSearchrange_GI2_Early	0x700000
-#define		bRxFrame_Guard_Counter_L	0x3800000
-#define		bRxSGI_Guard_L			0xc000000
-#define		bRxSGI_Search_L		0x30000000
-#define		bRxSGI_TH				0xc0000000
-#define		bDFSCnt0				0xff
-#define		bDFSCnt1				0xff00
-#define		bDFSFlag				0xf0000
-#define		bMFWeightSum			0x300000
-#define		bMinIdxTH				0x7f000000
-#define		bDAFormat				0x40000
-#define		bTxChEmuEnable		0x01000000
-#define		bTRSWIsolation_A		0x7f
-#define		bTRSWIsolation_B		0x7f00
-#define		bTRSWIsolation_C		0x7f0000
-#define		bTRSWIsolation_D		0x7f000000
-#define		bExtLNAGain				0x7c00
-
-/*  6. PageE(0xE00) */
-#define		bSTBCEn				0x4	/*  Useless */
-#define		bAntennaMapping		0x10
-#define		bNss					0x20
-#define		bCFOAntSumD			0x200
-#define		bPHYCounterReset		0x8000000
-#define		bCFOReportGet			0x4000000
-#define		bOFDMContinueTx		0x10000000
-#define		bOFDMSingleCarrier		0x20000000
-#define		bOFDMSingleTone		0x40000000
-/* define bRxPath1                 0x01 */
-/* define bRxPath2                 0x02 */
-/* define bRxPath3                 0x04 */
-/* define bRxPath4                 0x08 */
-/* define bTxPath1                 0x10 */
-/* define bTxPath2                 0x20 */
-#define		bHTDetect			0x100
-#define		bCFOEn				0x10000
-#define		bCFOValue			0xfff00000
-#define		bSigTone_Re		0x3f
-#define		bSigTone_Im		0x7f00
-#define		bCounter_CCA		0xffff
-#define		bCounter_ParityFail	0xffff0000
-#define		bCounter_RateIllegal		0xffff
-#define		bCounter_CRC8Fail	0xffff0000
-#define		bCounter_MCSNoSupport	0xffff
-#define		bCounter_FastSync	0xffff
-#define		bShortCFO			0xfff
-#define		bShortCFOTLength	12   /* total */
-#define		bShortCFOFLength	11   /* fraction */
-#define		bLongCFO			0x7ff
-#define		bLongCFOTLength	11
-#define		bLongCFOFLength	11
-#define		bTailCFO			0x1fff
-#define		bTailCFOTLength		13
-#define		bTailCFOFLength		12
-#define		bmax_en_pwdB		0xffff
-#define		bCC_power_dB		0xffff0000
-#define		bnoise_pwdB		0xffff
-#define		bPowerMeasTLength	10
-#define		bPowerMeasFLength	3
-#define		bRx_HT_BW			0x1
-#define		bRxSC				0x6
-#define		bRx_HT				0x8
-#define		bNB_intf_det_on		0x1
-#define		bIntf_win_len_cfg	0x30
-#define		bNB_Intf_TH_cfg		0x1c0
-#define		bRFGain				0x3f
-#define		bTableSel			0x40
-#define		bTRSW				0x80
-#define		bRxSNR_A			0xff
-#define		bRxSNR_B			0xff00
-#define		bRxSNR_C			0xff0000
-#define		bRxSNR_D			0xff000000
-#define		bSNREVMTLength		8
-#define		bSNREVMFLength		1
-#define		bCSI1st				0xff
-#define		bCSI2nd				0xff00
-#define		bRxEVM1st			0xff0000
-#define		bRxEVM2nd			0xff000000
-#define		bSIGEVM			0xff
-#define		bPWDB				0xff00
-#define		bSGIEN				0x10000
-
-#define		bSFactorQAM1		0xf	/*  Useless */
-#define		bSFactorQAM2		0xf0
-#define		bSFactorQAM3		0xf00
-#define		bSFactorQAM4		0xf000
-#define		bSFactorQAM5		0xf0000
-#define		bSFactorQAM6		0xf0000
-#define		bSFactorQAM7		0xf00000
-#define		bSFactorQAM8		0xf000000
-#define		bSFactorQAM9		0xf0000000
-#define		bCSIScheme			0x100000
-
-#define		bNoiseLvlTopSet		0x3	/*  Useless */
-#define		bChSmooth			0x4
-#define		bChSmoothCfg1		0x38
-#define		bChSmoothCfg2		0x1c0
-#define		bChSmoothCfg3		0xe00
-#define		bChSmoothCfg4		0x7000
-#define		bMRCMode			0x800000
-#define		bTHEVMCfg			0x7000000
-
-#define		bLoopFitType		0x1	/*  Useless */
-#define		bUpdCFO			0x40
-#define		bUpdCFOOffData		0x80
-#define		bAdvUpdCFO			0x100
-#define		bAdvTimeCtrl		0x800
-#define		bUpdClko			0x1000
-#define		bFC					0x6000
-#define		bTrackingMode		0x8000
-#define		bPhCmpEnable		0x10000
-#define		bUpdClkoLTF		0x20000
-#define		bComChCFO			0x40000
-#define		bCSIEstiMode		0x80000
-#define		bAdvUpdEqz			0x100000
-#define		bUChCfg				0x7000000
-#define		bUpdEqz			0x8000000
-
-/* Rx Pseduo noise */
-#define		bRxPesudoNoiseOn		0x20000000	/*  Useless */
-#define		bRxPesudoNoise_A		0xff
-#define		bRxPesudoNoise_B		0xff00
-#define		bRxPesudoNoise_C		0xff0000
-#define		bRxPesudoNoise_D		0xff000000
-#define		bPesudoNoiseState_A	0xffff
-#define		bPesudoNoiseState_B	0xffff0000
-#define		bPesudoNoiseState_C	0xffff
-#define		bPesudoNoiseState_D	0xffff0000
-
-/* 7. RF Register */
-/* Zebra1 */
-#define		bZebra1_HSSIEnable		0x8		/*  Useless */
-#define		bZebra1_TRxControl		0xc00
-#define		bZebra1_TRxGainSetting	0x07f
-#define		bZebra1_RxCorner		0xc00
-#define		bZebra1_TxChargePump	0x38
-#define		bZebra1_RxChargePump	0x7
-#define		bZebra1_ChannelNum	0xf80
-#define		bZebra1_TxLPFBW		0x400
-#define		bZebra1_RxLPFBW		0x600
-
-/* Zebra4 */
-#define		bRTL8256RegModeCtrl1	0x100	/*  Useless */
-#define		bRTL8256RegModeCtrl0	0x40
-#define		bRTL8256_TxLPFBW		0x18
-#define		bRTL8256_RxLPFBW		0x600
-
-/* RTL8258 */
-#define		bRTL8258_TxLPFBW		0xc	/*  Useless */
-#define		bRTL8258_RxLPFBW		0xc00
-#define		bRTL8258_RSSILPFBW	0xc0
-
-
 /*  */
 /*  Other Definition */
 /*  */
 
-/* byte endable for sb_write */
-#define		bByte0				0x1	/*  Useless */
-#define		bByte1				0x2
-#define		bByte2				0x4
-#define		bByte3				0x8
-#define		bWord0				0x3
-#define		bWord1				0xc
-#define		bDWord				0xf
-
 /* for PutRegsetting & GetRegSetting BitMask */
 #define		bMaskByte0			0xff	/*  Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
 #define		bMaskByte1			0xff00

@@ -1065,48 +224,8 @@
 #define		bMaskH3Bytes		0xffffff00
 #define		bMask12Bits			0xfff
 #define		bMaskH4Bits			0xf0000000
-#define		bMaskOFDM_D		0xffc00000
-#define		bMaskCCK			0x3f3f3f3f
-
 
 #define		bEnable			0x1	/*  Useless */
-#define		bDisable		0x0
-
-#define		LeftAntenna		0x0	/*  Useless */
-#define		RightAntenna	0x1
-
-#define		tCheckTxStatus		500   /* 500ms Useless */
-#define		tUpdateRxCounter	100   /* 100ms */
-
-#define		rateCCK		0	/*  Useless */
-#define		rateOFDM	1
-#define		rateHT		2
-
-/* define Register-End */
-#define		bPMAC_End			0x1ff	/*  Useless */
-#define		bFPGAPHY0_End		0x8ff
-#define		bFPGAPHY1_End		0x9ff
-#define		bCCKPHY0_End		0xaff
-#define		bOFDMPHY0_End		0xcff
-#define		bOFDMPHY1_End		0xdff
-
-/* define max debug item in each debug page */
-/* define bMaxItem_FPGA_PHY0        0x9 */
-/* define bMaxItem_FPGA_PHY1        0x3 */
-/* define bMaxItem_PHY_11B          0x16 */
-/* define bMaxItem_OFDM_PHY0        0x29 */
-/* define bMaxItem_OFDM_PHY1        0x0 */
-
-#define		bPMACControl		0x0		/*  Useless */
-#define		bWMACControl		0x1
-#define		bWNICControl		0x2
-
-#define		PathA			0x0	/*  Useless */
-#define		PathB			0x1
-#define		PathC			0x2
-#define		PathD			0x3
-
-/*--------------------------Define Parameters-------------------------------*/
 
 #define rDPDT_control				0x92c
 

index 6bf7933cbe4a..0b327a70aa15 100644
@@ -19,420 +19,47 @@
 #ifndef __INC_HAL8723BREG_H
 #define __INC_HAL8723BREG_H
 
-/*  */
-/*  */
-/*  */
-
-/*  */
-/*  */
-/*	0x0000h ~ 0x00FFh	System Configuration */
-/*  */
-/*  */
-#define REG_SYS_ISO_CTRL_8723B			0x0000	/*  2 Byte */
-#define REG_SYS_FUNC_EN_8723B			0x0002	/*  2 Byte */
-#define REG_APS_FSMCO_8723B			0x0004	/*  4 Byte */
-#define REG_SYS_CLKR_8723B			0x0008	/*  2 Byte */
-#define REG_9346CR_8723B			0x000A	/*  2 Byte */
-#define REG_EE_VPD_8723B			0x000C	/*  2 Byte */
-#define REG_AFE_MISC_8723B			0x0010	/*  1 Byte */
-#define REG_SPS0_CTRL_8723B			0x0011	/*  7 Byte */
-#define REG_SPS_OCP_CFG_8723B			0x0018	/*  4 Byte */
-#define REG_RSV_CTRL_8723B			0x001C	/*  3 Byte */
-#define REG_RF_CTRL_8723B			0x001F	/*  1 Byte */
-#define REG_LPLDO_CTRL_8723B			0x0023	/*  1 Byte */
-#define REG_AFE_XTAL_CTRL_8723B			0x0024	/*  4 Byte */
-#define REG_AFE_PLL_CTRL_8723B			0x0028	/*  4 Byte */
-#define REG_MAC_PLL_CTRL_EXT_8723B		0x002c	/*  4 Byte */
-#define REG_EFUSE_CTRL_8723B			0x0030
-#define REG_EFUSE_TEST_8723B			0x0034
-#define REG_PWR_DATA_8723B			0x0038
-#define REG_CAL_TIMER_8723B			0x003C
-#define REG_ACLK_MON_8723B			0x003E
-#define REG_GPIO_MUXCFG_8723B			0x0040
-#define REG_GPIO_IO_SEL_8723B			0x0042
-#define REG_MAC_PINMUX_CFG_8723B		0x0043
-#define REG_GPIO_PIN_CTRL_8723B			0x0044
-#define REG_GPIO_INTM_8723B			0x0048
-#define REG_LEDCFG0_8723B			0x004C
-#define REG_LEDCFG1_8723B			0x004D
-#define REG_LEDCFG2_8723B			0x004E
-#define REG_LEDCFG3_8723B			0x004F
-#define REG_FSIMR_8723B				0x0050
-#define REG_FSISR_8723B				0x0054
-#define REG_HSIMR_8723B				0x0058
-#define REG_HSISR_8723B				0x005c
-#define REG_GPIO_EXT_CTRL			0x0060
-#define REG_MULTI_FUNC_CTRL_8723B		0x0068
-#define REG_GPIO_STATUS_8723B			0x006C
-#define REG_SDIO_CTRL_8723B			0x0070
-#define REG_OPT_CTRL_8723B			0x0074
-#define REG_AFE_XTAL_CTRL_EXT_8723B		0x0078
-#define REG_MCUFWDL_8723B			0x0080
-#define REG_BT_PATCH_STATUS_8723B		0x0088
-#define REG_HIMR0_8723B				0x00B0
-#define REG_HISR0_8723B				0x00B4
-#define REG_HIMR1_8723B				0x00B8
-#define REG_HISR1_8723B				0x00BC
-#define REG_PMC_DBG_CTRL2_8723B			0x00CC
-#define	REG_EFUSE_BURN_GNT_8723B		0x00CF
-#define REG_HPON_FSM_8723B			0x00EC
-#define REG_SYS_CFG_8723B			0x00F0
-#define REG_SYS_CFG1_8723B			0x00FC
-#define REG_ROM_VERSION				0x00FD
-
 /*  */
 /*  */
 /*	0x0100h ~ 0x01FFh	MACTOP General Configuration */
 /*  */
 /*  */
-#define REG_CR_8723B				0x0100
-#define REG_PBP_8723B				0x0104
-#define REG_PKT_BUFF_ACCESS_CTRL_8723B		0x0106
-#define REG_TRXDMA_CTRL_8723B			0x010C
-#define REG_TRXFF_BNDY_8723B			0x0114
-#define REG_TRXFF_STATUS_8723B			0x0118
-#define REG_RXFF_PTR_8723B			0x011C
-#define REG_CPWM_8723B				0x012F
-#define REG_FWIMR_8723B				0x0130
-#define REG_FWISR_8723B				0x0134
-#define REG_FTIMR_8723B				0x0138
-#define REG_PKTBUF_DBG_CTRL_8723B		0x0140
-#define REG_RXPKTBUF_CTRL_8723B			0x0142
-#define REG_PKTBUF_DBG_DATA_L_8723B		0x0144
-#define REG_PKTBUF_DBG_DATA_H_8723B		0x0148
-
-#define REG_TC0_CTRL_8723B			0x0150
-#define REG_TC1_CTRL_8723B			0x0154
-#define REG_TC2_CTRL_8723B			0x0158
-#define REG_TC3_CTRL_8723B			0x015C
-#define REG_TC4_CTRL_8723B			0x0160
-#define REG_TCUNIT_BASE_8723B			0x0164
-#define REG_RSVD3_8723B				0x0168
-#define REG_C2HEVT_MSG_NORMAL_8723B		0x01A0
 #define REG_C2HEVT_CMD_SEQ_88XX			0x01A1
-#define REG_C2HEVT_CMD_CONTENT_88XX		0x01A2
 #define REG_C2HEVT_CMD_LEN_88XX			0x01AE
-#define REG_C2HEVT_CLEAR_8723B			0x01AF
-#define REG_MCUTST_1_8723B			0x01C0
-#define REG_MCUTST_WOWLAN_8723B			0x01C7
-#define REG_FMETHR_8723B			0x01C8
-#define REG_HMETFR_8723B			0x01CC
-#define REG_HMEBOX_0_8723B			0x01D0
-#define REG_HMEBOX_1_8723B			0x01D4
-#define REG_HMEBOX_2_8723B			0x01D8
-#define REG_HMEBOX_3_8723B			0x01DC
-#define REG_LLT_INIT_8723B			0x01E0
-#define REG_HMEBOX_EXT0_8723B			0x01F0
-#define REG_HMEBOX_EXT1_8723B			0x01F4
-#define REG_HMEBOX_EXT2_8723B			0x01F8
-#define REG_HMEBOX_EXT3_8723B			0x01FC
 
 /*  */
 /*  */
 /*	0x0200h ~ 0x027Fh	TXDMA Configuration */
 /*  */
 /*  */
-#define REG_RQPN_8723B				0x0200
-#define REG_FIFOPAGE_8723B			0x0204
-#define REG_DWBCN0_CTRL_8723B			REG_TDECTRL
-#define REG_TXDMA_OFFSET_CHK_8723B		0x020C
-#define REG_TXDMA_STATUS_8723B			0x0210
-#define REG_RQPN_NPQ_8723B			0x0214
 #define REG_DWBCN1_CTRL_8723B			0x0228
 
-/*  */
-/*  */
-/*	0x0280h ~ 0x02FFh	RXDMA Configuration */
-/*  */
-/*  */
-#define REG_RXDMA_AGG_PG_TH_8723B		0x0280
-#define REG_FW_UPD_RDPTR_8723B			0x0284 /*  FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
-#define REG_RXDMA_CONTROL_8723B			0x0286 /*  Control the RX DMA. */
-#define REG_RXPKT_NUM_8723B			0x0287 /*  The number of packets in RXPKTBUF. */
-#define REG_RXDMA_STATUS_8723B			0x0288
-#define REG_RXDMA_PRO_8723B			0x0290
-#define REG_EARLY_MODE_CONTROL_8723B		0x02BC
-#define REG_RSVD5_8723B				0x02F0
-#define REG_RSVD6_8723B				0x02F4
-
-/*  */
-/*  */
-/*	0x0300h ~ 0x03FFh	PCIe */
-/*  */
-/*  */
-#define	REG_PCIE_CTRL_REG_8723B			0x0300
-#define	REG_INT_MIG_8723B			0x0304	/*  Interrupt Migration */
-#define	REG_BCNQ_DESA_8723B			0x0308	/*  TX Beacon Descriptor Address */
-#define	REG_HQ_DESA_8723B			0x0310	/*  TX High Queue Descriptor Address */
-#define	REG_MGQ_DESA_8723B			0x0318	/*  TX Manage Queue Descriptor Address */
-#define	REG_VOQ_DESA_8723B			0x0320	/*  TX VO Queue Descriptor Address */
-#define	REG_VIQ_DESA_8723B			0x0328	/*  TX VI Queue Descriptor Address */
-#define	REG_BEQ_DESA_8723B			0x0330	/*  TX BE Queue Descriptor Address */
-#define	REG_BKQ_DESA_8723B			0x0338	/*  TX BK Queue Descriptor Address */
-#define	REG_RX_DESA_8723B			0x0340	/*  RX Queue	Descriptor Address */
-#define	REG_DBI_WDATA_8723B			0x0348	/*  DBI Write Data */
-#define	REG_DBI_RDATA_8723B			0x034C	/*  DBI Read Data */
-#define	REG_DBI_ADDR_8723B			0x0350	/*  DBI Address */
-#define	REG_DBI_FLAG_8723B			0x0352	/*  DBI Read/Write Flag */
-#define	REG_MDIO_WDATA_8723B			0x0354	/*  MDIO for Write PCIE PHY */
-#define	REG_MDIO_RDATA_8723B			0x0356	/*  MDIO for Reads PCIE PHY */
-#define	REG_MDIO_CTL_8723B			0x0358	/*  MDIO for Control */
-#define	REG_DBG_SEL_8723B			0x0360	/*  Debug Selection Register */
-#define	REG_PCIE_HRPWM_8723B			0x0361	/* PCIe RPWM */
-#define	REG_PCIE_HCPWM_8723B			0x0363	/* PCIe CPWM */
-#define	REG_PCIE_MULTIFET_CTRL_8723B		0x036A	/* PCIE Multi-Fethc Control */
-
 /*  spec version 11 */
 /*  */
 /*  */
 /*	0x0400h ~ 0x047Fh	Protocol Configuration */
 /*  */
 /*  */
-#define REG_VOQ_INFORMATION_8723B		0x0400
-#define REG_VIQ_INFORMATION_8723B		0x0404
-#define REG_BEQ_INFORMATION_8723B		0x0408
-#define REG_BKQ_INFORMATION_8723B		0x040C
-#define REG_MGQ_INFORMATION_8723B		0x0410
-#define REG_HGQ_INFORMATION_8723B		0x0414
-#define REG_BCNQ_INFORMATION_8723B		0x0418
-#define REG_TXPKT_EMPTY_8723B			0x041A
-
 #define REG_FWHW_TXQ_CTRL_8723B			0x0420
-#define REG_HWSEQ_CTRL_8723B			0x0423
-#define REG_TXPKTBUF_BCNQ_BDNY_8723B		0x0424
-#define REG_TXPKTBUF_MGQ_BDNY_8723B		0x0425
-#define REG_LIFECTRL_CTRL_8723B			0x0426
-#define REG_MULTI_BCNQ_OFFSET_8723B		0x0427
-#define REG_SPEC_SIFS_8723B			0x0428
-#define REG_RL_8723B				0x042A
-#define REG_TXBF_CTRL_8723B			0x042C
-#define REG_DARFRC_8723B			0x0430
-#define REG_RARFRC_8723B			0x0438
-#define REG_RRSR_8723B				0x0440
 #define REG_ARFR0_8723B				0x0444
 #define REG_ARFR1_8723B				0x044C
 #define REG_CCK_CHECK_8723B			0x0454
 #define REG_AMPDU_MAX_TIME_8723B		0x0456
-#define REG_TXPKTBUF_BCNQ_BDNY1_8723B		0x0457
 
 #define REG_AMPDU_MAX_LENGTH_8723B		0x0458
-#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B	0x045D
-#define REG_NDPA_OPT_CTRL_8723B			0x045F
-#define REG_FAST_EDCA_CTRL_8723B		0x0460
-#define REG_RD_RESP_PKT_TH_8723B		0x0463
 #define REG_DATA_SC_8723B			0x0483
-#define REG_TXRPT_START_OFFSET			0x04AC
-#define REG_POWER_STAGE1_8723B			0x04B4
-#define REG_POWER_STAGE2_8723B			0x04B8
-#define REG_AMPDU_BURST_MODE_8723B		0x04BC
-#define REG_PKT_VO_VI_LIFE_TIME_8723B		0x04C0
-#define REG_PKT_BE_BK_LIFE_TIME_8723B		0x04C2
-#define REG_STBC_SETTING_8723B			0x04C4
-#define REG_HT_SINGLE_AMPDU_8723B		0x04C7
-#define REG_PROT_MODE_CTRL_8723B		0x04C8
 #define REG_MAX_AGGR_NUM_8723B			0x04CA
-#define REG_RTS_MAX_AGGR_NUM_8723B		0x04CB
-#define REG_BAR_MODE_CTRL_8723B			0x04CC
-#define REG_RA_TRY_RATE_AGG_LMT_8723B		0x04CF
-#define REG_MACID_PKT_DROP0_8723B		0x04D0
-#define REG_MACID_PKT_SLEEP_8723B		0x04D4
 
 /*  */
 /*  */
 /*	0x0500h ~ 0x05FFh	EDCA Configuration */
 /*  */
 /*  */
-#define REG_EDCA_VO_PARAM_8723B			0x0500
-#define REG_EDCA_VI_PARAM_8723B			0x0504
-#define REG_EDCA_BE_PARAM_8723B			0x0508
-#define REG_EDCA_BK_PARAM_8723B			0x050C
-#define REG_BCNTCFG_8723B			0x0510
 #define REG_PIFS_8723B				0x0512
-#define REG_RDG_PIFS_8723B			0x0513
-#define REG_SIFS_CTX_8723B			0x0514
-#define REG_SIFS_TRX_8723B			0x0516
-#define REG_AGGR_BREAK_TIME_8723B		0x051A
-#define REG_SLOT_8723B				0x051B
-#define REG_TX_PTCL_CTRL_8723B			0x0520
-#define REG_TXPAUSE_8723B			0x0522
-#define REG_DIS_TXREQ_CLR_8723B			0x0523
-#define REG_RD_CTRL_8723B			0x0524
-/*  */
-/*  Format for offset 540h-542h: */
-/*	[3:0]:	TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */
-/*	[7:4]:	Reserved. */
-/*	[19:8]:	TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */
-/*	[23:20]: Reserved */
-/*  Description: */
-/* 	              | */
-/*      |<--Setup--|--Hold------------>| */
-/* 	--------------|---------------------- */
-/*                 | */
-/*                TBTT */
-/*  Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */
-/*  Described by Designer Tim and Bruce, 2011-01-14. */
-/*  */
-#define REG_TBTT_PROHIBIT_8723B			0x0540
-#define REG_RD_NAV_NXT_8723B			0x0544
-#define REG_NAV_PROT_LEN_8723B			0x0546
-#define REG_BCN_CTRL_8723B			0x0550
-#define REG_BCN_CTRL_1_8723B			0x0551
-#define REG_MBID_NUM_8723B			0x0552
-#define REG_DUAL_TSF_RST_8723B			0x0553
-#define REG_BCN_INTERVAL_8723B			0x0554
-#define REG_DRVERLYINT_8723B			0x0558
-#define REG_BCNDMATIM_8723B			0x0559
-#define REG_ATIMWND_8723B			0x055A
-#define REG_USTIME_TSF_8723B			0x055C
-#define REG_BCN_MAX_ERR_8723B			0x055D
-#define REG_RXTSF_OFFSET_CCK_8723B		0x055E
-#define REG_RXTSF_OFFSET_OFDM_8723B		0x055F
-#define REG_TSFTR_8723B				0x0560
-#define REG_CTWND_8723B				0x0572
-#define REG_SECONDARY_CCA_CTRL_8723B		0x0577
-#define REG_PSTIMER_8723B			0x0580
-#define REG_TIMER0_8723B			0x0584
-#define REG_TIMER1_8723B			0x0588
-#define REG_ACMHWCTRL_8723B			0x05C0
-#define REG_SCH_TXCMD_8723B			0x05F8
 
 /*	0x0600h ~ 0x07FFh	WMAC Configuration */
-#define REG_MAC_CR_8723B			0x0600
-#define REG_TCR_8723B				0x0604
-#define REG_RCR_8723B				0x0608
 #define REG_RX_PKT_LIMIT_8723B			0x060C
-#define REG_RX_DLK_TIME_8723B			0x060D
-#define REG_RX_DRVINFO_SZ_8723B			0x060F
-
-#define REG_MACID_8723B				0x0610
-#define REG_BSSID_8723B				0x0618
-#define REG_MAR_8723B				0x0620
-#define REG_MBIDCAMCFG_8723B			0x0628
 
-#define REG_USTIME_EDCA_8723B			0x0638
-#define REG_MAC_SPEC_SIFS_8723B			0x063A
-#define REG_RESP_SIFP_CCK_8723B			0x063C
-#define REG_RESP_SIFS_OFDM_8723B		0x063E
-#define REG_ACKTO_8723B				0x0640
-#define REG_CTS2TO_8723B			0x0641
-#define REG_EIFS_8723B				0x0642
-
-#define REG_NAV_UPPER_8723B			0x0652	/*  unit of 128 */
 #define REG_TRXPTCL_CTL_8723B			0x0668
 
-/*  Security */
-#define REG_CAMCMD_8723B			0x0670
-#define REG_CAMWRITE_8723B			0x0674
-#define REG_CAMREAD_8723B			0x0678
-#define REG_CAMDBG_8723B			0x067C
-#define REG_SECCFG_8723B			0x0680
-
-/*  Power */
-#define REG_WOW_CTRL_8723B			0x0690
-#define REG_PS_RX_INFO_8723B			0x0692
-#define REG_UAPSD_TID_8723B			0x0693
-#define REG_WKFMCAM_CMD_8723B			0x0698
-#define REG_WKFMCAM_NUM_8723B			0x0698
-#define REG_WKFMCAM_RWD_8723B			0x069C
-#define REG_RXFLTMAP0_8723B			0x06A0
-#define REG_RXFLTMAP1_8723B			0x06A2
-#define REG_RXFLTMAP2_8723B			0x06A4
-#define REG_BCN_PSR_RPT_8723B			0x06A8
-#define REG_BT_COEX_TABLE_8723B			0x06C0
-#define REG_BFMER0_INFO_8723B			0x06E4
-#define REG_BFMER1_INFO_8723B			0x06EC
-#define REG_CSI_RPT_PARAM_BW20_8723B		0x06F4
-#define REG_CSI_RPT_PARAM_BW40_8723B		0x06F8
-#define REG_CSI_RPT_PARAM_BW80_8723B		0x06FC
-
-/*  Hardware Port 2 */
-#define REG_MACID1_8723B			0x0700
-#define REG_BSSID1_8723B			0x0708
-#define REG_BFMEE_SEL_8723B			0x0714
-#define REG_SND_PTCL_CTRL_8723B			0x0718
-
-/*	Redifine 8192C register definition for compatibility */
-
-/*  TODO: use these definition when using REG_xxx naming rule. */
-/*  NOTE: DO NOT Remove these definition. Use later. */
-#define	EFUSE_CTRL_8723B	REG_EFUSE_CTRL_8723B	/*  E-Fuse Control. */
-#define	EFUSE_TEST_8723B	REG_EFUSE_TEST_8723B	/*  E-Fuse Test. */
-#define	MSR_8723B		(REG_CR_8723B + 2)	/*  Media Status register */
-#define	ISR_8723B		REG_HISR0_8723B
-#define	TSFR_8723B		REG_TSFTR_8723B		/*  Timing Sync Function Timer Register. */
-
-#define PBP_8723B		REG_PBP_8723B
-
-/*  Redifine MACID register, to compatible prior ICs. */
-#define	IDR0_8723B		REG_MACID_8723B		/*  MAC ID Register, Offset 0x0050-0x0053 */
-#define	IDR4_8723B		(REG_MACID_8723B + 4)	/*  MAC ID Register, Offset 0x0054-0x0055 */
-
-/*  9. Security Control Registers	(Offset:) */
-#define	RWCAM_8723B		REG_CAMCMD_8723B	/* IN 8190 Data Sheet is called CAMcmd */
-#define	WCAMI_8723B		REG_CAMWRITE_8723B	/*  Software write CAM input content */
-#define	RCAMO_8723B		REG_CAMREAD_8723B	/*  Software read/write CAM config */
-#define	CAMDBG_8723B		REG_CAMDBG_8723B
-#define	SECR_8723B		REG_SECCFG_8723B	/* Security Configuration Register */
-
-/*        8195 IMR/ISR bits		(offset 0xB0,  8bits) */
-#define	IMR_DISABLED_8723B		0
-/*  IMR DW0(0x00B0-00B3) Bit 0-31 */
-#define	IMR_TIMER2_8723B		BIT31	/*  Timeout interrupt 2 */
-#define	IMR_TIMER1_8723B		BIT30	/*  Timeout interrupt 1 */
-#define	IMR_PSTIMEOUT_8723B		BIT29	/*  Power Save Time Out Interrupt */
-#define	IMR_GTINT4_8723B		BIT28	/*  When GTIMER4 expires, this bit is set to 1 */
-#define	IMR_GTINT3_8723B		BIT27	/*  When GTIMER3 expires, this bit is set to 1 */
-#define	IMR_TXBCN0ERR_8723B		BIT26	/*  Transmit Beacon0 Error */
-#define	IMR_TXBCN0OK_8723B		BIT25	/*  Transmit Beacon0 OK */
-#define	IMR_TSF_BIT32_TOGGLE_8723B	BIT24	/*  TSF Timer BIT32 toggle indication interrupt */
-#define	IMR_BCNDMAINT0_8723B		BIT20	/*  Beacon DMA Interrupt 0 */
-#define	IMR_BCNDERR0_8723B		BIT16	/*  Beacon Queue DMA OK0 */
-#define	IMR_HSISR_IND_ON_INT_8723B	BIT15	/*  HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-#define	IMR_BCNDMAINT_E_8723B		BIT14	/*  Beacon DMA Interrupt Extension for Win7 */
-#define	IMR_ATIMEND_8723B		BIT12	/*  CTWidnow End or ATIM Window End */
-#define	IMR_C2HCMD_8723B		BIT10	/*  CPU to Host Command INT Status, Write 1 clear */
-#define	IMR_CPWM2_8723B			BIT9	/*  CPU power Mode exchange INT Status, Write 1 clear */
-#define	IMR_CPWM_8723B			BIT8	/*  CPU power Mode exchange INT Status, Write 1 clear */
-#define	IMR_HIGHDOK_8723B		BIT7	/*  High Queue DMA OK */
-#define	IMR_MGNTDOK_8723B		BIT6	/*  Management Queue DMA OK */
-#define	IMR_BKDOK_8723B			BIT5	/*  AC_BK DMA OK */
-#define	IMR_BEDOK_8723B			BIT4	/*  AC_BE DMA OK */
-#define	IMR_VIDOK_8723B			BIT3	/*  AC_VI DMA OK */
-#define	IMR_VODOK_8723B			BIT2	/*  AC_VO DMA OK */
-#define	IMR_RDU_8723B			BIT1	/*  Rx Descriptor Unavailable */
-#define	IMR_ROK_8723B			BIT0	/*  Receive DMA OK */
-
-/*  IMR DW1(0x00B4-00B7) Bit 0-31 */
-#define	IMR_BCNDMAINT7_8723B		BIT27	/*  Beacon DMA Interrupt 7 */
-#define	IMR_BCNDMAINT6_8723B		BIT26	/*  Beacon DMA Interrupt 6 */
-#define	IMR_BCNDMAINT5_8723B		BIT25	/*  Beacon DMA Interrupt 5 */
-#define	IMR_BCNDMAINT4_8723B		BIT24	/*  Beacon DMA Interrupt 4 */
-#define	IMR_BCNDMAINT3_8723B		BIT23	/*  Beacon DMA Interrupt 3 */
-#define	IMR_BCNDMAINT2_8723B		BIT22	/*  Beacon DMA Interrupt 2 */
-#define	IMR_BCNDMAINT1_8723B		BIT21	/*  Beacon DMA Interrupt 1 */
-#define	IMR_BCNDOK7_8723B		BIT20	/*  Beacon Queue DMA OK Interrupt 7 */
-#define	IMR_BCNDOK6_8723B		BIT19	/*  Beacon Queue DMA OK Interrupt 6 */
-#define	IMR_BCNDOK5_8723B		BIT18	/*  Beacon Queue DMA OK Interrupt 5 */
-#define	IMR_BCNDOK4_8723B		BIT17	/*  Beacon Queue DMA OK Interrupt 4 */
-#define	IMR_BCNDOK3_8723B		BIT16	/*  Beacon Queue DMA OK Interrupt 3 */
-#define	IMR_BCNDOK2_8723B		BIT15	/*  Beacon Queue DMA OK Interrupt 2 */
-#define	IMR_BCNDOK1_8723B		BIT14	/*  Beacon Queue DMA OK Interrupt 1 */
-#define	IMR_ATIMEND_E_8723B		BIT13	/*  ATIM Window End Extension for Win7 */
-#define	IMR_TXERR_8723B			BIT11	/*  Tx Error Flag Interrupt Status, write 1 clear. */
-#define	IMR_RXERR_8723B			BIT10	/*  Rx Error Flag INT Status, Write 1 clear */
-#define	IMR_TXFOVW_8723B		BIT9	/*  Transmit FIFO Overflow */
-#define	IMR_RXFOVW_8723B		BIT8	/*  Receive FIFO Overflow */
-
-/* 2 ACMHWCTRL 0x05C0 */
-#define	ACMHW_HWEN_8723B		BIT(0)
-#define	ACMHW_VOQEN_8723B		BIT(1)
-#define	ACMHW_VIQEN_8723B		BIT(2)
-#define	ACMHW_BEQEN_8723B		BIT(3)
-#define	ACMHW_VOQSTATUS_8723B		BIT(5)
-#define	ACMHW_VIQSTATUS_8723B		BIT(6)
-#define	ACMHW_BEQSTATUS_8723B		BIT(7)
-
-/*        8195 (RCR) Receive Configuration Register	(Offset 0x608, 32 bits) */
-#define	RCR_TCPOFLD_EN			BIT25	/*  Enable TCP checksum offload */
-
 #endif /*  #ifndef __INC_HAL8723BREG_H */

index e30071935d27..b81252d374ef 100644
@@ -49,8 +49,6 @@
 /*---------------------------------------------*/
    /*  define the base address of each block */
 #define PWR_BASEADDR_MAC		0x00
-#define PWR_BASEADDR_USB		0x01
-#define PWR_BASEADDR_PCIE		0x02
 #define PWR_BASEADDR_SDIO		0x03
 
 /*---------------------------------------------*/

@@ -64,21 +62,12 @@
 /*---------------------------------------------*/
 /* 3 The value of fab_msk: 4 bits */
 /*---------------------------------------------*/
-#define	PWR_FAB_TSMC_MSK		BIT(0)
-#define	PWR_FAB_UMC_MSK			BIT(1)
 #define	PWR_FAB_ALL_MSK			(BIT(0)|BIT(1)|BIT(2)|BIT(3))
 
 /*---------------------------------------------*/
 /* 3 The value of cut_msk: 8 bits */
 /*---------------------------------------------*/
 #define	PWR_CUT_TESTCHIP_MSK	BIT(0)
-#define	PWR_CUT_A_MSK			BIT(1)
-#define	PWR_CUT_B_MSK			BIT(2)
-#define	PWR_CUT_C_MSK			BIT(3)
-#define	PWR_CUT_D_MSK			BIT(4)
-#define	PWR_CUT_E_MSK			BIT(5)
-#define	PWR_CUT_F_MSK			BIT(6)
-#define	PWR_CUT_G_MSK			BIT(7)
 #define	PWR_CUT_ALL_MSK			0xFF
 
 

index f939d267b0c7..e103c4a15d1a 100644
@@ -39,11 +39,6 @@
 
 /* ifdef UNDER_MPTEST */
 #define	WIFI_MP_STATE							0x00010000
-#define	WIFI_MP_CTX_BACKGROUND				0x00020000	/*  in continuous tx background */
-#define	WIFI_MP_CTX_ST						0x00040000	/*  in continuous tx with single-tone */
-#define	WIFI_MP_CTX_BACKGROUND_PENDING	0x00080000	/*  pending in continuous tx background due to out of skb */
-#define	WIFI_MP_CTX_CCK_HW					0x00100000	/*  in continuous tx */
-#define	WIFI_MP_CTX_CCK_CS					0x00200000	/*  in continuous tx with carrier suppression */
 /* endif */
 
 /* define _FW_UNDER_CMD		WIFI_UNDER_CMD */

@@ -75,8 +70,6 @@ enum {
 	GHZ_MAX,
 };
 
-#define rtw_band_valid(band) ((band) >= GHZ24_50 && (band) < GHZ_MAX)
-
 /*
 
 there are several "locks" in mlme_priv,

@@ -252,11 +245,6 @@ struct mlme_priv {
 	unsigned long	timeBcnInfoChkStart;
 };
 
-#define rtw_mlme_set_auto_scan_int(adapter, ms) \
-	do { \
-		adapter->mlmepriv.auto_scan_int_ms = ms; \
-	while (0)
-
 void rtw_mlme_reset_auto_scan_int(struct adapter *adapter);
 
 struct hostapd_priv {

@@ -400,20 +388,6 @@ int is_same_network(struct wlan_bssid_ex *src, struct wlan_bssid_ex *dst, u8 fea
 
 #define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags)
 #define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags)
-#define rtw_clr_roam_flags(adapter, flags) \
-	do { \
-		((adapter)->mlmepriv.roam_flags &= ~flags); \
-	} while (0)
-
-#define rtw_set_roam_flags(adapter, flags) \
-	do { \
-		((adapter)->mlmepriv.roam_flags |= flags); \
-	} while (0)
-
-#define rtw_assign_roam_flags(adapter, flags) \
-	do { \
-		((adapter)->mlmepriv.roam_flags = flags); \
-	} while (0)
 
 void _rtw_roaming(struct adapter *adapter, struct wlan_network *tgt_network);
 void rtw_roaming(struct adapter *adapter, struct wlan_network *tgt_network);