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en7523 clk changes for pinctrl support

PATCH Superseded Lorenzo Bianconi 2 participants 5 messages Jul 9, 2024 – Jul 23, 2024 Common clk

v1 of 2 Superseded Latest is v2 →

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Lorenzo Bianconi

author
#0 lore raw

cover en7523 clk changes for pinctrl support

Reduce EN7581 clock driver IO region since this is shared with the upcoming EN7581 pinctrl driver. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Fix fixed rate estimation for emi, npu and crypto fixed clocks.

Lorenzo Bianconi (2):
clk: en7523: fix estimation of fixed rate for EN7581
clk: en7523: fix scuclk io region for upcoming pinctrl

 drivers/clk/clk-en7523.c | 136 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 128 insertions(+), 8 deletions(-)
Signature · 1 line
2.45.2
author
#1 lore raw

PATCH 1/2 clk: en7523: fix estimation of fixed rate for EN7581

Introduce fixed_rate in en_clk_soc_data struct in order to define per-SoC fixed-rate clock parameters and fix wrong parameters for emi, npu and crypto EN7581 clocks

Fixes 66bc47326ce2 ("clk: en7523: Add EN7581 support")
Signed-off-by Lorenzo Bianconi <[email protected]>
---
 drivers/clk/clk-en7523.c | 129 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 121 insertions(+), 8 deletions(-)
drivers/clk/clk-en7523.c +121 -8
index 22fbea61c3dc..b20e56337a6b 100644
@@ -31,6 +31,7 @@
 #define   REG_RESET_CONTROL_PCIE1	BIT(27)
 #define   REG_RESET_CONTROL_PCIE2	BIT(26)
 /* EN7581 */
+#define REG_CRYPTO_CLKSRC2		0x20c
 #define REG_PCIE0_MEM			0x00
 #define REG_PCIE0_MEM_MASK		0x04
 #define REG_PCIE1_MEM			0x08

@@ -78,6 +79,10 @@ struct en_rst_data {
 };
 
 struct en_clk_soc_data {
+	struct {
+		const struct en_clk_desc *desc;
+		u16 size;
+	} fixed_rate;
 	const struct clk_ops pcie_ops;
 	struct {
 		const u16 *bank_ofs;

@@ -92,6 +97,10 @@ static const u32 emi_base[] = { 333000000, 400000000 };
 static const u32 bus_base[] = { 500000000, 540000000 };
 static const u32 slic_base[] = { 100000000, 3125000 };
 static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
+/* EN7581 */
+static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
+static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
+static const u32 crypto_base[] = { 540000000, 480000000 };
 
 static const struct en_clk_desc en7523_base_clks[] = {
 	{

@@ -189,6 +198,102 @@ static const struct en_clk_desc en7523_base_clks[] = {
 	}
 };
 
+static const struct en_clk_desc en7581_base_clks[] = {
+	{
+		.id = EN7523_CLK_GSW,
+		.name = "gsw",
+
+		.base_reg = REG_GSW_CLK_DIV_SEL,
+		.base_bits = 1,
+		.base_shift = 8,
+		.base_values = gsw_base,
+		.n_base_values = ARRAY_SIZE(gsw_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_EMI,
+		.name = "emi",
+
+		.base_reg = REG_EMI_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = emi7581_base,
+		.n_base_values = ARRAY_SIZE(emi7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_BUS,
+		.name = "bus",
+
+		.base_reg = REG_BUS_CLK_DIV_SEL,
+		.base_bits = 1,
+		.base_shift = 8,
+		.base_values = bus_base,
+		.n_base_values = ARRAY_SIZE(bus_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_SLIC,
+		.name = "slic",
+
+		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = slic_base,
+		.n_base_values = ARRAY_SIZE(slic_base),
+
+		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_bits = 5,
+		.div_shift = 24,
+		.div_val0 = 20,
+		.div_step = 2,
+	}, {
+		.id = EN7523_CLK_SPI,
+		.name = "spi",
+
+		.base_reg = REG_SPI_CLK_DIV_SEL,
+
+		.base_value = 400000000,
+
+		.div_bits = 5,
+		.div_shift = 8,
+		.div_val0 = 40,
+		.div_step = 2,
+	}, {
+		.id = EN7523_CLK_NPU,
+		.name = "npu",
+
+		.base_reg = REG_NPU_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = npu7581_base,
+		.n_base_values = ARRAY_SIZE(npu7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_CRYPTO,
+		.name = "crypto",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = crypto_base,
+		.n_base_values = ARRAY_SIZE(crypto_base),
+	}
+};
+
 static const u16 en7581_rst_ofs[] = {
 	REG_RST_CTRL2,
 	REG_RST_CTRL1,

@@ -252,9 +357,9 @@ static const u16 en7581_rst_map[] = {
 	[EN7581_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
 };
 
-static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
+static unsigned int en7523_get_base_rate(const struct en_clk_desc *desc,
+					 void __iomem *base)
 {
-	const struct en_clk_desc *desc = &en7523_base_clks[i];
 	u32 val;
 
 	if (!desc->base_bits)

@@ -270,9 +375,8 @@ static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
 	return desc->base_values[val];
 }
 
-static u32 en7523_get_div(void __iomem *base, int i)
+static u32 en7523_get_div(const struct en_clk_desc *desc, void __iomem *base)
 {
-	const struct en_clk_desc *desc = &en7523_base_clks[i];
 	u32 reg, val;
 
 	if (!desc->div_bits)

@@ -441,15 +545,16 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
 				   void __iomem *base, void __iomem *np_base)
 {
+	const struct en_clk_soc_data *soc_data = device_get_match_data(dev);
 	struct clk_hw *hw;
 	u32 rate;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
-		const struct en_clk_desc *desc = &en7523_base_clks[i];
+	for (i = 0; i < soc_data->fixed_rate.size; i++) {
+		const struct en_clk_desc *desc = &soc_data->fixed_rate.desc[i];
 
-		rate = en7523_get_base_rate(base, i);
-		rate /= en7523_get_div(base, i);
+		rate = en7523_get_base_rate(desc, base);
+		rate /= en7523_get_div(desc, base);
 
 		hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
 		if (IS_ERR(hw)) {

@@ -603,6 +708,10 @@ static int en7523_clk_probe(struct platform_device *pdev)
 }
 
 static const struct en_clk_soc_data en7523_data = {
+	.fixed_rate = {
+		.desc = en7523_base_clks,
+		.size = ARRAY_SIZE(en7523_base_clks),
+	},
 	.pcie_ops = {
 		.is_enabled = en7523_pci_is_enabled,
 		.prepare = en7523_pci_prepare,

@@ -611,6 +720,10 @@ static const struct en_clk_soc_data en7523_data = {
 };
 
 static const struct en_clk_soc_data en7581_data = {
+	.fixed_rate = {
+		.desc = en7581_base_clks,
+		.size = ARRAY_SIZE(en7581_base_clks),
+	},
 	.pcie_ops = {
 		.is_enabled = en7581_pci_is_enabled,
 		.enable = en7581_pci_enable,
Signature · 1 line
2.45.2
author
#2 lore raw

PATCH 2/2 clk: en7523: fix scuclk io region for upcoming pinctrl

In reply to Lorenzo Bianconi

EN7581 clock driver shares the IO region with the upcoming pinctrl driver for Airoha EN7581 SoC. Fix it by reducing the clk mapped region to only used registers in order to not overlap with pinctrl one. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet.

Signed-off-by Lorenzo Bianconi <[email protected]>
---
 drivers/clk/clk-en7523.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)
drivers/clk/clk-en7523.c +15 -8
index b20e56337a6b..d9ecbb6bf55a 100644
@@ -31,7 +31,14 @@
 #define   REG_RESET_CONTROL_PCIE1	BIT(27)
 #define   REG_RESET_CONTROL_PCIE2	BIT(26)
 /* EN7581 */
-#define REG_CRYPTO_CLKSRC2		0x20c
+#define REG_GSW_CLK_DIV_SEL2		0x00
+#define REG_EMI_CLK_DIV_SEL2		0x04
+#define REG_BUS_CLK_DIV_SEL2		0x08
+#define REG_SPI_CLK_DIV_SEL2		0x10
+#define REG_SPI_CLK_FREQ_SEL2		0x14
+#define REG_NPU_CLK_DIV_SEL2		0x48
+#define REG_CRYPTO_CLKSRC2		0x58
+
 #define REG_PCIE0_MEM			0x00
 #define REG_PCIE0_MEM_MASK		0x04
 #define REG_PCIE1_MEM			0x08

@@ -203,7 +210,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
 		.id = EN7523_CLK_GSW,
 		.name = "gsw",
 
-		.base_reg = REG_GSW_CLK_DIV_SEL,
+		.base_reg = REG_GSW_CLK_DIV_SEL2,
 		.base_bits = 1,
 		.base_shift = 8,
 		.base_values = gsw_base,

@@ -217,7 +224,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
 		.id = EN7523_CLK_EMI,
 		.name = "emi",
 
-		.base_reg = REG_EMI_CLK_DIV_SEL,
+		.base_reg = REG_EMI_CLK_DIV_SEL2,
 		.base_bits = 2,
 		.base_shift = 8,
 		.base_values = emi7581_base,

@@ -231,7 +238,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
 		.id = EN7523_CLK_BUS,
 		.name = "bus",
 
-		.base_reg = REG_BUS_CLK_DIV_SEL,
+		.base_reg = REG_BUS_CLK_DIV_SEL2,
 		.base_bits = 1,
 		.base_shift = 8,
 		.base_values = bus_base,

@@ -245,13 +252,13 @@ static const struct en_clk_desc en7581_base_clks[] = {
 		.id = EN7523_CLK_SLIC,
 		.name = "slic",
 
-		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_reg = REG_SPI_CLK_FREQ_SEL2,
 		.base_bits = 1,
 		.base_shift = 0,
 		.base_values = slic_base,
 		.n_base_values = ARRAY_SIZE(slic_base),
 
-		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_reg = REG_SPI_CLK_DIV_SEL2,
 		.div_bits = 5,
 		.div_shift = 24,
 		.div_val0 = 20,

@@ -260,7 +267,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
 		.id = EN7523_CLK_SPI,
 		.name = "spi",
 
-		.base_reg = REG_SPI_CLK_DIV_SEL,
+		.base_reg = REG_SPI_CLK_DIV_SEL2,
 
 		.base_value = 400000000,
 

@@ -272,7 +279,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
 		.id = EN7523_CLK_NPU,
 		.name = "npu",
 
-		.base_reg = REG_NPU_CLK_DIV_SEL,
+		.base_reg = REG_NPU_CLK_DIV_SEL2,
 		.base_bits = 2,
 		.base_shift = 8,
 		.base_values = npu7581_base,
Signature · 1 line
2.45.2
#3 lore raw

Re: [PATCH 2/2] clk: en7523: fix scuclk io region for upcoming pinctrl

Il 09/07/24 09:48, Lorenzo Bianconi ha scritto:

Quoted 32 lines

EN7581 clock driver shares the IO region with the upcoming pinctrl driver for Airoha EN7581 SoC. Fix it by reducing the clk mapped region to only used registers in order to not overlap with pinctrl one. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet.

Signed-off-by Lorenzo Bianconi <[email protected]>
---
  drivers/clk/clk-en7523.c | 23 +++++++++++++++--------
  1 file changed, 15 insertions(+), 8 deletions(-)
drivers/clk/clk-en7523.c +8 -1
index b20e56337a6b..d9ecbb6bf55a 100644
@@ -31,7 +31,14 @@
  #define   REG_RESET_CONTROL_PCIE1	BIT(27)
  #define   REG_RESET_CONTROL_PCIE2	BIT(26)
  /* EN7581 */
-#define REG_CRYPTO_CLKSRC2		0x20c
+#define REG_GSW_CLK_DIV_SEL2		0x00
+#define REG_EMI_CLK_DIV_SEL2		0x04
+#define REG_BUS_CLK_DIV_SEL2		0x08
+#define REG_SPI_CLK_DIV_SEL2		0x10
+#define REG_SPI_CLK_FREQ_SEL2		0x14
+#define REG_NPU_CLK_DIV_SEL2		0x48
+#define REG_CRYPTO_CLKSRC2		0x58
+
  #define REG_PCIE0_MEM			0x00
  #define REG_PCIE0_MEM_MASK		0x04
  #define REG_PCIE1_MEM			0x08

drivers/clk/clk-en7523.c static const struct en_clk_desc en7581_base_clks[] = { · line 213

Quoted 5 lines
drivers/clk/clk-en7523.c +1 -1
@@ -203,7 +210,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_GSW,
  		.name = "gsw",
 
-		.base_reg = REG_GSW_CLK_DIV_SEL,
+		.base_reg = REG_GSW_CLK_DIV_SEL2,

This is practically just commit noise :-)

You are adding the en7581_base_clks[] in patch [1/2] with the wrong base register, then fixing it here ... and that's wrong.

Please squash the two patches.

Cheers,
Angelo

Quoted 55 lines
drivers/clk/clk-en7523.c +6 -6
  		.base_bits = 1,
  		.base_shift = 8,
  		.base_values = gsw_base,

@@ -217,7 +224,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_EMI,
  		.name = "emi",
 
-		.base_reg = REG_EMI_CLK_DIV_SEL,
+		.base_reg = REG_EMI_CLK_DIV_SEL2,
  		.base_bits = 2,
  		.base_shift = 8,
  		.base_values = emi7581_base,

@@ -231,7 +238,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_BUS,
  		.name = "bus",
 
-		.base_reg = REG_BUS_CLK_DIV_SEL,
+		.base_reg = REG_BUS_CLK_DIV_SEL2,
  		.base_bits = 1,
  		.base_shift = 8,
  		.base_values = bus_base,

@@ -245,13 +252,13 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_SLIC,
  		.name = "slic",
 
-		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_reg = REG_SPI_CLK_FREQ_SEL2,
  		.base_bits = 1,
  		.base_shift = 0,
  		.base_values = slic_base,
  		.n_base_values = ARRAY_SIZE(slic_base),
 
-		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_reg = REG_SPI_CLK_DIV_SEL2,
  		.div_bits = 5,
  		.div_shift = 24,
  		.div_val0 = 20,

@@ -260,7 +267,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_SPI,
  		.name = "spi",
 
-		.base_reg = REG_SPI_CLK_DIV_SEL,
+		.base_reg = REG_SPI_CLK_DIV_SEL2,
 
  		.base_value = 400000000,
 

@@ -272,7 +279,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_NPU,
  		.name = "npu",
 
-		.base_reg = REG_NPU_CLK_DIV_SEL,
+		.base_reg = REG_NPU_CLK_DIV_SEL2,
  		.base_bits = 2,
  		.base_shift = 8,
  		.base_values = npu7581_base,
author
#4 lore raw

Re: [PATCH 2/2] clk: en7523: fix scuclk io region for upcoming pinctrl

Quoted 40 lines

Il 09/07/24 09:48, Lorenzo Bianconi ha scritto:

Quoted 32 lines

EN7581 clock driver shares the IO region with the upcoming pinctrl driver for Airoha EN7581 SoC. Fix it by reducing the clk mapped region to only used registers in order to not overlap with pinctrl one. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet.

Signed-off-by Lorenzo Bianconi <[email protected]>
---
  drivers/clk/clk-en7523.c | 23 +++++++++++++++--------
  1 file changed, 15 insertions(+), 8 deletions(-)
drivers/clk/clk-en7523.c +8 -1
index b20e56337a6b..d9ecbb6bf55a 100644
@@ -31,7 +31,14 @@
  #define   REG_RESET_CONTROL_PCIE1	BIT(27)
  #define   REG_RESET_CONTROL_PCIE2	BIT(26)
  /* EN7581 */
-#define REG_CRYPTO_CLKSRC2		0x20c
+#define REG_GSW_CLK_DIV_SEL2		0x00
+#define REG_EMI_CLK_DIV_SEL2		0x04
+#define REG_BUS_CLK_DIV_SEL2		0x08
+#define REG_SPI_CLK_DIV_SEL2		0x10
+#define REG_SPI_CLK_FREQ_SEL2		0x14
+#define REG_NPU_CLK_DIV_SEL2		0x48
+#define REG_CRYPTO_CLKSRC2		0x58
+
  #define REG_PCIE0_MEM			0x00
  #define REG_PCIE0_MEM_MASK		0x04
  #define REG_PCIE1_MEM			0x08

drivers/clk/clk-en7523.c static const struct en_clk_desc en7581_base_clks[] = { · line 212

Quoted 4 lines
drivers/clk/clk-en7523.c +1 -1
@@ -203,7 +210,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_GSW,
  		.name = "gsw",
-		.base_reg = REG_GSW_CLK_DIV_SEL,
+		.base_reg = REG_GSW_CLK_DIV_SEL2,

This is practically just commit noise :-)

Quoted 4 lines

You are adding the en7581_base_clks[] in patch [1/2] with the wrong base register, then fixing it here ... and that's wrong.

Please squash the two patches.

ack, I will do.

Regards,
Lorenzo

Quoted 52 lines

Cheers,
Angelo

Quoted 47 lines
drivers/clk/clk-en7523.c +6 -6
  		.base_bits = 1,
  		.base_shift = 8,
  		.base_values = gsw_base,

@@ -217,7 +224,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_EMI,
  		.name = "emi",
-		.base_reg = REG_EMI_CLK_DIV_SEL,
+		.base_reg = REG_EMI_CLK_DIV_SEL2,
  		.base_bits = 2,
  		.base_shift = 8,
  		.base_values = emi7581_base,

@@ -231,7 +238,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_BUS,
  		.name = "bus",
-		.base_reg = REG_BUS_CLK_DIV_SEL,
+		.base_reg = REG_BUS_CLK_DIV_SEL2,
  		.base_bits = 1,
  		.base_shift = 8,
  		.base_values = bus_base,

@@ -245,13 +252,13 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_SLIC,
  		.name = "slic",
-		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_reg = REG_SPI_CLK_FREQ_SEL2,
  		.base_bits = 1,
  		.base_shift = 0,
  		.base_values = slic_base,
  		.n_base_values = ARRAY_SIZE(slic_base),
-		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_reg = REG_SPI_CLK_DIV_SEL2,
  		.div_bits = 5,
  		.div_shift = 24,
  		.div_val0 = 20,

@@ -260,7 +267,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_SPI,
  		.name = "spi",
-		.base_reg = REG_SPI_CLK_DIV_SEL,
+		.base_reg = REG_SPI_CLK_DIV_SEL2,
  		.base_value = 400000000,

@@ -272,7 +279,7 @@ static const struct en_clk_desc en7581_base_clks[] = {
  		.id = EN7523_CLK_NPU,
  		.name = "npu",
-		.base_reg = REG_NPU_CLK_DIV_SEL,
+		.base_reg = REG_NPU_CLK_DIV_SEL2,
  		.base_bits = 2,
  		.base_shift = 8,
  		.base_values = npu7581_base,