Add pinctrl support to EN7581 SoC

PATCH Superseded Lorenzo Bianconi 7 participants 19 messages Aug 11, 2024 – Aug 18, 2024

Subsystems (6)

Device tree bindings GPIO Arm MediaTek Pin control +2 more subsystems

lore

Share & tools

lore

Lorenzo Bianconi

author maintainer

2024-08-11 16:12 UTC #0 lore raw

cover Add pinctrl support to EN7581 SoC

Introduce pinctrl driver for EN7581 SoC. Current EN7581 pinctrl driver supports the following functionalities:
- pin multiplexing
- pin pull-up, pull-down, open-drain, current strength, {input,output}_enable, output_{low,high}
- gpio controller
- irq controller

Lorenzo Bianconi (2):
dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller
pinctrl: airoha: Add support for EN7581 SoC

 .../pinctrl/airoha,en7581-pinctrl.yaml        |  467 +++
 MAINTAINERS                                   |    7 +
 drivers/pinctrl/mediatek/Kconfig              |   14 +-
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-airoha.c     | 2983 +++++++++++++++++
 5 files changed, 3471 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-airoha.c

Signature · 1 line

2.46.0

Lorenzo Bianconi

author maintainer

2024-08-11 16:12 UTC #1 lore raw

PATCH 1/2 dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Introduce device-tree binding documentation for Airoha EN7581 pinctrl controller.

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 .../pinctrl/airoha,en7581-pinctrl.yaml        | 467 ++++++++++++++++++
 1 file changed, 467 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +467 -0

new file mode 100644
index 000000000000..b1f980613864
@@ -0,0 +1,467 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 Pin Controller
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+
+description:
+  The Airoha's EN7581 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    enum:
+      - airoha,en7581-pinctrl
+
+  reg:
+    items:
+      - description: IOMUX base address
+      - description: LED IOMUX base address
+      - description: GPIO flash mode base address
+      - description: GPIO flash mode extended base address
+      - description: IO pin configuration base address
+      - description: PCIE reset open-drain base address
+      - description: GPIO bank0 data register base address
+      - description: GPIO bank1 data register base address
+      - description: GPIO bank0 first control register base address
+      - description: GPIO bank0 second control register base address
+      - description: GPIO bank1 first control register base address
+      - description: GPIO bank1 second control register base address
+      - description: GPIO bank0 output enable register base address
+      - description: GPIO bank1 output enable register base address
+      - description: GPIO bank0 irq status register base address
+      - description: GPIO bank1 irq status register base address
+      - description: GPIO bank0 irq level first control register base address
+      - description: GPIO bank0 irq level second control register base address
+      - description: GPIO bank1 irq level first control register base address
+      - description: GPIO bank1 irq level second control register base address
+      - description: GPIO bank0 irq edge first control register base address
+      - description: GPIO bank0 irq edge second control register base address
+      - description: GPIO bank1 irq edge first control register base address
+      - description: GPIO bank1 irq edge second control register base address
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+    description:
+      Number of cells in GPIO specifier. Since the generic GPIO binding is
+      used, the amount of cells must be specified as 2. See the below mentioned
+      gpio binding representation for description of particular cells.
+
+  gpio-ranges:
+    maxItems: 1
+    description:
+      GPIO valid number range.
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 2
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - "#gpio-cells"
+
+patternProperties:
+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    patternProperties:
+      '^.*mux.*$':
+        type: object
+        additionalProperties: false
+        description: |
+          pinmux configuration nodes.
+
+        $ref: /schemas/pinctrl/pinmux-node.yaml
+        properties:
+          function:
+            description:
+              A string containing the name of the function to mux to the group.
+            enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
+                   pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0,
+                   phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
+                   phy3_led1, phy4_led1]
+          groups:
+            description:
+              An array of strings. Each string contains the name of a group.
+        required:
+          - function
+          - groups
+
+        allOf:
+          - if:
+              properties:
+                function:
+                  const: pon
+            then:
+              properties:
+                groups:
+                  enum: [pon]
+          - if:
+              properties:
+                function:
+                  const: tod_1pps
+            then:
+              properties:
+                groups:
+                  enum: [pon_tod_1pps, gsw_tod_1pps]
+          - if:
+              properties:
+                function:
+                  const: sipo
+            then:
+              properties:
+                groups:
+                  enum: [sipo, sipo_rclk]
+          - if:
+              properties:
+                function:
+                  const: mdio
+            then:
+              properties:
+                groups:
+                  enum: [mdio]
+          - if:
+              properties:
+                function:
+                  const: uart
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, uart4,
+                           uart5]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [i2c1]
+          - if:
+              properties:
+                function:
+                  const: jtag
+            then:
+              properties:
+                groups:
+                  enum: [jtag_udi, jtag_dfd]
+          - if:
+              properties:
+                function:
+                  const: pcm
+            then:
+              properties:
+                groups:
+                  enum: [pcm1, pcm2]
+          - if:
+              properties:
+                function:
+                  const: spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [spi_quad, spi_cs1]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: pcm_spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
+                           pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3,
+                           pcm_spi_cs4]
+                  maxItems: 7
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [i2s]
+          - if:
+              properties:
+                function:
+                  const: emmc
+            then:
+              properties:
+                groups:
+                  enum: [emmc]
+          - if:
+              properties:
+                function:
+                  const: pnand
+            then:
+              properties:
+                groups:
+                  enum: [pnand]
+          - if:
+              properties:
+                function:
+                  const: pcie_reset
+            then:
+              properties:
+                groups:
+                  enum: [pcie_reset0, pcie_reset1, pcie_reset2]
+          - if:
+              properties:
+                function:
+                  const: pwm
+            then:
+              properties:
+                groups:
+                  enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
+                         gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
+                         gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                         gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
+                         gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
+                         gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
+                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
+          - if:
+              properties:
+                function:
+                  const: phy1_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy2_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy3_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy4_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy1_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy2_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy3_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy4_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+
+      '^.*conf.*$':
+        type: object
+        additionalProperties: false
+        description:
+          pinconf configuration nodes.
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+
+        properties:
+          pins:
+            description:
+              An array of strings. Each string contains the name of a pin.
+            items:
+              enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk,
+                     spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4,
+                     gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,
+                     gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                     gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
+                     gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33,
+                     gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40,
+                     gpio41, gpio42, gpio43, gpio44, gpio45, gpio46,
+                     pcie_reset0, pcie_reset1, pcie_reset2]
+            maxItems: 58
+
+          bias-disable: true
+
+          bias-pull-up: true
+
+          bias-pull-down: true
+
+          input-enable: true
+
+          output-enable: true
+
+          output-low: true
+
+          output-high: true
+
+          drive-open-drain: true
+
+          drive-strength:
+            enum: [2, 4, 6, 8]
+
+        required:
+          - pins
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pio: pinctrl@1fa20214 {
+        compatible = "airoha,en7581-pinctrl";
+        reg = <0x0 0x1fa20214 0x0 0x30>,
+              <0x0 0x1fa2027c 0x0 0x8>,
+              <0x0 0x1fbf0234 0x0 0x4>,
+              <0x0 0x1fbf0268 0x0 0x4>,
+              <0x0 0x1fa2001c 0x0 0x50>,
+              <0x0 0x1fa2018c 0x0 0x4>,
+              <0x0 0x1fbf0204 0x0 0x4>,
+              <0x0 0x1fbf0270 0x0 0x4>,
+              <0x0 0x1fbf0200 0x0 0x4>,
+              <0x0 0x1fbf0220 0x0 0x4>,
+              <0x0 0x1fbf0260 0x0 0x4>,
+              <0x0 0x1fbf0264 0x0 0x4>,
+              <0x0 0x1fbf0214 0x0 0x4>,
+              <0x0 0x1fbf0278 0x0 0x4>,
+              <0x0 0x1fbf0208 0x0 0x4>,
+              <0x0 0x1fbf027c 0x0 0x4>,
+              <0x0 0x1fbf0210 0x0 0x4>,
+              <0x0 0x1fbf028c 0x0 0x4>,
+              <0x0 0x1fbf0290 0x0 0x4>,
+              <0x0 0x1fbf0294 0x0 0x4>,
+              <0x0 0x1fbf020c 0x0 0x4>,
+              <0x0 0x1fbf0280 0x0 0x4>,
+              <0x0 0x1fbf0284 0x0 0x4>,
+              <0x0 0x1fbf0288 0x0 0x4>;
+
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 13 47>;
+
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+        pcie1-rst-pins {
+          conf {
+            pins = "pcie_reset1";
+            drive-open-drain = <1>;
+          };
+        };
+
+        pwm-pins {
+          mux {
+            function = "pwm";
+            groups = "gpio18";
+          };
+        };
+
+        spi-pins {
+          mux {
+            function = "spi";
+            groups = "spi_quad", "spi_cs1";
+          };
+        };
+
+        uuart2-pins {
+          mux {
+            function = "uart";
+            groups = "uart2", "uart2_cts_rts";
+          };
+        };
+
+        uar5-pins {
+          mux {
+            function = "uart";
+            groups = "uart5";
+          };
+        };
+
+        mmc-pins {
+          mux {
+            function = "emmc";
+            groups = "emmc";
+          };
+        };
+
+        mdio-pins {
+          mux {
+            function = "mdio";
+            groups = "mdio";
+          };
+
+          conf {
+            pins = "gpio2";
+            output-enable;
+          };
+        };
+
+        gswp1-led0-pins {
+          mux {
+            function = "phy1_led0";
+            groups = "gpio33";
+          };
+        };
+
+        gswp2-led1-pins {
+          mux {
+            function = "phy2_led1";
+            groups = "gpio44";
+          };
+        };
+      };
+    };

Signature · 1 line

2.46.0

Krzysztof Kozlowski

2024-08-12 06:49 UTC #2 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 83 lines · Lorenzo Bianconi

Introduce device-tree binding documentation for Airoha EN7581 pinctrl controller.

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 .../pinctrl/airoha,en7581-pinctrl.yaml        | 467 ++++++++++++++++++
 1 file changed, 467 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +68 -0

new file mode 100644
index 000000000000..b1f980613864
@@ -0,0 +1,467 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 Pin Controller
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+
+description:
+  The Airoha's EN7581 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    enum:
+      - airoha,en7581-pinctrl
+
+  reg:
+    items:
+      - description: IOMUX base address
+      - description: LED IOMUX base address
+      - description: GPIO flash mode base address
+      - description: GPIO flash mode extended base address
+      - description: IO pin configuration base address
+      - description: PCIE reset open-drain base address
+      - description: GPIO bank0 data register base address
+      - description: GPIO bank1 data register base address
+      - description: GPIO bank0 first control register base address
+      - description: GPIO bank0 second control register base address
+      - description: GPIO bank1 first control register base address
+      - description: GPIO bank1 second control register base address
+      - description: GPIO bank0 output enable register base address
+      - description: GPIO bank1 output enable register base address
+      - description: GPIO bank0 irq status register base address
+      - description: GPIO bank1 irq status register base address
+      - description: GPIO bank0 irq level first control register base address
+      - description: GPIO bank0 irq level second control register base address
+      - description: GPIO bank1 irq level first control register base address
+      - description: GPIO bank1 irq level second control register base address
+      - description: GPIO bank0 irq edge first control register base address
+      - description: GPIO bank0 irq edge second control register base address
+      - description: GPIO bank1 irq edge first control register base address
+      - description: GPIO bank1 irq edge second control register base address
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+    description:
+      Number of cells in GPIO specifier. Since the generic GPIO binding is
+      used, the amount of cells must be specified as 2. See the below mentioned
+      gpio binding representation for description of particular cells.
+
+  gpio-ranges:
+    maxItems: 1
+    description:
+      GPIO valid number range.
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 2
+

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 78

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0
+allOf:
+  - $ref: pinctrl.yaml#
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - "#gpio-cells"
+
+patternProperties:

Keep it after properties: block.

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 87

Quoted 9 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +9 -0

+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    patternProperties:
+      '^.*mux.*$':
+        type: object
+        additionalProperties: false
+        description: |

Do not need '|' unless you need to preserve formatting.

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 99

Quoted 12 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +12 -0

+          pinmux configuration nodes.
+
+        $ref: /schemas/pinctrl/pinmux-node.yaml
+        properties:
+          function:
+            description:
+              A string containing the name of the function to mux to the group.
+            enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
+                   pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0,
+                   phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
+                   phy3_led1, phy4_led1]
+          groups:

minItems: 1
maxItems: 32 (or whatever is sensible)

Quoted 218 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +218 -0

+            description:
+              An array of strings. Each string contains the name of a group.
+        required:
+          - function
+          - groups
+
+        allOf:
+          - if:
+              properties:
+                function:
+                  const: pon
+            then:
+              properties:
+                groups:
+                  enum: [pon]
+          - if:
+              properties:
+                function:
+                  const: tod_1pps
+            then:
+              properties:
+                groups:
+                  enum: [pon_tod_1pps, gsw_tod_1pps]
+          - if:
+              properties:
+                function:
+                  const: sipo
+            then:
+              properties:
+                groups:
+                  enum: [sipo, sipo_rclk]
+          - if:
+              properties:
+                function:
+                  const: mdio
+            then:
+              properties:
+                groups:
+                  enum: [mdio]
+          - if:
+              properties:
+                function:
+                  const: uart
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, uart4,
+                           uart5]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [i2c1]
+          - if:
+              properties:
+                function:
+                  const: jtag
+            then:
+              properties:
+                groups:
+                  enum: [jtag_udi, jtag_dfd]
+          - if:
+              properties:
+                function:
+                  const: pcm
+            then:
+              properties:
+                groups:
+                  enum: [pcm1, pcm2]
+          - if:
+              properties:
+                function:
+                  const: spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [spi_quad, spi_cs1]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: pcm_spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
+                           pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3,
+                           pcm_spi_cs4]
+                  maxItems: 7
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [i2s]
+          - if:
+              properties:
+                function:
+                  const: emmc
+            then:
+              properties:
+                groups:
+                  enum: [emmc]
+          - if:
+              properties:
+                function:
+                  const: pnand
+            then:
+              properties:
+                groups:
+                  enum: [pnand]
+          - if:
+              properties:
+                function:
+                  const: pcie_reset
+            then:
+              properties:
+                groups:
+                  enum: [pcie_reset0, pcie_reset1, pcie_reset2]
+          - if:
+              properties:
+                function:
+                  const: pwm
+            then:
+              properties:
+                groups:
+                  enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
+                         gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
+                         gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                         gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
+                         gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
+                         gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
+                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
+          - if:
+              properties:
+                function:
+                  const: phy1_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy2_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy3_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy4_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy1_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy2_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy3_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy4_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+
+      '^.*conf.*$':
+        type: object
+        additionalProperties: false
+        description:
+          pinconf configuration nodes.
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+
+        properties:
+          pins:
+            description:
+              An array of strings. Each string contains the name of a pin.

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 327

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0

+            items:
+              enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk,
+                     spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4,
+                     gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,
+                     gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                     gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
+                     gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33,
+                     gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40,
+                     gpio41, gpio42, gpio43, gpio44, gpio45, gpio46,
+                     pcie_reset0, pcie_reset1, pcie_reset2]

minItems

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +7 -0
+            maxItems: 58
+
+          bias-disable: true
+
+          bias-pull-up: true
+
+          bias-pull-down: true

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 344

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0
+
+          input-enable: true
+
+          output-enable: true
+
+          output-low: true
+
+          output-high: true
+
+          drive-open-drain: true

Drop blank lines between these.

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 346

Quoted 2 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +2 -0
+
+          drive-strength:

What are the units? Shouldn't this be drive-strength-microamp?

Quoted 32 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +32 -0

+            enum: [2, 4, 6, 8]
+
+        required:
+          - pins
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pio: pinctrl@1fa20214 {
+        compatible = "airoha,en7581-pinctrl";
+        reg = <0x0 0x1fa20214 0x0 0x30>,
+              <0x0 0x1fa2027c 0x0 0x8>,
+              <0x0 0x1fbf0234 0x0 0x4>,
+              <0x0 0x1fbf0268 0x0 0x4>,
+              <0x0 0x1fa2001c 0x0 0x50>,
+              <0x0 0x1fa2018c 0x0 0x4>,
+              <0x0 0x1fbf0204 0x0 0x4>,
+              <0x0 0x1fbf0270 0x0 0x4>,
+              <0x0 0x1fbf0200 0x0 0x4>,
+              <0x0 0x1fbf0220 0x0 0x4>,
+              <0x0 0x1fbf0260 0x0 0x4>,
+              <0x0 0x1fbf0264 0x0 0x4>,
+              <0x0 0x1fbf0214 0x0 0x4>,
+              <0x0 0x1fbf0278 0x0 0x4>,

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 388

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0

+              <0x0 0x1fbf0208 0x0 0x4>,
+              <0x0 0x1fbf027c 0x0 0x4>,
+              <0x0 0x1fbf0210 0x0 0x4>,
+              <0x0 0x1fbf028c 0x0 0x4>,
+              <0x0 0x1fbf0290 0x0 0x4>,
+              <0x0 0x1fbf0294 0x0 0x4>,
+              <0x0 0x1fbf020c 0x0 0x4>,
+              <0x0 0x1fbf0280 0x0 0x4>,
+              <0x0 0x1fbf0284 0x0 0x4>,
+              <0x0 0x1fbf0288 0x0 0x4>;

Why are you mapping individual registers? At least half of these are continuous.

Quoted 50 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +50 -0

+
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 13 47>;
+
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+        pcie1-rst-pins {
+          conf {
+            pins = "pcie_reset1";
+            drive-open-drain = <1>;
+          };
+        };
+
+        pwm-pins {
+          mux {
+            function = "pwm";
+            groups = "gpio18";
+          };
+        };
+
+        spi-pins {
+          mux {
+            function = "spi";
+            groups = "spi_quad", "spi_cs1";
+          };
+        };
+
+        uuart2-pins {
+          mux {
+            function = "uart";
+            groups = "uart2", "uart2_cts_rts";
+          };
+        };
+
+        uar5-pins {
+          mux {
+            function = "uart";
+            groups = "uart5";
+          };
+        };
+
+        mmc-pins {
+          mux {
+            function = "emmc";
+            groups = "emmc";
+          };

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 448

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0

+        };
+
+        mdio-pins {
+          mux {
+            function = "mdio";
+            groups = "mdio";
+          };
+
+          conf {
+            pins = "gpio2";

What is the point of having both groups and pins?

Quoted 5 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +5 -0
+            output-enable;
+          };
+        };
+
+        gswp1-led0-pins {

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 463

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0

+          mux {
+            function = "phy1_led0";
+            groups = "gpio33";
+          };
+        };
+
+        gswp2-led1-pins {
+          mux {
+            function = "phy2_led1";
+            groups = "gpio44";

That's not a group but pin name.

Best regards,
Krzysztof

Benjamin Larsson

2024-08-13 08:06 UTC #3 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 26 lines · Krzysztof Kozlowski

Quoted 16 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +16 -0

+      pio: pinctrl@1fa20214 {
+        compatible = "airoha,en7581-pinctrl";
+        reg = <0x0 0x1fa20214 0x0 0x30>,
+              <0x0 0x1fa2027c 0x0 0x8>,
+              <0x0 0x1fbf0234 0x0 0x4>,
+              <0x0 0x1fbf0268 0x0 0x4>,
+              <0x0 0x1fa2001c 0x0 0x50>,
+              <0x0 0x1fa2018c 0x0 0x4>,
+              <0x0 0x1fbf0204 0x0 0x4>,
+              <0x0 0x1fbf0270 0x0 0x4>,
+              <0x0 0x1fbf0200 0x0 0x4>,
+              <0x0 0x1fbf0220 0x0 0x4>,
+              <0x0 0x1fbf0260 0x0 0x4>,
+              <0x0 0x1fbf0264 0x0 0x4>,
+              <0x0 0x1fbf0214 0x0 0x4>,
+              <0x0 0x1fbf0278 0x0 0x4>,

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 388

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0

+              <0x0 0x1fbf0208 0x0 0x4>,
+              <0x0 0x1fbf027c 0x0 0x4>,
+              <0x0 0x1fbf0210 0x0 0x4>,
+              <0x0 0x1fbf028c 0x0 0x4>,
+              <0x0 0x1fbf0290 0x0 0x4>,
+              <0x0 0x1fbf0294 0x0 0x4>,
+              <0x0 0x1fbf020c 0x0 0x4>,
+              <0x0 0x1fbf0280 0x0 0x4>,
+              <0x0 0x1fbf0284 0x0 0x4>,
+              <0x0 0x1fbf0288 0x0 0x4>;

Quoted 2 lines

Why are you mapping individual registers? At least half of these are continuous.

Hi, this is by design because of the register placement in the gpio block and the fact that the pwm functionality is intermixed in there also. As example the following registers are all GPIOCTRL:

<0x0 0x1fbf0200 0x0 0x4>,
<0x0 0x1fbf0220 0x0 0x4>,
<0x0 0x1fbf0260 0x0 0x4>,
<0x0 0x1fbf0264 0x0 0x4>,

To simplify the driver code logic the complexity is moved to the dts because of that.

MvH

Benjamin Larsson

Rob Herring

maintainer

2024-08-16 22:52 UTC #4 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 34 lines · Benjamin Larsson

Quoted 26 lines · Krzysztof Kozlowski
Quoted 16 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +16 -0
+      pio: pinctrl@1fa20214 {
+        compatible = "airoha,en7581-pinctrl";
+        reg = <0x0 0x1fa20214 0x0 0x30>,
+              <0x0 0x1fa2027c 0x0 0x8>,
+              <0x0 0x1fbf0234 0x0 0x4>,
+              <0x0 0x1fbf0268 0x0 0x4>,
+              <0x0 0x1fa2001c 0x0 0x50>,
+              <0x0 0x1fa2018c 0x0 0x4>,
+              <0x0 0x1fbf0204 0x0 0x4>,
+              <0x0 0x1fbf0270 0x0 0x4>,
+              <0x0 0x1fbf0200 0x0 0x4>,
+              <0x0 0x1fbf0220 0x0 0x4>,
+              <0x0 0x1fbf0260 0x0 0x4>,
+              <0x0 0x1fbf0264 0x0 0x4>,
+              <0x0 0x1fbf0214 0x0 0x4>,
+              <0x0 0x1fbf0278 0x0 0x4>,
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 388
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0
+              <0x0 0x1fbf0208 0x0 0x4>,
+              <0x0 0x1fbf027c 0x0 0x4>,
+              <0x0 0x1fbf0210 0x0 0x4>,
+              <0x0 0x1fbf028c 0x0 0x4>,
+              <0x0 0x1fbf0290 0x0 0x4>,
+              <0x0 0x1fbf0294 0x0 0x4>,
+              <0x0 0x1fbf020c 0x0 0x4>,
+              <0x0 0x1fbf0280 0x0 0x4>,
+              <0x0 0x1fbf0284 0x0 0x4>,
+              <0x0 0x1fbf0288 0x0 0x4>;
Quoted 2 lines
Why are you mapping individual registers? At least half of these are continuous.
Hi, this is by design because of the register placement in the gpio block and the fact that the pwm functionality is intermixed in there also. As example the following registers are all GPIOCTRL:

Quoted 7 lines

<0x0 0x1fbf0200 0x0 0x4>,
<0x0 0x1fbf0220 0x0 0x4>,
<0x0 0x1fbf0260 0x0 0x4>,
<0x0 0x1fbf0264 0x0 0x4>,
To simplify the driver code logic the complexity is moved to the dts because of that.

DT to OS is an ABI. Don't put the complexity there. The driver is easy to change.

Lot's of h/w blocks are just bit soup. This is not special. If a few regions is helpful, then that would be fine.

Rob

Benjamin Larsson

2024-08-17 20:46 UTC #5 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 11 lines · Rob Herring

Quoted 11 lines
Hi, this is by design because of the register placement in the gpio block and the fact that the pwm functionality is intermixed in there also. As example the following registers are all GPIOCTRL:
<0x0 0x1fbf0200 0x0 0x4>,
<0x0 0x1fbf0220 0x0 0x4>,
<0x0 0x1fbf0260 0x0 0x4>,
<0x0 0x1fbf0264 0x0 0x4>,
To simplify the driver code logic the complexity is moved to the dts because of that.

Quoted 7 lines

DT to OS is an ABI. Don't put the complexity there. The driver is easy to change.
Lot's of h/w blocks are just bit soup. This is not special. If a few regions is helpful, then that would be fine.
Rob

Hi, the pwm functionality is to blame.

The following is the logic that populates the direction registers (GPIOCTRL).

for (i = 0; i < ARRAY_SIZE(pinctrl->gpiochip.dir); i++) { ptr = devm_platform_ioremap_resource(pdev, index++); if (IS_ERR(ptr))
return dev_err_probe(dev, PTR_ERR(ptr), "failed to map gpio dir regs\n");

pinctrl->gpiochip.dir[i] = ptr;
}

As example in between 0x1fbf0200, 0x1fbf0220 and 0x1fbf0260 we have pwm related registers.

The gpio block could if I count it correctly be split into 8+ regions. The dts list contain 18 rows related to the gpio block. So the savings would be ca 10 rows but a register mapping list in the driver would be needed instead.

Is that savings worth the addition of a register lookup table ?

MvH

Benjamin Larsson

Andrew Lunn

2024-08-17 21:39 UTC #6 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 35 lines · Benjamin Larsson

Quoted 11 lines · Rob Herring
Quoted 11 lines
Hi, this is by design because of the register placement in the gpio block and the fact that the pwm functionality is intermixed in there also. As example the following registers are all GPIOCTRL:
<0x0 0x1fbf0200 0x0 0x4>,
<0x0 0x1fbf0220 0x0 0x4>,
<0x0 0x1fbf0260 0x0 0x4>,
<0x0 0x1fbf0264 0x0 0x4>,
To simplify the driver code logic the complexity is moved to the dts because of that.
Quoted 7 lines
DT to OS is an ABI. Don't put the complexity there. The driver is easy to change.
Lot's of h/w blocks are just bit soup. This is not special. If a few regions is helpful, then that would be fine.
Rob
Hi, the pwm functionality is to blame.
The following is the logic that populates the direction registers (GPIOCTRL).
    for (i = 0; i < ARRAY_SIZE(pinctrl->gpiochip.dir); i++) { ptr = devm_platform_ioremap_resource(pdev, index++); if (IS_ERR(ptr))
            return dev_err_probe(dev, PTR_ERR(ptr), "failed to map gpio dir regs\n");
        pinctrl->gpiochip.dir[i] = ptr;
   }

Quoted 7 lines

As example in between 0x1fbf0200, 0x1fbf0220 and 0x1fbf0260 we have pwm related registers.
The gpio block could if I count it correctly be split into 8+ regions. The dts list contain 18 rows related to the gpio block. So the savings would be ca 10 rows but a register mapping list in the driver would be needed instead.

How messy are the GPIO and PWM registers? Are there N blocks of independent GPIO registers? and M blocks of independent PWM registers? By that, does one block of GPIO registers contain all you need for one GPIO controller? One block of PWM registers give you all you need for one PWM controller? Or are the registers for one GPIO controller scattered all over the place?

Could you point at a public datasheet?

Andrew

Benjamin Larsson

2024-08-18 12:48 UTC #7 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 11 lines · Andrew Lunn

How messy are the GPIO and PWM registers? Are there N blocks of independent GPIO registers? and M blocks of independent PWM registers? By that, does one block of GPIO registers contain all you need for one GPIO controller? One block of PWM registers give you all you need for one PWM controller? Or are the registers for one GPIO controller scattered all over the place?
Could you point at a public datasheet?
Andrew

Hi, per my understanding there is no public datasheet/register reference manual.

But here is the division of regions of the registers in the gpio block and how it is currently divided between the drivers (according to my current understanding).

1FBF0200, gpio/pinctrl
1FBF0204, gpio/pinctrl
1FBF0208, gpio/pinctrl
1FBF020C, gpio/pinctrl
1FBF0210, gpio/pinctrl
1FBF0214, gpio/pinctrl
1FBF0218, unclaimed
1FBF021C, pwm
1FBF0220, gpio/pinctrl
1FBF0224, pwm
1FBF0228, pwm
1FBF022C, pwm
1FBF0230, pwm
1FBF0234, pwm
1FBF0238, unclaimed
1FBF023C, pwm
1FBF0240, pwm
1FBF0244, pwm
1FBF0248, pwm
1FBF024C, pwm
1FBF0250, pwm
1FBF0254, pwm
1FBF0258, pwm
1FBF025C, pwm
1FBF0260, gpio/pinctrl
1FBF0264, gpio/pinctrl
1FBF0268, gpio/pinctrl
1FBF0270, gpio/pinctrl
1FBF0278, gpio/pinctrl
1FBF027C, gpio/pinctrl
1FBF0280, gpio/pinctrl
1FBF0284, gpio/pinctrl
1FBF0288, gpio/pinctrl
1FBF028C, gpio/pinctrl
1FBF0290, gpio/pinctrl
1FBF0294, gpio/pinctrl
1FBF0298, pwm
1FBF029C, pwm
1FBF02A0, unclaimed
1FBF02A4, unclaimed
1FBF02A8, unclaimed
1FBF02AC, unclaimed
1FBF02B0, unclaimed
1FBF02B4, unclaimed
1FBF02B8, unclaimed
1FBF02BC, pwm (but currently unclaimed)

The gpio functions are split in 2x32bit register banks. The pin-io and interrupt support for these are split amongst the regions.

MvH

Benjamin Larsson

Andrew Lunn

2024-08-18 16:02 UTC #8 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 19 lines · Benjamin Larsson

Quoted 11 lines · Andrew Lunn
How messy are the GPIO and PWM registers? Are there N blocks of independent GPIO registers? and M blocks of independent PWM registers? By that, does one block of GPIO registers contain all you need for one GPIO controller? One block of PWM registers give you all you need for one PWM controller? Or are the registers for one GPIO controller scattered all over the place?
Could you point at a public datasheet?
Andrew
Hi, per my understanding there is no public datasheet/register reference manual.
But here is the division of regions of the registers in the gpio block and how it is currently divided between the drivers (according to my current understanding).

Quoted 6 lines

1FBF0200, gpio/pinctrl
1FBF0204, gpio/pinctrl
1FBF0208, gpio/pinctrl
1FBF020C, gpio/pinctrl
1FBF0210, gpio/pinctrl
1FBF0214, gpio/pinctrl

A typical SoC has multiple instances of a GPIO controller. Each GPIO controller typically has 4 or 5 registers: In, Out, Direction, Interrupt Enable, Interrupt Status. If these 4 or 5 registers are contiguous, you could have one DT node per controller, rather than one node for all GPIO controllers.

If the hardware designer has really messed up and fully interleaved GPIO and PWM, it might be better to have an MFD. The MFD node has a single reg covering the entire range. The MFD would then map the whole range, and provide accessors to the child devices. Hard code the knowledge of what registers are where. Given how badly the hardware is designed, it is unlikely it will get reused in the future, so there is no point putting lots of stuff into DT. Hard code it.

Andrew

Christian Marangi

2024-08-18 16:06 UTC #9 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 33 lines · Andrew Lunn

Quoted 19 lines · Benjamin Larsson
Quoted 11 lines · Andrew Lunn
How messy are the GPIO and PWM registers? Are there N blocks of independent GPIO registers? and M blocks of independent PWM registers? By that, does one block of GPIO registers contain all you need for one GPIO controller? One block of PWM registers give you all you need for one PWM controller? Or are the registers for one GPIO controller scattered all over the place?
Could you point at a public datasheet?
Andrew
Hi, per my understanding there is no public datasheet/register reference manual.
But here is the division of regions of the registers in the gpio block and how it is currently divided between the drivers (according to my current understanding).
Quoted 6 lines
1FBF0200, gpio/pinctrl
1FBF0204, gpio/pinctrl
1FBF0208, gpio/pinctrl
1FBF020C, gpio/pinctrl
1FBF0210, gpio/pinctrl
1FBF0214, gpio/pinctrl
A typical SoC has multiple instances of a GPIO controller. Each GPIO controller typically has 4 or 5 registers: In, Out, Direction, Interrupt Enable, Interrupt Status. If these 4 or 5 registers are contiguous, you could have one DT node per controller, rather than one node for all GPIO controllers.

Quoted 8 lines

If the hardware designer has really messed up and fully interleaved GPIO and PWM, it might be better to have an MFD. The MFD node has a single reg covering the entire range. The MFD would then map the whole range, and provide accessors to the child devices. Hard code the knowledge of what registers are where. Given how badly the hardware is designed, it is unlikely it will get reused in the future, so there is no point putting lots of stuff into DT. Hard code it.

Problem is that the MFD will also affect other stuff like watchdog... thermal sensor/monitor, clocks... They really messed and put in that range all kind of stuff so we would end up in a very big mapped range and lots of child for the MFD.

Signature · 1 line

	Ansuel

Lorenzo Bianconi

author maintainer

2024-08-18 16:15 UTC #10 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

In reply to Andrew Lunn

Quoted 27 lines · Andrew Lunn

Quoted 19 lines · Benjamin Larsson
Quoted 11 lines · Andrew Lunn
How messy are the GPIO and PWM registers? Are there N blocks of independent GPIO registers? and M blocks of independent PWM registers? By that, does one block of GPIO registers contain all you need for one GPIO controller? One block of PWM registers give you all you need for one PWM controller? Or are the registers for one GPIO controller scattered all over the place?
Could you point at a public datasheet?
Andrew
Hi, per my understanding there is no public datasheet/register reference manual.
But here is the division of regions of the registers in the gpio block and how it is currently divided between the drivers (according to my current understanding).
Quoted 6 lines
1FBF0200, gpio/pinctrl
1FBF0204, gpio/pinctrl
1FBF0208, gpio/pinctrl
1FBF020C, gpio/pinctrl
1FBF0210, gpio/pinctrl
1FBF0214, gpio/pinctrl

Quoted 5 lines

A typical SoC has multiple instances of a GPIO controller. Each GPIO controller typically has 4 or 5 registers: In, Out, Direction, Interrupt Enable, Interrupt Status. If these 4 or 5 registers are contiguous, you could have one DT node per controller, rather than one node for all GPIO controllers.

it is the same for en7581 pinctrl too. I think we can squash most of the gpio/irq registers into "bigger" io-regions (just keeping a couple of holes for pwm and leds). It is just a matter of moving the logic from the dts to the driver. I am currently working on it. I will post v2 soon.

Quoted 8 lines

If the hardware designer has really messed up and fully interleaved GPIO and PWM, it might be better to have an MFD. The MFD node has a single reg covering the entire range. The MFD would then map the whole range, and provide accessors to the child devices. Hard code the knowledge of what registers are where. Given how badly the hardware is designed, it is unlikely it will get reused in the future, so there is no point putting lots of stuff into DT. Hard code it.

I am not sure it is possible/feasible to implement a MFD device here since the mapped region is huge and sparse.

Regards,
Lorenzo

Quoted 2 lines

Andrew

Benjamin Larsson

2024-08-18 16:59 UTC #11 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

In reply to Andrew Lunn

Quoted 28 lines · Andrew Lunn

Quoted 8 lines
Hi, per my understanding there is no public datasheet/register reference manual.
But here is the division of regions of the registers in the gpio block and how it is currently divided between the drivers (according to my current understanding).
Quoted 6 lines
1FBF0200, gpio/pinctrl
1FBF0204, gpio/pinctrl
1FBF0208, gpio/pinctrl
1FBF020C, gpio/pinctrl
1FBF0210, gpio/pinctrl
1FBF0214, gpio/pinctrl
A typical SoC has multiple instances of a GPIO controller. Each GPIO controller typically has 4 or 5 registers: In, Out, Direction, Interrupt Enable, Interrupt Status. If these 4 or 5 registers are contiguous, you could have one DT node per controller, rather than one node for all GPIO controllers.
If the hardware designer has really messed up and fully interleaved GPIO and PWM, it might be better to have an MFD. The MFD node has a single reg covering the entire range. The MFD would then map the whole range, and provide accessors to the child devices. Hard code the knowledge of what registers are where. Given how badly the hardware is designed, it is unlikely it will get reused in the future, so there is no point putting lots of stuff into DT. Hard code it.

Quoted 1 line

Andrew

Hi, the pwm driver could be re-used on the EN7523 SoC. Future Airoha SoCs will most likely have the same ip-block also.

MvH

Benjamin Larsson

Andrew Lunn

2024-08-18 17:35 UTC #12 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

Quoted 2 lines

Hi, the pwm driver could be re-used on the EN7523 SoC. Future Airoha SoCs will most likely have the same ip-block also.

A lot will depend on if they sort out the mess they made with the registers. Given how simple these drivers are, it is sometimes better to just write a new driver once the registers are in sane blocks, rather than all interleaved.

Andrew

Lorenzo Bianconi

author maintainer

2024-08-18 14:22 UTC #13 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

In reply to Rob Herring

Quoted 40 lines · Benjamin Larsson

Quoted 39 lines · Krzysztof Kozlowski
Quoted 26 lines
Quoted 16 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +16 -0
+      pio: pinctrl@1fa20214 {
+        compatible = "airoha,en7581-pinctrl";
+        reg = <0x0 0x1fa20214 0x0 0x30>,
+              <0x0 0x1fa2027c 0x0 0x8>,
+              <0x0 0x1fbf0234 0x0 0x4>,
+              <0x0 0x1fbf0268 0x0 0x4>,
+              <0x0 0x1fa2001c 0x0 0x50>,
+              <0x0 0x1fa2018c 0x0 0x4>,
+              <0x0 0x1fbf0204 0x0 0x4>,
+              <0x0 0x1fbf0270 0x0 0x4>,
+              <0x0 0x1fbf0200 0x0 0x4>,
+              <0x0 0x1fbf0220 0x0 0x4>,
+              <0x0 0x1fbf0260 0x0 0x4>,
+              <0x0 0x1fbf0264 0x0 0x4>,
+              <0x0 0x1fbf0214 0x0 0x4>,
+              <0x0 0x1fbf0278 0x0 0x4>,
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 388
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0
+              <0x0 0x1fbf0208 0x0 0x4>,
+              <0x0 0x1fbf027c 0x0 0x4>,
+              <0x0 0x1fbf0210 0x0 0x4>,
+              <0x0 0x1fbf028c 0x0 0x4>,
+              <0x0 0x1fbf0290 0x0 0x4>,
+              <0x0 0x1fbf0294 0x0 0x4>,
+              <0x0 0x1fbf020c 0x0 0x4>,
+              <0x0 0x1fbf0280 0x0 0x4>,
+              <0x0 0x1fbf0284 0x0 0x4>,
+              <0x0 0x1fbf0288 0x0 0x4>;
Quoted 2 lines
Why are you mapping individual registers? At least half of these are continuous.
Hi, this is by design because of the register placement in the gpio block and the fact that the pwm functionality is intermixed in there also. As example the following registers are all GPIOCTRL:
<0x0 0x1fbf0200 0x0 0x4>,
<0x0 0x1fbf0220 0x0 0x4>,
<0x0 0x1fbf0260 0x0 0x4>,
<0x0 0x1fbf0264 0x0 0x4>,

Quoted 8 lines

Quoted 2 lines
To simplify the driver code logic the complexity is moved to the dts because of that.
DT to OS is an ABI. Don't put the complexity there. The driver is easy to change.
Lot's of h/w blocks are just bit soup. This is not special. If a few regions is helpful, then that would be fine.

ack, I guess we can try to move the complexity in the driver, at least for gpio-irq controllers, merging regs whenever possible. I will work on it.

Regards,
Lorenzo

Quoted 2 lines

Rob

Lorenzo Bianconi

author maintainer

2024-08-18 14:20 UTC #14 lore raw

Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller

In reply to Krzysztof Kozlowski

[...]

Quoted 4 lines

Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +4 -0
+allOf:
+  - $ref: pinctrl.yaml#
+
+required:

Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 78
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +6 -0
+  - compatible
+  - reg
+  - gpio-controller
+  - "#gpio-cells"
+
+patternProperties:
Keep it after properties: block.

ack, I will fix it in v2

Quoted 11 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 87
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +9 -0
+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    patternProperties:
+      '^.*mux.*$':
+        type: object
+        additionalProperties: false
+        description: |

Quoted 1 line

Do not need '|' unless you need to preserve formatting.

ack, I will fix it in v2

Quoted 14 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 99

Quoted 13 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +12 -0

+          pinmux configuration nodes.
+
+        $ref: /schemas/pinctrl/pinmux-node.yaml
+        properties:
+          function:
+            description:
+              A string containing the name of the function to mux to the group.
+            enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
+                   pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0,
+                   phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
+                   phy3_led1, phy4_led1]
+          groups:

Quoted 2 lines

minItems: 1
maxItems: 32 (or whatever is sensible)

I was assuming the default values are minIems = maxItems = 1 and we can overwrite maxItems if required (e.g. for "uart" or for "pcm_spi" blocks). Am I missing something?

Quoted 223 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +222 -0

+            description:
+              An array of strings. Each string contains the name of a group.
+        required:
+          - function
+          - groups
+
+        allOf:
+          - if:
+              properties:
+                function:
+                  const: pon
+            then:
+              properties:
+                groups:
+                  enum: [pon]
+          - if:
+              properties:
+                function:
+                  const: tod_1pps
+            then:
+              properties:
+                groups:
+                  enum: [pon_tod_1pps, gsw_tod_1pps]
+          - if:
+              properties:
+                function:
+                  const: sipo
+            then:
+              properties:
+                groups:
+                  enum: [sipo, sipo_rclk]
+          - if:
+              properties:
+                function:
+                  const: mdio
+            then:
+              properties:
+                groups:
+                  enum: [mdio]
+          - if:
+              properties:
+                function:
+                  const: uart
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, uart4,
+                           uart5]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [i2c1]
+          - if:
+              properties:
+                function:
+                  const: jtag
+            then:
+              properties:
+                groups:
+                  enum: [jtag_udi, jtag_dfd]
+          - if:
+              properties:
+                function:
+                  const: pcm
+            then:
+              properties:
+                groups:
+                  enum: [pcm1, pcm2]
+          - if:
+              properties:
+                function:
+                  const: spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [spi_quad, spi_cs1]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: pcm_spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
+                           pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3,
+                           pcm_spi_cs4]
+                  maxItems: 7
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [i2s]
+          - if:
+              properties:
+                function:
+                  const: emmc
+            then:
+              properties:
+                groups:
+                  enum: [emmc]
+          - if:
+              properties:
+                function:
+                  const: pnand
+            then:
+              properties:
+                groups:
+                  enum: [pnand]
+          - if:
+              properties:
+                function:
+                  const: pcie_reset
+            then:
+              properties:
+                groups:
+                  enum: [pcie_reset0, pcie_reset1, pcie_reset2]
+          - if:
+              properties:
+                function:
+                  const: pwm
+            then:
+              properties:
+                groups:
+                  enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
+                         gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
+                         gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                         gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
+                         gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
+                         gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
+                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
+          - if:
+              properties:
+                function:
+                  const: phy1_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy2_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy3_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy4_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio33, gpio34, gpio35, gpio42]
+          - if:
+              properties:
+                function:
+                  const: phy1_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy2_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy3_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+          - if:
+              properties:
+                function:
+                  const: phy4_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio43, gpio44, gpio45, gpio46]
+
+      '^.*conf.*$':
+        type: object
+        additionalProperties: false
+        description:
+          pinconf configuration nodes.
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+
+        properties:
+          pins:
+            description:
+              An array of strings. Each string contains the name of a pin.
+            items:
+              enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk,
+                     spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4,
+                     gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,

Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 327

Quoted 6 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +6 -0

+                     gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                     gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
+                     gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33,
+                     gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40,
+                     gpio41, gpio42, gpio43, gpio44, gpio45, gpio46,
+                     pcie_reset0, pcie_reset1, pcie_reset2]

minItems

ack, I will fix it in v2.

Quoted 12 lines

Quoted 12 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +11 -0
+            maxItems: 58
+
+          bias-disable: true
+
+          bias-pull-up: true
+
+          bias-pull-down: true
+
+          input-enable: true
+
+          output-enable: true

Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 344
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +6 -0
+
+          output-low: true
+
+          output-high: true
+
+          drive-open-drain: true
Drop blank lines between these.

ack, I will fix it in v2.

Quoted 4 lines

Review
Quoted 2 lines
(quoted diff) +2 -0
+
+          drive-strength:
What are the units? Shouldn't this be drive-strength-microamp?

nope, it is in mA. I will add a description to specify it.

Quoted 101 lines

Quoted 33 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +32 -0

+            enum: [2, 4, 6, 8]
+
+        required:
+          - pins
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pio: pinctrl@1fa20214 {
+        compatible = "airoha,en7581-pinctrl";
+        reg = <0x0 0x1fa20214 0x0 0x30>,
+              <0x0 0x1fa2027c 0x0 0x8>,
+              <0x0 0x1fbf0234 0x0 0x4>,
+              <0x0 0x1fbf0268 0x0 0x4>,
+              <0x0 0x1fa2001c 0x0 0x50>,
+              <0x0 0x1fa2018c 0x0 0x4>,
+              <0x0 0x1fbf0204 0x0 0x4>,
+              <0x0 0x1fbf0270 0x0 0x4>,
+              <0x0 0x1fbf0200 0x0 0x4>,
+              <0x0 0x1fbf0220 0x0 0x4>,
+              <0x0 0x1fbf0260 0x0 0x4>,
+              <0x0 0x1fbf0264 0x0 0x4>,
+              <0x0 0x1fbf0214 0x0 0x4>,
+              <0x0 0x1fbf0278 0x0 0x4>,

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 388

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +10 -0

+              <0x0 0x1fbf0208 0x0 0x4>,
+              <0x0 0x1fbf027c 0x0 0x4>,
+              <0x0 0x1fbf0210 0x0 0x4>,
+              <0x0 0x1fbf028c 0x0 0x4>,
+              <0x0 0x1fbf0290 0x0 0x4>,
+              <0x0 0x1fbf0294 0x0 0x4>,
+              <0x0 0x1fbf020c 0x0 0x4>,
+              <0x0 0x1fbf0280 0x0 0x4>,
+              <0x0 0x1fbf0284 0x0 0x4>,
+              <0x0 0x1fbf0288 0x0 0x4>;

Why are you mapping individual registers? At least half of these are continuous.

Quoted 54 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +54 -0

+
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 13 47>;
+
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+        pcie1-rst-pins {
+          conf {
+            pins = "pcie_reset1";
+            drive-open-drain = <1>;
+          };
+        };
+
+        pwm-pins {
+          mux {
+            function = "pwm";
+            groups = "gpio18";
+          };
+        };
+
+        spi-pins {
+          mux {
+            function = "spi";
+            groups = "spi_quad", "spi_cs1";
+          };
+        };
+
+        uuart2-pins {
+          mux {
+            function = "uart";
+            groups = "uart2", "uart2_cts_rts";
+          };
+        };
+
+        uar5-pins {
+          mux {
+            function = "uart";
+            groups = "uart5";
+          };
+        };
+
+        mmc-pins {
+          mux {
+            function = "emmc";
+            groups = "emmc";
+          };
+        };
+
+        mdio-pins {
+          mux {

Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 448
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +6 -0
+            function = "mdio";
+            groups = "mdio";
+          };
+
+          conf {
+            pins = "gpio2";
What is the point of having both groups and pins?

"pins" is specific for "conf" block and it is used to specify the pins where we need to apply the configuration while "group" is just used in the "mux" block. Am I missing something?

Quoted 10 lines

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +9 -0
+            output-enable;
+          };
+        };
+
+        gswp1-led0-pins {
+          mux {
+            function = "phy1_led0";
+            groups = "gpio33";
+          };

Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml line 463
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file +6 -0
+        };
+
+        gswp2-led1-pins {
+          mux {
+            function = "phy2_led1";
+            groups = "gpio44";
That's not a group but pin name.

Looking at the patch 2/2, "gpio44" is actually a group used to specify a single pin group.

Regards,
Lorenzo

Quoted 4 lines

Best regards,
Krzysztof

Lorenzo Bianconi

author maintainer

2024-08-11 16:12 UTC #15 lore raw

PATCH 2/2 pinctrl: airoha: Add support for EN7581 SoC

In reply to Lorenzo Bianconi

Tested-by Benjamin Larsson <[email protected]>

Co-developed-by Benjamin Larsson <[email protected]>

Signed-off-by Benjamin Larsson <[email protected]>

Signed-off-by Lorenzo Bianconi <[email protected]>

---
 MAINTAINERS                               |    7 +
 drivers/pinctrl/mediatek/Kconfig          |   14 +-
 drivers/pinctrl/mediatek/Makefile         |    1 +
 drivers/pinctrl/mediatek/pinctrl-airoha.c | 2983 +++++++++++++++++++++
 4 files changed, 3004 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-airoha.c

MAINTAINERS +7 -0

index 804dcbc448b6..dfea9a52abb4 100644
@@ -17670,6 +17670,13 @@ F:	drivers/pinctrl/
 F:	include/dt-bindings/pinctrl/
 F:	include/linux/pinctrl/
 
+PIN CONTROLLER - AIROHA
+M:	Lorenzo Bianconi <[email protected]>
+L:	[email protected] (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
+F:	drivers/pinctrl/mediatek/pinctrl-airoha.c
+
 PIN CONTROLLER - AMD
 M:	Basavaraj Natikar <[email protected]>
 M:	Shyam Sundar S K <[email protected]>

drivers/pinctrl/mediatek/Kconfig +13 -1

index 7af287252834..7443a090d40b 100644
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 menu "MediaTek pinctrl drivers"
-	depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST
+	depends on ARCH_MEDIATEK || ARCH_AIROHA || RALINK || COMPILE_TEST
 
 config EINT_MTK
 	tristate "MediaTek External Interrupt Support"

@@ -126,6 +126,18 @@ config PINCTRL_MT8127
 	select PINCTRL_MTK
 
 # For ARMv8 SoCs
+config PINCTRL_AIROHA
+	tristate "Airoha pin control"
+	depends on OF
+	depends on ARM64 || COMPILE_TEST
+	select PINMUX
+	select GENERIC_PINCONF
+	select GPIOLIB
+	select GPIOLIB_IRQCHIP
+	help
+	  Say yes here to support pin controller and gpio driver
+	  on Airoha EN7581 SoC.
+
 config PINCTRL_MT2712
 	bool "MediaTek MT2712 pin control"
 	depends on OF

drivers/pinctrl/mediatek/Makefile +1 -0

index 680f7e8526e0..1405d434218e 100644
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MTK_MOORE)		+= pinctrl-moore.o
 obj-$(CONFIG_PINCTRL_MTK_PARIS)		+= pinctrl-paris.o
 
 # SoC Drivers
+obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
 obj-$(CONFIG_PINCTRL_MT7620)		+= pinctrl-mt7620.o
 obj-$(CONFIG_PINCTRL_MT7621)		+= pinctrl-mt7621.o
 obj-$(CONFIG_PINCTRL_MT76X8)		+= pinctrl-mt76x8.o

drivers/pinctrl/mediatek/pinctrl-airoha.c new file +2983 -0

2,955 lines not on this page · raw message

The rest of this diff is not shown. View the raw message.

Signature · 1 line

2.46.0

Part of the diff is not shown here. View the raw message.

kernel test robot

build bot

2024-08-11 21:08 UTC #16 lore raw

Re: [PATCH 2/2] pinctrl: airoha: Add support for EN7581 SoC

kernel test robot noticed the following build warnings:

Hi Lorenzo,

kernel test robot noticed the following build warnings:

[auto build test WARNING on linusw-pinctrl/devel]
[also build test WARNING on linusw-pinctrl/for-next linus/master v6.11-rc2 next-20240809] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Lorenzo-Bianconi/dt-bindings-pinctrl-airoha-Add-EN7581-pinctrl-controller/20240812-001436
base:   https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
patch link:    https://lore.kernel.org/r/c69c4a9b8e57eebdde0521731b8cd9f92ed4891b.1723392444.git.lorenzo%40kernel.org
patch subject: [PATCH 2/2] pinctrl: airoha: Add support for EN7581 SoC
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20240812/[email protected]/config)
compiler: m68k-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240812/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
    1922 | static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
         |                                                                  ^
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   In file included from include/linux/printk.h:574,
                    from include/asm-generic/bug.h:22,
                    from arch/m68k/include/asm/bug.h:32,
                    from include/linux/bug.h:5,
                    from include/linux/thread_info.h:13,
                    from include/asm-generic/preempt.h:5,
                    from ./arch/m68k/include/generated/asm/preempt.h:1,
                    from include/linux/preempt.h:79,
                    from include/linux/spinlock.h:56,
                    from include/linux/irq.h:14,
                    from include/linux/irqchip/chained_irq.h:10,
                    from include/linux/gpio/driver.h:8,
                    from drivers/pinctrl/mediatek/pinctrl-airoha.c:9:
   drivers/pinctrl/mediatek/pinctrl-airoha.c: In function 'airoha_pinmux_set_mux':
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2279:21: error: 'struct function_desc' has no member named 'name'
    2279 |                 desc->name, grp->grp.name);
         |                     ^~
   include/linux/dynamic_debug.h:224:29: note: in definition of macro '__dynamic_func_call_cls'
     224 |                 func(&id, ##__VA_ARGS__);                       \
         |                             ^~~~~~~~~~~
   include/linux/dynamic_debug.h:250:9: note: in expansion of macro '_dynamic_func_call_cls'
     250 |         _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
         |         ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/dynamic_debug.h:273:9: note: in expansion of macro '_dynamic_func_call'
     273 |         _dynamic_func_call(fmt, __dynamic_dev_dbg,              \
         |         ^~~~~~~~~~~~~~~~~~
   include/linux/dev_printk.h:165:9: note: in expansion of macro 'dynamic_dev_dbg'
     165 |         dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
         |         ^~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2278:9: note: in expansion of macro 'dev_dbg'
    2278 |         dev_dbg(pctrl_dev->dev, "enable function %s group %s\n",
         |         ^~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c: In function 'airoha_pinctrl_get_conf':
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2359:38: error: implicit declaration of function '__bf_shf' [-Wimplicit-function-declaration]
    2359 |         *val = (*val & reg->mask) >> __bf_shf(reg->mask);
         |                                      ^~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c: In function 'airoha_pinctrl_probe':
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2946:61: error: 'const struct function_desc' has no member named 'name'
    2946 |                                                   func->desc.name,
         |                                                             ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2947:61: error: 'const struct function_desc' has no member named 'group_names'
    2947 |                                                   func->desc.group_names,
         |                                                             ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2948:61: error: 'const struct function_desc' has no member named 'num_group_names'
    2948 |                                                   func->desc.num_group_names,
         |                                                             ^
   In file included from include/linux/device.h:15,
                    from include/linux/platform_device.h:13,
                    from drivers/pinctrl/mediatek/pinctrl-airoha.c:22:
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2952:43: error: 'const struct function_desc' has no member named 'name'
    2952 |                                 func->desc.name);
         |                                           ^
   include/linux/dev_printk.h:110:37: note: in definition of macro 'dev_printk_index_wrap'
     110 |                 _p_func(dev, fmt, ##__VA_ARGS__);                       \
         |                                     ^~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2951:25: note: in expansion of macro 'dev_err'
    2951 |                         dev_err(&pdev->dev, "Failed to register function %s\n",
         |                         ^~~~~~~

vim +1922 drivers/pinctrl/mediatek/pinctrl-airoha.c

1921

> 1922	static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {

1923 PINCTRL_FUNC_DESC(pon),
1924 PINCTRL_FUNC_DESC(tod_1pps),
1925 PINCTRL_FUNC_DESC(sipo),
1926 PINCTRL_FUNC_DESC(mdio),
1927 PINCTRL_FUNC_DESC(uart),
1928 PINCTRL_FUNC_DESC(i2c),
1929 PINCTRL_FUNC_DESC(jtag),
1930 PINCTRL_FUNC_DESC(pcm),
1931 PINCTRL_FUNC_DESC(spi),
1932 PINCTRL_FUNC_DESC(pcm_spi),
1933 PINCTRL_FUNC_DESC(i2s),
1934 PINCTRL_FUNC_DESC(emmc),
1935 PINCTRL_FUNC_DESC(pnand),
1936 PINCTRL_FUNC_DESC(pcie_reset),
1937 PINCTRL_FUNC_DESC(pwm),
1938 PINCTRL_FUNC_DESC(phy1_led0),
1939 PINCTRL_FUNC_DESC(phy2_led0),
1940 PINCTRL_FUNC_DESC(phy3_led0),
1941 PINCTRL_FUNC_DESC(phy4_led0),
1942 PINCTRL_FUNC_DESC(phy1_led1),
1943 PINCTRL_FUNC_DESC(phy2_led1),
1944 PINCTRL_FUNC_DESC(phy3_led1),
1945 PINCTRL_FUNC_DESC(phy4_led1),
1946 };
1947

Signature · 2 lines

0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

kernel test robot

build bot

2024-08-11 21:49 UTC #17 lore raw

Re: [PATCH 2/2] pinctrl: airoha: Add support for EN7581 SoC

In reply to Lorenzo Bianconi

kernel test robot noticed the following build errors:

Hi Lorenzo,

kernel test robot noticed the following build errors:

[auto build test ERROR on linusw-pinctrl/devel]
[also build test ERROR on linusw-pinctrl/for-next linus/master v6.11-rc2 next-20240809] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Lorenzo-Bianconi/dt-bindings-pinctrl-airoha-Add-EN7581-pinctrl-controller/20240812-001436
base:   https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
patch link:    https://lore.kernel.org/r/c69c4a9b8e57eebdde0521731b8cd9f92ed4891b.1723392444.git.lorenzo%40kernel.org
patch subject: [PATCH 2/2] pinctrl: airoha: Add support for EN7581 SoC
config: hexagon-allmodconfig (https://download.01.org/0day-ci/archive/20240812/[email protected]/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project f86594788ce93b696675c94f54016d27a6c21d18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240812/[email protected]/reproduce)

All error/warnings (new ones prefixed by >>):

In file included from drivers/pinctrl/mediatek/pinctrl-airoha.c:9:
In file included from include/linux/gpio/driver.h:8:
In file included from include/linux/irqchip/chained_irq.h:10:
In file included from include/linux/irq.h:20:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:548:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]

     548 |         val = __raw_readb(PCI_IOBASE + addr);
         |                           ~~~~~~~~~~ ^
   include/asm-generic/io.h:561:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     561 |         val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
         |                                                         ~~~~~~~~~~ ^
   include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
      37 | #define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
         |                                                   ^
   In file included from drivers/pinctrl/mediatek/pinctrl-airoha.c:9:
   In file included from include/linux/gpio/driver.h:8:
   In file included from include/linux/irqchip/chained_irq.h:10:
   In file included from include/linux/irq.h:20:
   In file included from include/linux/io.h:14:
   In file included from arch/hexagon/include/asm/io.h:328:
   include/asm-generic/io.h:574:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     574 |         val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
         |                                                         ~~~~~~~~~~ ^
   include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
      35 | #define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
         |                                                   ^
   In file included from drivers/pinctrl/mediatek/pinctrl-airoha.c:9:
   In file included from include/linux/gpio/driver.h:8:
   In file included from include/linux/irqchip/chained_irq.h:10:
   In file included from include/linux/irq.h:20:
   In file included from include/linux/io.h:14:
   In file included from arch/hexagon/include/asm/io.h:328:
   include/asm-generic/io.h:585:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     585 |         __raw_writeb(value, PCI_IOBASE + addr);
         |                             ~~~~~~~~~~ ^
   include/asm-generic/io.h:595:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     595 |         __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
         |                                                       ~~~~~~~~~~ ^
   include/asm-generic/io.h:605:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
     605 |         __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
         |                                                       ~~~~~~~~~~ ^
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:1923:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1923 |         PINCTRL_FUNC_DESC(pon),
         |         ^~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:279:1: note: expanded from here
     279 | "pon"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1924:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1924 |         PINCTRL_FUNC_DESC(tod_1pps),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:284:1: note: expanded from here
     284 | "tod_1pps"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1925:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1925 |         PINCTRL_FUNC_DESC(sipo),
         |         ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:289:1: note: expanded from here
     289 | "sipo"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1926:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1926 |         PINCTRL_FUNC_DESC(mdio),
         |         ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:294:1: note: expanded from here
     294 | "mdio"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1927:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1927 |         PINCTRL_FUNC_DESC(uart),
         |         ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:299:1: note: expanded from here
     299 | "uart"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1928:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1928 |         PINCTRL_FUNC_DESC(i2c),
         |         ^~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:304:1: note: expanded from here
     304 | "i2c"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1929:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1929 |         PINCTRL_FUNC_DESC(jtag),
         |         ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:309:1: note: expanded from here
     309 | "jtag"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1930:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1930 |         PINCTRL_FUNC_DESC(pcm),
         |         ^~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:314:1: note: expanded from here
     314 | "pcm"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1931:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1931 |         PINCTRL_FUNC_DESC(spi),
         |         ^~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:319:1: note: expanded from here
     319 | "spi"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1932:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1932 |         PINCTRL_FUNC_DESC(pcm_spi),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:324:1: note: expanded from here
     324 | "pcm_spi"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1933:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1933 |         PINCTRL_FUNC_DESC(i2s),
         |         ^~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:329:1: note: expanded from here
     329 | "i2s"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1934:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1934 |         PINCTRL_FUNC_DESC(emmc),
--
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1935:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1935 |         PINCTRL_FUNC_DESC(pnand),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:339:1: note: expanded from here
     339 | "pnand"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1936:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1936 |         PINCTRL_FUNC_DESC(pcie_reset),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:344:1: note: expanded from here
     344 | "pcie_reset"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1937:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1937 |         PINCTRL_FUNC_DESC(pwm),
         |         ^~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:349:1: note: expanded from here
     349 | "pwm"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1938:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1938 |         PINCTRL_FUNC_DESC(phy1_led0),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:354:1: note: expanded from here
     354 | "phy1_led0"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1939:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1939 |         PINCTRL_FUNC_DESC(phy2_led0),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:359:1: note: expanded from here
     359 | "phy2_led0"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1940:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1940 |         PINCTRL_FUNC_DESC(phy3_led0),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:364:1: note: expanded from here
     364 | "phy3_led0"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1941:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1941 |         PINCTRL_FUNC_DESC(phy4_led0),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:369:1: note: expanded from here
     369 | "phy4_led0"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1942:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1942 |         PINCTRL_FUNC_DESC(phy1_led1),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:374:1: note: expanded from here
     374 | "phy1_led1"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1943:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1943 |         PINCTRL_FUNC_DESC(phy2_led1),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:379:1: note: expanded from here
     379 | "phy2_led1"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1944:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1944 |         PINCTRL_FUNC_DESC(phy3_led1),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:384:1: note: expanded from here
     384 | "phy3_led1"
         | ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1945:2: warning: suggest braces around initialization of subobject [-Wmissing-braces]
    1945 |         PINCTRL_FUNC_DESC(phy4_led1),
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:33:13: note: expanded from macro 'PINCTRL_FUNC_DESC'
      33 |                 .desc = { #id, id##_groups, ARRAY_SIZE(id##_groups) },  \
         |                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   <scratch space>:389:1: note: expanded from here
     389 | "phy4_led1"
         | ^
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2279:9: error: no member named 'name' in 'struct function_desc'
    2279 |                 desc->name, grp->grp.name);
         |                 ~~~~  ^
   include/linux/dev_printk.h:165:39: note: expanded from macro 'dev_dbg'
     165 |         dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
         |                                              ^~~~~~~~~~~
   include/linux/dynamic_debug.h:274:19: note: expanded from macro 'dynamic_dev_dbg'
     274 |                            dev, fmt, ##__VA_ARGS__)
         |                                        ^~~~~~~~~~~
   include/linux/dynamic_debug.h:250:59: note: expanded from macro '_dynamic_func_call'
     250 |         _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
         |                                                                  ^~~~~~~~~~~
   include/linux/dynamic_debug.h:248:65: note: expanded from macro '_dynamic_func_call_cls'
     248 |         __dynamic_func_call_cls(__UNIQUE_ID(ddebug), cls, fmt, func, ##__VA_ARGS__)
         |                                                                        ^~~~~~~~~~~
   include/linux/dynamic_debug.h:224:15: note: expanded from macro '__dynamic_func_call_cls'
     224 |                 func(&id, ##__VA_ARGS__);                       \
         |                             ^~~~~~~~~~~
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2359:31: error: call to undeclared function '__bf_shf'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
    2359 |         *val = (*val & reg->mask) >> __bf_shf(reg->mask);
         |                                      ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2376:14: error: call to undeclared function '__bf_shf'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
    2376 |                            val << __bf_shf(reg->mask));
         |                                   ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2946:20: error: no member named 'name' in 'struct function_desc'
    2946 |                                                   func->desc.name,
         |                                                   ~~~~~~~~~~ ^
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2947:20: error: no member named 'group_names' in 'struct function_desc'
    2947 |                                                   func->desc.group_names,
         |                                                   ~~~~~~~~~~ ^
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2948:20: error: no member named 'num_group_names' in 'struct function_desc'
    2948 |                                                   func->desc.num_group_names,
         |                                                   ~~~~~~~~~~ ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2952:16: error: no member named 'name' in 'struct function_desc'
    2952 |                                 func->desc.name);
         |                                 ~~~~~~~~~~ ^
   include/linux/dev_printk.h:154:65: note: expanded from macro 'dev_err'
     154 |         dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
         |                                                                        ^~~~~~~~~~~
   include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
     110 |                 _p_func(dev, fmt, ##__VA_ARGS__);                       \
         |                                     ^~~~~~~~~~~

29 warnings and 7 errors generated.

vim +2279 drivers/pinctrl/mediatek/pinctrl-airoha.c

2259
2260 static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
2261 unsigned int selector,
2262 unsigned int group)
2263 {
2264 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2265 const struct airoha_pinctrl_func *func;
2266 struct function_desc *desc;
2267 struct group_desc *grp;
2268 int i;
2269
2270 desc = pinmux_generic_get_function(pctrl_dev, selector);
2271 if (!desc)
2272 return -EINVAL;
2273
2274 grp = pinctrl_generic_get_group(pctrl_dev, group);
2275 if (!grp)
2276 return -EINVAL;
2277
2278 dev_dbg(pctrl_dev->dev, "enable function %s group %s\n",

> 2279			desc->name, grp->grp.name);
  2280	
  2281		func = desc->data;
  2282		for (i = 0; i < func->group_size; i++) {
  2283			const struct airoha_pinctrl_func_group *group;
  2284			int j;
  2285	
  2286			group = &func->groups[i];
  2287			if (strcmp(group->name, grp->grp.name))
  2288				continue;
  2289	
  2290			for (j = 0; j < group->regmap_size; j++) {
  2291				void __iomem *base;
  2292	
  2293				base = pinctrl->regs.mux[group->regmap[j].mux];
  2294				airoha_pinctrl_rmw(pinctrl,
  2295						   base + group->regmap[j].offset,
  2296						   group->regmap[j].mask,
  2297						   group->regmap[j].val);
  2298			}
  2299			return 0;
  2300		}
  2301	
  2302		return -EINVAL;
  2303	}
  2304	
  2305	static int airoha_pinmux_gpio_set_direction(struct pinctrl_dev *pctrl_dev,
  2306						    struct pinctrl_gpio_range *range,
  2307						    unsigned int pin, bool input)
  2308	{
  2309		struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
  2310		int gpio = pin - range->pin_base;
  2311	
  2312		airoha_pinctrl_gpio_set_direction(pinctrl, gpio, input);
  2313	
  2314		return 0;
  2315	}
  2316	
  2317	static int airoha_pinctrl_get_gpio_from_pin(struct pinctrl_dev *pctrl_dev,
  2318						    int pin)
  2319	{
  2320		struct pinctrl_gpio_range *range;
  2321		int gpio;
  2322	
  2323		range = pinctrl_find_gpio_range_from_pin_nolock(pctrl_dev, pin);
  2324		if (!range)
  2325			return -EINVAL;
  2326	
  2327		gpio = pin - range->pin_base;
  2328		if (gpio < 0)
  2329			return -EINVAL;
  2330	
  2331		return gpio;
  2332	}
  2333	
  2334	static const struct airoha_pinctrl_reg *
  2335	airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,
  2336				    int conf_size, int pin)
  2337	{
  2338		int i;
  2339	
  2340		for (i = 0; i < conf_size; i++) {
  2341			if (conf[i].pin == pin)
  2342				return &conf[i].reg;
  2343		}
  2344	
  2345		return NULL;
  2346	}
  2347	
  2348	static int airoha_pinctrl_get_conf(void __iomem *base,
  2349					   const struct airoha_pinctrl_conf *conf,
  2350					   int conf_size, int pin, u32 *val)
  2351	{
  2352		const struct airoha_pinctrl_reg *reg;
  2353	
  2354		reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
  2355		if (!reg)
  2356			return -EINVAL;
  2357	
  2358		*val = readl(base + reg->offset);
> 2359		*val = (*val & reg->mask) >> __bf_shf(reg->mask);
  2360	
  2361		return 0;
  2362	}
  2363	
  2364	static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
  2365					   void __iomem *base,
  2366					   const struct airoha_pinctrl_conf *conf,
  2367					   int conf_size, int pin, u32 val)
  2368	{
  2369		const struct airoha_pinctrl_reg *reg = NULL;
  2370	
  2371		reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
  2372		if (!reg)
  2373			return -EINVAL;
  2374	
  2375		airoha_pinctrl_rmw(pinctrl, base + reg->offset, reg->mask,
> 2376				   val << __bf_shf(reg->mask));

2377
2378 return 0;
2379 }
2380

Signature · 2 lines

0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

kernel test robot

build bot

2024-08-11 22:00 UTC #18 lore raw

Re: [PATCH 2/2] pinctrl: airoha: Add support for EN7581 SoC

In reply to Lorenzo Bianconi

kernel test robot noticed the following build errors:

Hi Lorenzo,

kernel test robot noticed the following build errors:

url:    https://github.com/intel-lab-lkp/linux/commits/Lorenzo-Bianconi/dt-bindings-pinctrl-airoha-Add-EN7581-pinctrl-controller/20240812-001436
base:   https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
patch link:    https://lore.kernel.org/r/c69c4a9b8e57eebdde0521731b8cd9f92ed4891b.1723392444.git.lorenzo%40kernel.org
patch subject: [PATCH 2/2] pinctrl: airoha: Add support for EN7581 SoC
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20240812/[email protected]/config)
compiler: alpha-linux-gcc (GCC) 13.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240812/[email protected]/reproduce)

All errors (new ones prefixed by >>):

drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]

    1922 | static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
         |                                                                  ^
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   drivers/pinctrl/mediatek/pinctrl-airoha.c:1922:66: warning: missing braces around initializer [-Wmissing-braces]
   In file included from include/linux/printk.h:574,
                    from include/asm-generic/bug.h:22,
                    from arch/alpha/include/asm/bug.h:23,
                    from include/linux/bug.h:5,
                    from include/linux/thread_info.h:13,
                    from include/asm-generic/preempt.h:5,
                    from ./arch/alpha/include/generated/asm/preempt.h:1,
                    from include/linux/preempt.h:79,
                    from include/linux/spinlock.h:56,
                    from include/linux/irq.h:14,
                    from include/linux/irqchip/chained_irq.h:10,
                    from include/linux/gpio/driver.h:8,
                    from drivers/pinctrl/mediatek/pinctrl-airoha.c:9:
   drivers/pinctrl/mediatek/pinctrl-airoha.c: In function 'airoha_pinmux_set_mux':
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2279:21: error: 'struct function_desc' has no member named 'name'
    2279 |                 desc->name, grp->grp.name);
         |                     ^~
   include/linux/dynamic_debug.h:224:29: note: in definition of macro '__dynamic_func_call_cls'
     224 |                 func(&id, ##__VA_ARGS__);                       \
         |                             ^~~~~~~~~~~
   include/linux/dynamic_debug.h:250:9: note: in expansion of macro '_dynamic_func_call_cls'
     250 |         _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
         |         ^~~~~~~~~~~~~~~~~~~~~~
   include/linux/dynamic_debug.h:273:9: note: in expansion of macro '_dynamic_func_call'
     273 |         _dynamic_func_call(fmt, __dynamic_dev_dbg,              \
         |         ^~~~~~~~~~~~~~~~~~
   include/linux/dev_printk.h:165:9: note: in expansion of macro 'dynamic_dev_dbg'
     165 |         dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
         |         ^~~~~~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2278:9: note: in expansion of macro 'dev_dbg'
    2278 |         dev_dbg(pctrl_dev->dev, "enable function %s group %s\n",
         |         ^~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c: In function 'airoha_pinctrl_get_conf':
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2359:38: error: implicit declaration of function '__bf_shf' [-Werror=implicit-function-declaration]
    2359 |         *val = (*val & reg->mask) >> __bf_shf(reg->mask);
         |                                      ^~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c: In function 'airoha_pinctrl_probe':
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2946:61: error: 'const struct function_desc' has no member named 'name'
    2946 |                                                   func->desc.name,
         |                                                             ^
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2947:61: error: 'const struct function_desc' has no member named 'group_names'
    2947 |                                                   func->desc.group_names,
         |                                                             ^
>> drivers/pinctrl/mediatek/pinctrl-airoha.c:2948:61: error: 'const struct function_desc' has no member named 'num_group_names'
    2948 |                                                   func->desc.num_group_names,
         |                                                             ^
   In file included from include/linux/device.h:15,
                    from include/linux/platform_device.h:13,
                    from drivers/pinctrl/mediatek/pinctrl-airoha.c:22:
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2952:43: error: 'const struct function_desc' has no member named 'name'
    2952 |                                 func->desc.name);
         |                                           ^
   include/linux/dev_printk.h:110:37: note: in definition of macro 'dev_printk_index_wrap'
     110 |                 _p_func(dev, fmt, ##__VA_ARGS__);                       \
         |                                     ^~~~~~~~~~~
   drivers/pinctrl/mediatek/pinctrl-airoha.c:2951:25: note: in expansion of macro 'dev_err'
    2951 |                         dev_err(&pdev->dev, "Failed to register function %s\n",
         |                         ^~~~~~~

cc1: some warnings being treated as errors

vim +2279 drivers/pinctrl/mediatek/pinctrl-airoha.c

> 2279			desc->name, grp->grp.name);
  2280	
  2281		func = desc->data;
  2282		for (i = 0; i < func->group_size; i++) {
  2283			const struct airoha_pinctrl_func_group *group;
  2284			int j;
  2285	
  2286			group = &func->groups[i];
  2287			if (strcmp(group->name, grp->grp.name))
  2288				continue;
  2289	
  2290			for (j = 0; j < group->regmap_size; j++) {
  2291				void __iomem *base;
  2292	
  2293				base = pinctrl->regs.mux[group->regmap[j].mux];
  2294				airoha_pinctrl_rmw(pinctrl,
  2295						   base + group->regmap[j].offset,
  2296						   group->regmap[j].mask,
  2297						   group->regmap[j].val);
  2298			}
  2299			return 0;
  2300		}
  2301	
  2302		return -EINVAL;
  2303	}
  2304	
  2305	static int airoha_pinmux_gpio_set_direction(struct pinctrl_dev *pctrl_dev,
  2306						    struct pinctrl_gpio_range *range,
  2307						    unsigned int pin, bool input)
  2308	{
  2309		struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
  2310		int gpio = pin - range->pin_base;
  2311	
  2312		airoha_pinctrl_gpio_set_direction(pinctrl, gpio, input);
  2313	
  2314		return 0;
  2315	}
  2316	
  2317	static int airoha_pinctrl_get_gpio_from_pin(struct pinctrl_dev *pctrl_dev,
  2318						    int pin)
  2319	{
  2320		struct pinctrl_gpio_range *range;
  2321		int gpio;
  2322	
  2323		range = pinctrl_find_gpio_range_from_pin_nolock(pctrl_dev, pin);
  2324		if (!range)
  2325			return -EINVAL;
  2326	
  2327		gpio = pin - range->pin_base;
  2328		if (gpio < 0)
  2329			return -EINVAL;
  2330	
  2331		return gpio;
  2332	}
  2333	
  2334	static const struct airoha_pinctrl_reg *
  2335	airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,
  2336				    int conf_size, int pin)
  2337	{
  2338		int i;
  2339	
  2340		for (i = 0; i < conf_size; i++) {
  2341			if (conf[i].pin == pin)
  2342				return &conf[i].reg;
  2343		}
  2344	
  2345		return NULL;
  2346	}
  2347	
  2348	static int airoha_pinctrl_get_conf(void __iomem *base,
  2349					   const struct airoha_pinctrl_conf *conf,
  2350					   int conf_size, int pin, u32 *val)
  2351	{
  2352		const struct airoha_pinctrl_reg *reg;
  2353	
  2354		reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
  2355		if (!reg)
  2356			return -EINVAL;
  2357	
  2358		*val = readl(base + reg->offset);
> 2359		*val = (*val & reg->mask) >> __bf_shf(reg->mask);

2360
2361 return 0;
2362 }
2363

Signature · 2 lines

0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki