clk: at91: add sama7d65 clock support
Subsystems (2)
v2 cover clk: at91: add sama7d65 clock support
From: Ryan Wanner <[email protected]>
Hello,
This series adds clock support for the SAMA7D65 SoC. There are also changes to the master clock driver and PLL driver in order to account for the increased amount of clocks being supported in this new SoC.
Trying to account for all the updates happening in this system, this patch set is based off of the most recent updates to at91-next branch.
Changes in v2:
- Correct PLL ID from PLL_ID_IMG to PLL_ID_GPU in the description.
- Adjust master clock description to match amount of master clocks 0-9.
- Correct bad spacing and bad alignment.
- Remove double variable definition.
- Add missing kfree() at end of function.
- Reorganize clk and pll driver changes in patch set.
Ryan Wanner (3):
clk: at91: clk-master: increase maximum number of clocks
clk: at91: clk-sam9x60-pll: increase maximum amount of plls
clk: at91: sama7d65: add sama7d65 pmc driver
drivers/clk/at91/Makefile | 1 + drivers/clk/at91/clk-master.c | 2 +- drivers/clk/at91/clk-sam9x60-pll.c | 2 +- drivers/clk/at91/pmc.c | 1 + drivers/clk/at91/sama7d65.c | 1373 ++++++++++++++++++++++++++++ 5 files changed, 1377 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/at91/sama7d65.c
Signature · 1 line
2.43.0
PATCH v2 1/3 clk: at91: clk-master: increase maximum number of clocks
From: Ryan Wanner <[email protected]>
Increase maximum number of vaild master clocks. The PMC for the SAMA7D65 requires 9 master clocks.
--- drivers/clk/at91/clk-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/at91/clk-master.c +1 -1
@@ -20,7 +20,7 @@#define PMC_MCR_CSS_SHIFT (16) -#define MASTER_MAX_ID 4 +#define MASTER_MAX_ID 9#define to_clk_master (hw) container_of(hw, struct clk_master, hw)
Signature · 1 line
2.43.0
Re: [PATCH v2 1/3] clk: at91: clk-master: increase maximum number of clocks
Quoted 3 lines · On 04/09/24 9:24 pm, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Increase maximum number of vaild master clocks. The PMC for the SAMA7D65
A typo ^valid
Quoted 20 lines
requires 9 master clocks.
Signed-off-by Ryan Wanner <[email protected]>--- drivers/clk/at91/clk-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/at91/clk-master.c +1
-1@@ -20,7 +20,7 @@#define PMC_MCR_CSS_SHIFT (16) -#define MASTER_MAX_ID 4 +#define MASTER_MAX_ID 9#define to_clk_master (hw) container_of(hw, struct clk_master, hw)
Signature · 2 lines
With Best Regards, Dharma B.
PATCH v2 2/3 clk: at91: clk-sam9x60-pll: increase maximum amount of plls
In reply to [email protected]From: Ryan Wanner <[email protected]>
Increase maximum amount of PLLs to 9 to support SAMA7D65 SoC PLL requirements.
--- drivers/clk/at91/clk-sam9x60-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/at91/clk-sam9x60-pll.c +1 -1
@@ -23,7 +23,7 @@#define UPLL_DIV 2#define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) -#define PLL_MAX_ID 7 +#define PLL_MAX_ID 9struct sam9x60_pll_core {struct regmap *regmap;
Signature · 1 line
2.43.0
PATCH v2 3/3 clk: at91: sama7d65: add sama7d65 pmc driver
In reply to [email protected]From: Ryan Wanner <[email protected]>
Add clock support for SAMA7D65 SoC.
--- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/pmc.c | 1 + drivers/clk/at91/sama7d65.c | 1373 +++++++++++++++++++++++++++++++++++ 3 files changed, 1375 insertions(+) create mode 100644 drivers/clk/at91/sama7d65.c
drivers/clk/at91/Makefile +1 -0
@@ -25,3 +25,4 @@ obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o obj-$(CONFIG_SOC_SAMA7G5) += sama7g5.o +obj-$(CONFIG_SOC_SAMA7D65) += sama7d65.o
drivers/clk/at91/pmc.c +1 -0
@@ -151,6 +151,7 @@ static struct syscore_ops pmc_syscore_ops = {static const struct of_device_id pmc_dt_ids[] = { { .compatible ="atmel,sama5d2-pmc" }, { .compatible ="microchip,sama7g5-pmc" , }, + { .compatible ="microchip,sama7d65-pmc" , }, {/* sentinel */ } };
drivers/clk/at91/sama7d65.c new file +1373 -0
1,373 lines not on this page · raw message
Signature · 1 line
2.43.0
Quoted 11 lines · On 04/09/2024 at 17:54, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Hello,
This series adds clock support for the SAMA7D65 SoC. There are also changes to the master clock driver and PLL driver in order to account for the increased amount of clocks being supported in this new SoC.
Trying to account for all the updates happening in this system, this patch set is based off of the most recent updates to at91-next branch.
Quoted 7 lines
Changes in v2:
- Correct PLL ID fromPLL_ID_IMGtoPLL_ID_GPUin the description.
- Adjust master clock description to match amount of master clocks 0-9.
- Correct bad spacing and bad alignment.
- Remove double variable definition.
- Add missingkfree()at end of function.
- Reorganize clk and pll driver changes in patch set.
To the whole series:
Quoted 4 lines
Ryan Wanner (3):
clk: at91: clk-master: increase maximum number of clocks
clk: at91: clk-sam9x60-pll: increase maximum amount of plls
clk: at91: sama7d65: add sama7d65 pmc driver
For the record, additions to the DT binding are posed here:
https://lore.kernel.org/lkml/[email protected]/
Best regards,
Nicolas
Quoted 8 lines
drivers/clk/at91/Makefile | 1 + drivers/clk/at91/clk-master.c | 2 +- drivers/clk/at91/clk-sam9x60-pll.c | 2 +- drivers/clk/at91/pmc.c | 1 + drivers/clk/at91/sama7d65.c | 1373 ++++++++++++++++++++++++++++ 5 files changed, 1377 insertions(+), 2 deletions(-)create mode 100644
drivers/clk/at91/sama7d65.c
claudiu beznea
maintainerHi, Ryan,
Can you, please, re-submit this series and include also the dt-binding patch, to follow the process highlighted in [1] ?
Thank you,
Claudiu Beznea
[1]
https://lore.kernel.org/lkml/[email protected]/
Quoted 33 lines · On 04.09.2024 18:54, [email protected] wrote:
From: Ryan Wanner <[email protected]>
Hello,
This series adds clock support for the SAMA7D65 SoC. There are also changes to the master clock driver and PLL driver in order to account for the increased amount of clocks being supported in this new SoC.
Trying to account for all the updates happening in this system, this patch set is based off of the most recent updates to at91-next branch.
Changes in v2:
- Correct PLL ID fromPLL_ID_IMGtoPLL_ID_GPUin the description.
- Adjust master clock description to match amount of master clocks 0-9.
- Correct bad spacing and bad alignment.
- Remove double variable definition.
- Add missingkfree()at end of function.
- Reorganize clk and pll driver changes in patch set.Ryan Wanner (3):
clk: at91: clk-master: increase maximum number of clocks
clk: at91: clk-sam9x60-pll: increase maximum amount of plls
clk: at91: sama7d65: add sama7d65 pmc driverdrivers/clk/at91/Makefile | 1 + drivers/clk/at91/clk-master.c | 2 +- drivers/clk/at91/clk-sam9x60-pll.c | 2 +- drivers/clk/at91/pmc.c | 1 + drivers/clk/at91/sama7d65.c | 1373 ++++++++++++++++++++++++++++ 5 files changed, 1377 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/at91/sama7d65.c