x86/resctrl : Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE)

Introduce io_alloc_capable in struct resctrl_cache to detect SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement) feature.

Signed-off-by Babu Moger <[email protected]>

---
v2: Changed sdciae_capable to io_alloc_capable to make it generic feature.
Also moved the io_alloc_capable in struct resctrl_cache.

---
 arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++
 include/linux/resctrl.h            | 4 ++++
 2 files changed, 11 insertions(+)

arch/x86/kernel/cpu/resctrl/core.c +0 -0

index c2450cd52511..39e110033d96 100644

arch/x86/kernel/cpu/resctrl/core.c +3 -0

+
 static void rdt_get_cdp_l3_config(void)
 {
 	rdt_get_cdp_config(RDT_RESOURCE_L3);

@@ -931,6 +936,8 @@ static __init bool get_rdt_alloc_resources(void)
 		rdt_get_cache_alloc_cfg(1, r);
 		if (rdt_cpu_has(X86_FEATURE_CDP_L3))
 			rdt_get_cdp_l3_config();
+		if (rdt_cpu_has(X86_FEATURE_SDCIAE))
+			rdt_get_sdciae_alloc_cfg(r);
 		ret = true;
 	}
 	if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {

include/linux/resctrl.h +0 -0

index d94abba1c716..5837acff7442 100644

include/linux/resctrl.h +1 -0

  */
 struct resctrl_cache {
 	unsigned int	cbm_len;

@@ -136,6 +138,7 @@ struct resctrl_cache {
 	unsigned int	shareable_bits;
 	bool		arch_has_sparse_bitmasks;
 	bool		arch_has_per_cpu_cfg;
+	bool		io_alloc_capable;
 };
 
 /**

Hi Babu,

Quoted 2 lines · Babu Moger

Introduce io_alloc_capable in struct resctrl_cache to detect SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement) feature.

Please distinguish clearly between the resctrl feature ("io_alloc_capable") and the architecture specific feature (SDCIAE) that backs it. This is similar to what you have done for ABMC and makes the work much easier to understand. When the resctrl and arch feature is used interchangeably it becomes confusing.

Quoted 19 lines

Signed-off-by Babu Moger <[email protected]>

---
v2: Changed sdciae_capable to io_alloc_capable to make it generic feature.
Also moved the io_alloc_capable in struct resctrl_cache.

---
 arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++
 include/linux/resctrl.h            | 4 ++++
 2 files changed, 11 insertions(+)

arch/x86/kernel/cpu/resctrl/core.c +0 -0

index c2450cd52511..39e110033d96 100644
@@ -306,6 +306,11 @@ static void rdt_get_cdp_config(int level)
 	rdt_resources_all[level].r_resctrl.cdp_capable = true;
 }
 

arch/x86/kernel/cpu/resctrl/core.c static void rdt_get_cdp_config(int level) · line 312

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/core.c +4 -0

+static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r)
+{
+	r->cache.io_alloc_capable = true;
+}

rdt_get_sdciae_alloc_cfg() looks like one that should have "set" in its name, not "get". This also does not seem architecture specific so "sdciae" should not be in the name. rdt_set_io_alloc_capable()?

Quoted 19 lines

arch/x86/kernel/cpu/resctrl/core.c +3 -0

+
 static void rdt_get_cdp_l3_config(void)
 {
 	rdt_get_cdp_config(RDT_RESOURCE_L3);

@@ -931,6 +936,8 @@ static __init bool get_rdt_alloc_resources(void)
 		rdt_get_cache_alloc_cfg(1, r);
 		if (rdt_cpu_has(X86_FEATURE_CDP_L3))
 			rdt_get_cdp_l3_config();
+		if (rdt_cpu_has(X86_FEATURE_SDCIAE))
+			rdt_get_sdciae_alloc_cfg(r);
 		ret = true;
 	}
 	if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {

include/linux/resctrl.h +0 -0

index d94abba1c716..5837acff7442 100644
@@ -129,6 +129,8 @@ struct rdt_mon_domain {

include/linux/resctrl.h struct rdt_mon_domain { · line 133

Quoted 5 lines

include/linux/resctrl.h +2 -0

  * @arch_has_sparse_bitmasks:	True if a bitmask like f00f is valid.
  * @arch_has_per_cpu_cfg:	True if QOS_CFG register for this cache
  *				level has CPU scope.
+ * @io_alloc_capable:	Smart Data Cache Injection Allocation Enforcement
+ *			capable (SDCIAE).

Please remove arch specific text here. For example, "True if portion of the L3 cache can be allocated for I/O traffic."

Quoted 11 lines

include/linux/resctrl.h +1 -0

  */
 struct resctrl_cache {
 	unsigned int	cbm_len;

@@ -136,6 +138,7 @@ struct resctrl_cache {
 	unsigned int	shareable_bits;
 	bool		arch_has_sparse_bitmasks;
 	bool		arch_has_per_cpu_cfg;
+	bool		io_alloc_capable;
 };
 

include/linux/resctrl.h enum resctrl_scope { · line 211

Quoted 9 lines

include/linux/resctrl.h +1 -0

 /**

@@ -202,6 +205,7 @@ enum resctrl_scope {
  * @evt_list:		List of monitoring events
  * @fflags:		flags to choose base and info files
  * @cdp_capable:	Is the CDP feature available on this resource
+ * @sdciae_capable:	Is SDCIAE feature available on this resource
  */
 struct rdt_resource {
 	int			rid;

Leftover from previous version?

Introduce architecture-specific2yy handlers to manage the detection and

enabling/disabling of this feature.

SDCIAE feature can be enabled by setting bit 1 in MSR L3_QOS_EXT_CFG. When the state of SDCIAE is modified, the updated value must be applied across all logical processors within the QOS Domain. By default, the io_alloc feature is turned off.

The SDCIAE feature details are available in APM listed below [1].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE)

Link https://bugzilla.kernel.org/show_bug.cgi?id=206537

Signed-off-by Babu Moger <[email protected]>

---
v2: Renamed the functions to simplify the code.
Renamed sdciae_capable to io_alloc_capable.

Changed the name of few arch functions similar to ABMC series. resctrl_arch_get_io_alloc_enabled() resctrl_arch_io_alloc_enable()

---
 arch/x86/include/asm/msr-index.h       |  1 +
 arch/x86/kernel/cpu/resctrl/internal.h | 10 ++++++++
 arch/x86/kernel/cpu/resctrl/rdtgroup.c | 34 ++++++++++++++++++++++++++
 include/linux/resctrl.h                |  9 +++++++
 4 files changed, 54 insertions(+)

arch/x86/include/asm/msr-index.h +1 -0

index 3f3e2bc99162..360c52a62da9 100644
@@ -1196,6 +1196,7 @@
 /* - AMD: */
 #define MSR_IA32_MBA_BW_BASE		0xc0000200
 #define MSR_IA32_SMBA_BW_BASE		0xc0000280
+#define MSR_IA32_L3_QOS_EXT_CFG		0xc00003ff
 #define MSR_IA32_EVT_CFG_BASE		0xc0000400
 
 /* AMD-V MSRs */

arch/x86/kernel/cpu/resctrl/internal.h +5 -0

index 20c898f09b7e..dff3354c2282 100644
@@ -56,6 +56,9 @@
 /* Max event bits supported */
 #define MAX_EVT_CONFIG_BITS		GENMASK(6, 0)
 
+/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
+#define SDCIAE_ENABLE_BIT		1
+
 /**
  * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those that
  *			        aren't marked nohz_full

@@ -479,6 +482,7 @@ struct rdt_parse_data {
  * @mbm_cfg_mask:	Bandwidth sources that can be tracked when Bandwidth
  *			Monitoring Event Configuration (BMEC) is supported.
  * @cdp_enabled:	CDP state of this resource
+ * @sdciae_enabled:	SDCIAE feature is enabled
  *
  * Members of this structure are either private to the architecture
  * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.

@@ -493,6 +497,7 @@ struct rdt_hw_resource {
 	unsigned int		mbm_width;
 	unsigned int		mbm_cfg_mask;
 	bool			cdp_enabled;
+	bool			sdciae_enabled;
 };
 
 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)

arch/x86/kernel/cpu/resctrl/internal.h +4 -0

+{
+	return rdt_resources_all[l].sdciae_enabled;
+}
+
 /*
  * To return the common struct rdt_resource, which is contained in struct
  * rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource.

arch/x86/kernel/cpu/resctrl/rdtgroup.c +9 -0

index 6419e04d8a7b..398f241b65d5 100644
@@ -1798,6 +1798,40 @@ static ssize_t mbm_local_bytes_config_write(struct kernfs_open_file *of,
 	return ret ?: nbytes;
 }
 
+static void resctrl_sdciae_set_one_amd(void *arg)
+{
+	bool *enable = arg;
+
+	if (*enable)
+		msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+	else
+		msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+}

arch/x86/kernel/cpu/resctrl/rdtgroup.c +15 -0

+}
+
+int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
+{
+	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
+
+	if (hw_res->r_resctrl.cache.io_alloc_capable &&
+	    hw_res->sdciae_enabled != enable) {
+		_resctrl_io_alloc_enable(r, enable);
+		hw_res->sdciae_enabled = enable;
+	}
+
+	return 0;
+}
+
 /* rdtgroup information files for one cache resource. */
 static struct rftype res_common_files[] = {
 	{

include/linux/resctrl.h +2 -0

index 5837acff7442..8c66aeac4768 100644
@@ -344,6 +344,15 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d,
  */
 void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d);
 
+/**
+ * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature.

Hi Babu,

Quoted 1 line · Babu Moger

Introduce architecture-specific2yy handlers to manage the detection and

"architecture-specific2yy"?

Quoted 2 lines

enabling/disabling of this feature.

Please add more to the context. It just jumps in with a "this feature" without any introduction.

Quoted 72 lines

SDCIAE feature can be enabled by setting bit 1 in MSR L3_QOS_EXT_CFG. When the state of SDCIAE is modified, the updated value must be applied across all logical processors within the QOS Domain. By default, the io_alloc feature is turned off.

The SDCIAE feature details are available in APM listed below [1].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE)

Link https://bugzilla.kernel.org/show_bug.cgi?id=206537

Signed-off-by Babu Moger <[email protected]>

---
v2: Renamed the functions to simplify the code.
Renamed sdciae_capable to io_alloc_capable.

Changed the name of few arch functions similar to ABMC series. resctrl_arch_get_io_alloc_enabled() resctrl_arch_io_alloc_enable()

---
 arch/x86/include/asm/msr-index.h       |  1 +
 arch/x86/kernel/cpu/resctrl/internal.h | 10 ++++++++
 arch/x86/kernel/cpu/resctrl/rdtgroup.c | 34 ++++++++++++++++++++++++++
 include/linux/resctrl.h                |  9 +++++++
 4 files changed, 54 insertions(+)

arch/x86/include/asm/msr-index.h +1 -0

index 3f3e2bc99162..360c52a62da9 100644
@@ -1196,6 +1196,7 @@
 /* - AMD: */
 #define MSR_IA32_MBA_BW_BASE		0xc0000200
 #define MSR_IA32_SMBA_BW_BASE		0xc0000280
+#define MSR_IA32_L3_QOS_EXT_CFG		0xc00003ff
 #define MSR_IA32_EVT_CFG_BASE		0xc0000400
 
 /* AMD-V MSRs */

arch/x86/kernel/cpu/resctrl/internal.h +5 -0

index 20c898f09b7e..dff3354c2282 100644
@@ -56,6 +56,9 @@
 /* Max event bits supported */
 #define MAX_EVT_CONFIG_BITS		GENMASK(6, 0)
 
+/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */
+#define SDCIAE_ENABLE_BIT		1
+
 /**
  * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those that
  *			        aren't marked nohz_full

@@ -479,6 +482,7 @@ struct rdt_parse_data {
  * @mbm_cfg_mask:	Bandwidth sources that can be tracked when Bandwidth
  *			Monitoring Event Configuration (BMEC) is supported.
  * @cdp_enabled:	CDP state of this resource
+ * @sdciae_enabled:	SDCIAE feature is enabled
  *
  * Members of this structure are either private to the architecture
  * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g.

@@ -493,6 +497,7 @@ struct rdt_hw_resource {
 	unsigned int		mbm_width;
 	unsigned int		mbm_cfg_mask;
 	bool			cdp_enabled;
+	bool			sdciae_enabled;
 };
 
 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r)

@@ -539,6 +544,11 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable);
 

arch/x86/kernel/cpu/resctrl/internal.h int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable); · line 547

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/internal.h +1 -0

 void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain *d);
 
+static inline bool resctrl_arch_get_io_alloc_enabled(enum resctrl_res_level l)

The custom is to pass a pointer to the resource when interacting with it. Why is it needed to pass the ID here?

Quoted 31 lines

arch/x86/kernel/cpu/resctrl/internal.h +4 -0

+{
+	return rdt_resources_all[l].sdciae_enabled;
+}
+
 /*
  * To return the common struct rdt_resource, which is contained in struct
  * rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource.

arch/x86/kernel/cpu/resctrl/rdtgroup.c +15 -0

index 6419e04d8a7b..398f241b65d5 100644
@@ -1798,6 +1798,40 @@ static ssize_t mbm_local_bytes_config_write(struct kernfs_open_file *of,
 	return ret ?: nbytes;
 }
 
+static void resctrl_sdciae_set_one_amd(void *arg)
+{
+	bool *enable = arg;
+
+	if (*enable)
+		msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+	else
+		msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT);
+}
+
+static int _resctrl_io_alloc_enable(struct rdt_resource *r, bool enable)
+{
+	struct rdt_ctrl_domain *d;
+
+	/* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains*/

arch/x86/kernel/cpu/resctrl/rdtgroup.c static ssize_t mbm_local_bytes_config_write(struct kernfs_open_file *of, · line 1819

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +4 -0

+	list_for_each_entry(d, &r->ctrl_domains, hdr.list)
+		on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1);
+
+	return 0;

Same comment as in V1 about this arch specific handler always returning 0 and can thus just return void. Also the name should not reflect that it is resctrl code. One option could be _resctrl_arch_io_alloc_enable().

Quoted 29 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +15 -0

+}
+
+int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
+{
+	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
+
+	if (hw_res->r_resctrl.cache.io_alloc_capable &&
+	    hw_res->sdciae_enabled != enable) {
+		_resctrl_io_alloc_enable(r, enable);
+		hw_res->sdciae_enabled = enable;
+	}
+
+	return 0;
+}
+
 /* rdtgroup information files for one cache resource. */
 static struct rftype res_common_files[] = {
 	{

include/linux/resctrl.h +2 -0

index 5837acff7442..8c66aeac4768 100644
@@ -344,6 +344,15 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d,
  */
 void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d);
 
+/**
+ * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature.

include/linux/resctrl.h void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d, · line 358

Quoted 10 lines

include/linux/resctrl.h +7 -0

+ * @r:		The resctrl resource.
+ * @enable:	Enable (1) or disable (0) the feature
+ *
+ * This can be called from any CPU.
+ */
+int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable);
+
 extern unsigned int resctrl_rmid_realloc_threshold;
 extern unsigned int resctrl_rmid_realloc_limit;
 

Reinette

arch/x86/kernel/cpu/resctrl/core.c static void rdt_get_cdp_config(int level) · line 314

Quoted 6 lines

static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r)

 {
      r->cache.io_alloc_capable = true;

arch/x86/kernel/cpu/resctrl/core.c +2 -0

+     resctrl_file_fflags_init("io_alloc",
+                              RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE);
 }

I think those fflags will make this file appear in all info cache directories (L2 and L3).

Presumably you only want this file (and "io_alloc_cbm" added by next patch) in the L3 directory.

Quoted 10 lines

arch/x86/kernel/cpu/resctrl/core.c static void rdt_get_cdp_config(int level) · line 314

Quoted 6 lines

static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r)

 {
      r->cache.io_alloc_capable = true;

arch/x86/kernel/cpu/resctrl/core.c +2 -0

+     resctrl_file_fflags_init("io_alloc",
+                              RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE);
 }

I think those fflags will make this file appear in all info cache directories (L2 and L3).

Quoted 2 lines

Presumably you only want this file (and "io_alloc_cbm" added by next patch) in the L3 directory.

Could you please elaborate why this file should only be in L3 directory? I do not see the problem with having it in L2. "io_alloc" communicates to user space if this I/O alloc feature is supported and does so with its content as opposed to its existence. For L2 it will indicate that the feature is not supported.

The io_alloc feature in resctrl enables system software to configure the portion of the L3 cache allocated for I/O traffic.

Smart Data Cache Injection (SDCI) is a mechanism that allows direct insertion of data from I/O devices into the L3 cache. By caching I/O data directly in the L3 cache, instead of writing it to DRAM first, SDCI reduces DRAM bandwidth usage and lowers latency for the processor consuming the I/O data.

When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1.MAX_COS. For example, if MAX_COS=15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register.

Introduce interface to enable/disable "io_alloc" feature on user input.

Signed-off-by Babu Moger <[email protected]>

---
v2: Renamed the feature to "io_alloc".
Added generic texts for the feature in commit log and resctrl.rst doc. Added resctrl_io_alloc_init_cat() to initialize io_alloc to default values when enabled.
Fixed io_alloc show functinality to display only on L3 resource.

---
 Documentation/arch/x86/resctrl.rst     |  27 ++++++
 arch/x86/kernel/cpu/resctrl/core.c     |   2 +
 arch/x86/kernel/cpu/resctrl/rdtgroup.c | 118 +++++++++++++++++++++++++
 3 files changed, 147 insertions(+)

Documentation/arch/x86/resctrl.rst +4 -0

index 6768fc1fad16..52679175ee14 100644
@@ -135,6 +135,33 @@ related to allocation:
 			"1":
 			      Non-contiguous 1s value in CBM is supported.
 
+"io_alloc":
+		The "io_alloc" feature in resctrl enables system software to
+		configure the portion of the L3 cache allocated for I/O traffic.
+

Documentation/arch/x86/resctrl.rst +1 -0

+
 Memory bandwidth(MB) subdirectory contains the following files
 with respect to allocation:
 

arch/x86/kernel/cpu/resctrl/core.c +2 -0

index 39e110033d96..066a7997eaf1 100644
@@ -309,6 +309,8 @@ static void rdt_get_cdp_config(int level)
 static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r)
 {
 	r->cache.io_alloc_capable = true;
+	resctrl_file_fflags_init("io_alloc",
+				 RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE);
 }
 
 static void rdt_get_cdp_l3_config(void)

arch/x86/kernel/cpu/resctrl/rdtgroup.c +1 -0

index 398f241b65d5..e30731ce9335 100644
@@ -62,6 +62,7 @@ static char last_cmd_status_buf[512];
 
 static int rdtgroup_setup_root(struct rdt_fs_context *ctx);
 static void rdtgroup_destroy_root(void);
+static int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid);
 
 struct dentry *debugfs_resctrl;
 

arch/x86/kernel/cpu/resctrl/rdtgroup.c +6 -0

+ * Get the max CLOSID number
+ */
+static u32 resctrl_io_alloc_closid_get(struct rdt_resource *r)
+{
+	return resctrl_arch_get_num_closid(r) - 1;
+}

arch/x86/kernel/cpu/resctrl/rdtgroup.c +3 -0

+
 /**
  * closid_allocated - test if provided closid is in use
  * @closid: closid to be tested

@@ -1832,6 +1852,97 @@ int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
 	return 0;
 }
 
+static int resctrl_io_alloc_show(struct kernfs_open_file *of,
+				 struct seq_file *seq, void *v)

arch/x86/kernel/cpu/resctrl/rdtgroup.c +36 -0

+			ret = rdtgroup_init_cat(s, closid);
+			if (ret < 0)
+				goto out_init_cat;
+
+			ret = resctrl_arch_update_domains(r, closid);
+			if (ret < 0)
+				goto out_init_cat;
+		}
+	}
+
+out_init_cat:
+	if (ret)
+		rdt_last_cmd_puts("Failed to initialize io_alloc allocations\n");
+
+	rdt_staged_configs_clear();
+	return ret;
+}
+
+static ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *buf,
+				      size_t nbytes, loff_t off)
+{
+	struct resctrl_schema *s = of->kn->parent->priv;
+	struct rdt_resource *r = s->res;
+	u32 io_alloc_closid;
+	bool enable;
+	int ret;
+
+	if (!r->cache.io_alloc_capable)
+		return -EINVAL;
+
+	ret = kstrtobool(buf, &enable);
+	if (ret)
+		return ret;
+
+	cpus_read_lock();
+	mutex_lock(&rdtgroup_mutex);

arch/x86/kernel/cpu/resctrl/rdtgroup.c +17 -0

+				goto out_io_alloc;
+			}
+
+		} else {
+			closid_free(io_alloc_closid);
+		}
+
+		ret = resctrl_arch_io_alloc_enable(r, enable);
+	}
+
+out_io_alloc:
+	mutex_unlock(&rdtgroup_mutex);
+	cpus_read_unlock();
+
+	return ret ?: nbytes;
+}
+
 /* rdtgroup information files for one cache resource. */
 static struct rftype res_common_files[] = {
 	{

@@ -1984,6 +2095,13 @@ static struct rftype res_common_files[] = {
 		.seq_show	= rdtgroup_schemata_show,
 		.fflags		= RFTYPE_CTRL_BASE,
 	},

Hi Babu,

Quoted 3 lines · Babu Moger

The io_alloc feature in resctrl enables system software to configure the portion of the L3 cache allocated for I/O traffic.

Above is about resctrl feature.

Quoted 11 lines

Smart Data Cache Injection (SDCI) is a mechanism that allows direct insertion of data from I/O devices into the L3 cache. By caching I/O data directly in the L3 cache, instead of writing it to DRAM first, SDCI reduces DRAM bandwidth usage and lowers latency for the processor consuming the I/O data.

When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1.MAX_COS. For example, if MAX_COS=15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register.

Above is about AMD feature.

Quoted 2 lines

Introduce interface to enable/disable "io_alloc" feature on user input.

Back to resctrl feature.

Please do not jump from resctrl to AMD feature in a way that makes it seem that they are interchangeable. To help with this you could use similar style as in ABMC where the text flows like:

<resctrl feature description>.

On AMD <resctrl feature> is backed by <AMD feature> that <AMD feature details>.

Quoted 32 lines

Signed-off-by Babu Moger <[email protected]>

---
v2: Renamed the feature to "io_alloc".
Added generic texts for the feature in commit log and resctrl.rst doc. Added resctrl_io_alloc_init_cat() to initialize io_alloc to default values when enabled.
Fixed io_alloc show functinality to display only on L3 resource.

---
 Documentation/arch/x86/resctrl.rst     |  27 ++++++
 arch/x86/kernel/cpu/resctrl/core.c     |   2 +
 arch/x86/kernel/cpu/resctrl/rdtgroup.c | 118 +++++++++++++++++++++++++
 3 files changed, 147 insertions(+)

Documentation/arch/x86/resctrl.rst +9 -0

index 6768fc1fad16..52679175ee14 100644
@@ -135,6 +135,33 @@ related to allocation:
 			"1":
 			      Non-contiguous 1s value in CBM is supported.
 
+"io_alloc":
+		The "io_alloc" feature in resctrl enables system software to
+		configure the portion of the L3 cache allocated for I/O traffic.
+
+		Smart Data Cache Injection (SDCI) is a mechanism that allows
+		direct insertion of data from I/O devices into the L3 cache.
+		By caching I/O data directly in the L3 cache, instead of writing
+		it to DRAM first, SDCI reduces DRAM bandwidth usage and lowers
+		latency for the processor consuming the I/O data.

Documentation/arch/x86/resctrl.rst related to allocation: · line 151

Quoted 5 lines

Documentation/arch/x86/resctrl.rst +5 -0

+
+		When enabled the feature forces all SDCI lines to be placed
+		into the L3 cache partitions identified by the highest-supported
+		CLOSID (num_closids-1). This CLOSID will not be available to the
+		resctrl group.

Same comment as V1. The above two paragraphs cannot be guaranteed to be specific to the "io_alloc" feature ... it is only specific to SDCIAE.

Quoted 12 lines

Documentation/arch/x86/resctrl.rst +11 -0

+
+			"0":
+			    I/O device L3 cache control is not enabled.
+			"1":
+			    I/O device L3 cache control is enabled, allowing users
+			    to manage the portions of the L3 cache allocated for
+			    the I/O device.
+
+		Feature can be enabled/disabled by writing to the interface.
+		Example::
+

Documentation/arch/x86/resctrl.rst related to allocation: · line 163

Quoted 1 line

Documentation/arch/x86/resctrl.rst +1 -0

+			# echo 1 > /sys/fs/resctrl/info/L3/io_alloc

Similar to comment of V1 there is no information about what user can expect when enabling this. For example, if this fails then one cause may be that a resource group already owns that CLOSID and that removing that resource group would make it possible to enable this feature. Even so, user space does not know about CLOSIDs, only resource groups, making it difficult to correct without more help.

Quoted 30 lines

Documentation/arch/x86/resctrl.rst +1 -0

+
 Memory bandwidth(MB) subdirectory contains the following files
 with respect to allocation:
 

arch/x86/kernel/cpu/resctrl/core.c +2 -0

index 39e110033d96..066a7997eaf1 100644
@@ -309,6 +309,8 @@ static void rdt_get_cdp_config(int level)
 static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r)
 {
 	r->cache.io_alloc_capable = true;
+	resctrl_file_fflags_init("io_alloc",
+				 RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE);
 }
 
 static void rdt_get_cdp_l3_config(void)

arch/x86/kernel/cpu/resctrl/rdtgroup.c +1 -0

index 398f241b65d5..e30731ce9335 100644
@@ -62,6 +62,7 @@ static char last_cmd_status_buf[512];
 
 static int rdtgroup_setup_root(struct rdt_fs_context *ctx);
 static void rdtgroup_destroy_root(void);
+static int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid);
 
 struct dentry *debugfs_resctrl;
 

arch/x86/kernel/cpu/resctrl/rdtgroup.c void closid_free(int closid) · line 185

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +2 -0

@@ -180,6 +181,25 @@ void closid_free(int closid)
 	__set_bit(closid, &closid_free_map);
 }
 
+/*
+ * io_alloc (SDCIAE) feature uses max CLOSID to route the SDCI traffic.

Please do not use io_alloc and SDCIAE interchangeably.

Quoted 15 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +14 -0

+ * Get the max CLOSID number
+ */
+static u32 resctrl_io_alloc_closid_get(struct rdt_resource *r)
+{
+	return resctrl_arch_get_num_closid(r) - 1;
+}
+
+static int resctrl_io_alloc_closid_alloc(struct rdt_resource *r)
+{
+	u32 io_alloc_closid = resctrl_io_alloc_closid_get(r);
+
+	if (__test_and_clear_bit(io_alloc_closid, &closid_free_map))
+		return io_alloc_closid;
+	else

arch/x86/kernel/cpu/resctrl/rdtgroup.c void closid_free(int closid) · line 201

Quoted 2 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +2 -0

+		return -ENOSPC;
+}

This does not look right. The way resctrl manages CLOSID is to use the *minimum* of all CLOSID supported across all resources. It may thus be possible for the L3 resource to support more CLOSID than other resources causing the closid_free_map to be sized to a value smaller than the L3 max CLOSID. The bit being tested/cleared here may thus exceed what is in the bitmap.

Also, during V1 we discussed how CDP was not handled and I am not able to see where/if it is handled in this version.

Quoted 9 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +1 -0

+
 /**
  * closid_allocated - test if provided closid is in use
  * @closid: closid to be tested

@@ -1832,6 +1852,97 @@ int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable)
 	return 0;
 }
 

arch/x86/kernel/cpu/resctrl/rdtgroup.c int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) · line 1866

Quoted 12 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +12 -0

+static int resctrl_io_alloc_show(struct kernfs_open_file *of,
+				 struct seq_file *seq, void *v)
+{
+	struct resctrl_schema *s = of->kn->parent->priv;
+	struct rdt_resource *r = s->res;
+
+	seq_printf(seq, "%x\n", resctrl_arch_get_io_alloc_enabled(r->rid));
+	return 0;
+}
+
+/*
+ * Initialize the io_alloc feature default when enabled

It is not clear what this comment describes.

arch/x86/kernel/cpu/resctrl/rdtgroup.c int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) · line 1877

Quoted 12 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +11 -0

+ */
+static int resctrl_io_alloc_init_cat(struct rdt_resource *r, u32 closid)
+{
+	struct resctrl_schema *s;
+	int ret = 0;
+
+	rdt_staged_configs_clear();
+
+	list_for_each_entry(s, &resctrl_schema_all, list) {
+		r = s->res;
+		if (r->rid == RDT_RESOURCE_L3) {

It looks like the function ignores the resource provided to it via function parameter and instead uses internal hardcode of which resource to act on?

Quoted 44 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +43 -0

+			ret = rdtgroup_init_cat(s, closid);
+			if (ret < 0)
+				goto out_init_cat;
+
+			ret = resctrl_arch_update_domains(r, closid);
+			if (ret < 0)
+				goto out_init_cat;
+		}
+	}
+
+out_init_cat:
+	if (ret)
+		rdt_last_cmd_puts("Failed to initialize io_alloc allocations\n");
+
+	rdt_staged_configs_clear();
+	return ret;
+}
+
+static ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *buf,
+				      size_t nbytes, loff_t off)
+{
+	struct resctrl_schema *s = of->kn->parent->priv;
+	struct rdt_resource *r = s->res;
+	u32 io_alloc_closid;
+	bool enable;
+	int ret;
+
+	if (!r->cache.io_alloc_capable)
+		return -EINVAL;
+
+	ret = kstrtobool(buf, &enable);
+	if (ret)
+		return ret;
+
+	cpus_read_lock();
+	mutex_lock(&rdtgroup_mutex);
+
+	rdt_last_cmd_clear();
+
+	io_alloc_closid = resctrl_io_alloc_closid_get(r);
+
+	if (resctrl_arch_get_io_alloc_enabled(r->rid) != enable) {
+		if (enable) {

arch/x86/kernel/cpu/resctrl/rdtgroup.c int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) · line 1923

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +3 -0

+			ret = resctrl_io_alloc_closid_alloc(r);
+			if (ret < 0) {
+				rdt_last_cmd_puts("io_alloc CLOSID is not available\n");

Can this be more useful to the user? The user does not know what the CLOSID is nor what can be remedied to fix this. What if the message instead contains the name of the resource group to which the CLOSID is assigned so that user knows which resource group could be removed to be able to enable io_alloc?

arch/x86/kernel/cpu/resctrl/rdtgroup.c int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) · line 1928

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +5 -0

+				goto out_io_alloc;
+			}
+			ret = resctrl_io_alloc_init_cat(r, io_alloc_closid);
+			if (ret) {
+				closid_free(io_alloc_closid);

Could you please make a resctrl_io_alloc_closid_free() that is symmetrical to resctrl_io_alloc_closid_alloc()?

Quoted 25 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +17 -0

+				goto out_io_alloc;
+			}
+
+		} else {
+			closid_free(io_alloc_closid);
+		}
+
+		ret = resctrl_arch_io_alloc_enable(r, enable);
+	}
+
+out_io_alloc:
+	mutex_unlock(&rdtgroup_mutex);
+	cpus_read_unlock();
+
+	return ret ?: nbytes;
+}
+
 /* rdtgroup information files for one cache resource. */
 static struct rftype res_common_files[] = {
 	{

@@ -1984,6 +2095,13 @@ static struct rftype res_common_files[] = {
 		.seq_show	= rdtgroup_schemata_show,
 		.fflags		= RFTYPE_CTRL_BASE,
 	},

arch/x86/kernel/cpu/resctrl/rdtgroup.c static struct rftype res_common_files[] = { · line 2107

Quoted 10 lines

arch/x86/kernel/cpu/resctrl/rdtgroup.c +7 -0

+	{
+		.name		= "io_alloc",
+		.mode		= 0644,
+		.kf_ops		= &rdtgroup_kf_single_ops,
+		.seq_show	= resctrl_io_alloc_show,
+		.write		= resctrl_io_alloc_write,
+	},
 	{
 		.name		= "mba_MBps_event",
 		.mode		= 0644,

Reinette

I don't have an AMD system, so I added a couple of hacks to the code to pretend I did. My hacks might have missed something, so the below test may not fail for you.

My test:

# echo 1 > info/L3/io_alloc
# cat info/L3/bit_usage

This gave me a console splat starting with:

[  163.801078] invalid mode for closid 14

That happened because in rdt_bit_usage_show()

                for (i = 0; i < closids_supported(); i++) {
                        if (!closid_allocated(i))
                                continue;
                        ctrl_val = resctrl_arch_get_config(r, dom, i,
                                                           s->conf_type);
                        mode = rdtgroup_mode_by_closid(i);

CLOSID 14 is my highest. It's supported, and allocated.

rdtgroup_mode_by_closid() searches rdt_all_groups to find one using CLOSID 14, but there isn't one. So it returns RDT_NUM_MODES

Maybe RDT_NUM_MODES isn't invalid in the switch() Looks like it should be same action as RDT_MODE_SHAREABLE?