clk: at91: add support for parent_data and
Subsystems (2)
v2 cover clk: at91: add support for parent_data and
From: Ryan Wanner <[email protected]>
This series adds support for parent data and parent _hw on the at91 clock drivers. This also updates all the SoC specific clock drivers to use this format as well.
This is a continuation of the V1 of this series here [1].
This has been tested on the SAMA5* SoCs, the sam9x* SoCs, and the SAMA7* SoCs.
Changes v1 -> V2:
- Remove all the small sama7g54 SoC driver changes and put them in their own patch.
- Add the SAMA7D65 and the SAM9X75 to this update.
- Add a patch to move all common used macros into the pmc.h file.
- Update changes from v6.6 to v6.16.
- Remove patches that where style fixes and include those in the update.
1) https://lore.kernel.org/all/[email protected]/
Claudiu Beznea (29):
clk: at91: pmc: add macros for clk_parent_data
clk: at91: clk-sam9x60-pll: use clk_parent_data
clk: at91: clk-peripheral: switch to clk_parent_data
clk: at91: clk-main: switch to clk parent data
clk: at91: clk-utmi: use clk_parent_data
clk: at91: clk-master: use clk_parent_data
clk: at91: clk-programmable: use clk_parent_data
clk: at91: clk-generated: use clk_parent_data
clk: at91: clk-usb: add support for clk_parent_data
clk: at91: clk-system: use clk_parent_data
clk: at91: clk-pll: add support for parent_hw
clk: at91: clk-audio-pll: add support for parent_hw
clk: at91: clk-plldiv: add support for parent_hw
clk: at91: clk-h32mx: add support for parent_hw
clk: at91: clk-i2s-mux: add support for parent_hw
clk: at91: clk-smd: add support for clk_parent_data
clk: at91: clk-slow: add support for parent_hw
clk: at91: dt-compat: switch to parent_hw and parent_data
clk: at91: sam9x60: switch to parent_hw and parent_data
clk: at91: sama5d2: switch to parent_hw and parent_data
clk: at91: sama5d3: switch to parent_hw and parent_data
clk: at91: sama5d4: switch to parent_hw and parent_data
clk: at91: at91sam9x5: switch to parent_hw and parent_data
clk: at91: at91rm9200: switch to parent_hw and parent_data
clk: at91: at91sam9260: switch to parent_hw and parent_data
clk: at91: at91sam9g45: switch to parent_hw and parent_data
clk: at91: at91sam9n12: switch to parent_hw and parent_data
clk: at91: at91sam9rl: switch to clk_parent_data
clk: at91: sama7g5: switch to clk_parent_data
Ryan Wanner (3):
clk: at91: pmc: Move macro to header file
clk: at91: sam9x75: switch to parent_hw and parent_data
clk: at91: sama7d65: switch to clk_parent_data
drivers/clk/at91/at91rm9200.c | 95 ++++---- drivers/clk/at91/at91sam9260.c | 136 ++++++------ drivers/clk/at91/at91sam9g45.c | 89 ++++---- drivers/clk/at91/at91sam9n12.c | 106 ++++----- drivers/clk/at91/at91sam9rl.c | 63 +++--- drivers/clk/at91/at91sam9x5.c | 125 ++++++----- drivers/clk/at91/clk-audio-pll.c | 28 ++- drivers/clk/at91/clk-generated.c | 8 +- drivers/clk/at91/clk-h32mx.c | 11 +- drivers/clk/at91/clk-i2s-mux.c | 6 +- drivers/clk/at91/clk-main.c | 16 +- drivers/clk/at91/clk-master.c | 24 +- drivers/clk/at91/clk-peripheral.c | 16 +- drivers/clk/at91/clk-pll.c | 9 +- drivers/clk/at91/clk-plldiv.c | 11 +- drivers/clk/at91/clk-programmable.c | 8 +- drivers/clk/at91/clk-sam9x60-pll.c | 14 +- drivers/clk/at91/clk-slow.c | 8 +- drivers/clk/at91/clk-smd.c | 10 +- drivers/clk/at91/clk-system.c | 8 +- drivers/clk/at91/clk-usb.c | 41 ++-- drivers/clk/at91/clk-utmi.c | 16 +- drivers/clk/at91/dt-compat.c | 80 +++++-- drivers/clk/at91/pmc.h | 66 +++--- drivers/clk/at91/sam9x60.c | 117 +++++----- drivers/clk/at91/sam9x7.c | 330 ++++++++++++++++------------ drivers/clk/at91/sama5d2.c | 168 +++++++------- drivers/clk/at91/sama5d3.c | 122 +++++----- drivers/clk/at91/sama5d4.c | 129 +++++------ drivers/clk/at91/sama7d65.c | 116 +++++----- drivers/clk/at91/sama7g5.c | 111 +++++----- 31 files changed, 1110 insertions(+), 977 deletions(-)
Signature · 1 line
2.43.0
PATCH v2 1/32 clk: at91: pmc: add macros for clk_parent_data
From: Claudiu Beznea <[email protected]>
Add helpers to set parent_data objects in platform specific drivers.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: enclose complex macro with parentheses.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/pmc.h | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/clk/at91/pmc.h +6 -0
@@ -15,6 +15,12 @@#include <dt-bindings/clock/at91.h> +#define AT91_CLK_PD_NAME (n, i) ((struct clk_parent_data){ \ + .hw = NULL, .name = (n), .fw_name = (n), .index = (i), \ +}) + +#define AT91_CLK_PD_HW (h) ((struct clk_parent_data){ .hw = (h) }) +extern spinlock_t pmc_pcr_lock;struct pmc_data {
Signature · 1 line
2.43.0
PATCH v2 2/32 clk: at91: pmc: Move macro to header file
In reply to [email protected]From: Ryan Wanner <[email protected]>
Move this macro to the header file as it is used by more than one driver file.
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/pmc.h | 3 +++ drivers/clk/at91/sama7d65.c | 3 --- drivers/clk/at91/sama7g5.c | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-)
drivers/clk/at91/pmc.h +3 -0
@@ -21,6 +21,9 @@#define AT91_CLK_PD_HW (h) ((struct clk_parent_data){ .hw = (h) }) +/* Used to create an array entry identifying a PLL by its components. */ +#define PLL_IDS_TO_ARR_ENTRY (_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp} +extern spinlock_t pmc_pcr_lock;struct pmc_data {
drivers/clk/at91/sama7d65.c +0 -3
@@ -428,9 +428,6 @@ static struct sama7d65_pll { }, }; -/* Used to create an array entry identifying a PLL by its components. */ -#define PLL_IDS_TO_ARR_ENTRY (_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp} -/* * Master clock (MCK[0..9]) description * @n: clock name
drivers/clk/at91/sama7g5.c +0 -3
@@ -341,9 +341,6 @@ static struct sama7g5_pll { }, }; -/* Used to create an array entry identifying a PLL by its components. */ -#define PLL_IDS_TO_ARR_ENTRY (_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp} -/* * Master clock (MCK[1..4]) description * @n: clock name
Signature · 1 line
2.43.0
PATCH v2 3/32 clk: at91: clk-sam9x60-pll: use clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. As clk-sam9x60-pll need to know parent's rate at initialization we pass it now from SoC specific drivers. This will lead in the end at removing __clk_get_hw() in SoC specific drivers (that will be solved by subsequent commits).
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific driver changes, those will be added in subsequent commits.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++--------- drivers/clk/at91/pmc.h | 5 +++-- 2 files changed, 8 insertions(+), 11 deletions(-)
drivers/clk/at91/clk-sam9x60-pll.c +5 -9
@@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = {struct clk_hw *__init sam9x60_clk_register_frac_pll (struct regmap *regmap,spinlock_t *lock, -const char *name,const char *parent_name, -struct clk_hw *parent_hw,u8 id, +const char *name,const struct clk_parent_data *parent_data, +unsigned long parent_rate,u8 id,const struct clk_pll_characteristics *characteristics,const struct clk_pll_layout *layout,u32 flags) {struct sam9x60_frac *frac;struct clk_hw *hw;struct clk_init_data init = {}; -unsigned long parent_rate, irqflags; +unsigned long irqflags;unsigned int val;int ret; -if (id >PLL_MAX_ID || !lock || !parent_hw) +if (id >PLL_MAX_ID || !lock || !parent_data)return ERR_PTR (-EINVAL ); frac =kzalloc (sizeof (*frac),GFP_KERNEL );
@@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,return ERR_PTR (-ENOMEM ); init.name = name; -if (parent_name) - init.parent_names = &parent_name; -else - init.parent_hws = (const struct clk_hw **)&parent_hw; + init.parent_data = (const struct clk_parent_data *)parent_data; init.num_parents =1 ;if (flags &CLK_SET_RATE_GATE ) init.ops = &sam9x60_frac_pll_ops;
@@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,* its rate leading to enabling this PLL with unsupported * rate. This will lead to PLL not being locked at all. */ - parent_rate =clk_hw_get_rate (parent_hw);if (!parent_rate) { hw =ERR_PTR (-EINVAL ); goto free;
drivers/clk/at91/pmc.h +3 -2
@@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,struct clk_hw *__init sam9x60_clk_register_frac_pll (struct regmap *regmap,spinlock_t *lock, -const char *name,const char *parent_name, -struct clk_hw *parent_hw,u8 id, +const char *name, +const struct clk_parent_data *parent_data, +unsigned long parent_rate,u8 id,const struct clk_pll_characteristics *characteristics,const struct clk_pll_layout *layout,u32 flags);
Signature · 1 line
2.43.0
Claudiu Beznea
maintainerRe: [PATCH v2 03/32] clk: at91: clk-sam9x60-pll: use clk_parent_data
Hi, Ryan,
Quoted 10 lines · On 24.06.2025 18:08, [email protected] wrote:
From: Claudiu Beznea <[email protected]>
Use struct
clk_parent_datainstead of structparent_hwas this leads to less usage of__clk_get_hw()in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers fromparent_namesto modernclk_parent_datastructures. As clk-sam9x60-pll need to know parent's rate at initialization we pass it now from SoC specific drivers. This will lead in the end at removing__clk_get_hw()in SoC specific drivers (that will be solved by subsequent commits).
Quoted 3 lines
Signed-off-by Claudiu Beznea <[email protected]>[[email protected]: Remove SoC specific driver changes, those will be added in subsequent commits.]
With this, series is not bisectable.
Also, building this patch throws:
../drivers/clk/at91/sama7g5.c: In function ‘sama7g5_pmc_setup’:../drivers/clk/at91/sama7g5.c:1054:12: warning: passing argument 5 of ‘sam9x60_clk_register_frac_pll’ makes integer from pointer without a cast [-Wint-conversion]
1054 | NULL, parent_hw, i,
| ^~~~~~~~~
| |
| struct clk_hw *
In file included from ../drivers/clk/at91/sama7g5.c:17:
../drivers/clk/at91/pmc.h:260:24: note: expected ‘long unsigned int’ but
argument is of type ‘struct clk_hw *’
260 | unsigned long parent_rate, u8 id,
| ~~~~~~~~~~~~~~^~~~~~~~~~~../drivers/clk/at91/sama7d65.c: In function ‘sama7d65_pmc_setup’:../drivers/clk/at91/sama7d65.c:1175:12: warning: passing argument 5 of ‘sam9x60_clk_register_frac_pll’ makes integer from pointer without a cast [-Wint-conversion]
1175 | NULL, parent_hw, i,
| ^~~~~~~~~
| |
| struct clk_hw *
In file included from ../drivers/clk/at91/sama7d65.c:16:
../drivers/clk/at91/pmc.h:260:24: note: expected ‘long unsigned int’ but
argument is of type ‘struct clk_hw *’
260 | unsigned long parent_rate, u8 id,
| ~~~~~~~~~~~~~~^~~~~~~~~~~ AR drivers/clk/at91/built-in.a
Same for the rest of patches in this series following the "Remove SoC specific driver changes" approach.
Quoted 70 lines
Signed-off-by Ryan Wanner <[email protected]>--- drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++--------- drivers/clk/at91/pmc.h | 5 +++-- 2 files changed, 8 insertions(+), 11 deletions(-)drivers/clk/at91/clk-sam9x60-pll.c +5
-9@@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = {struct clk_hw *__init sam9x60_clk_register_frac_pll (struct regmap *regmap,spinlock_t *lock, -const char *name,const char *parent_name, -struct clk_hw *parent_hw,u8 id, +const char *name,const struct clk_parent_data *parent_data, +unsigned long parent_rate,u8 id,const struct clk_pll_characteristics *characteristics,const struct clk_pll_layout *layout,u32 flags) {struct sam9x60_frac *frac;struct clk_hw *hw;struct clk_init_data init = {}; -unsigned long parent_rate, irqflags; +unsigned long irqflags;unsigned int val;int ret; -if (id >PLL_MAX_ID || !lock || !parent_hw) +if (id >PLL_MAX_ID || !lock || !parent_data)return ERR_PTR (-EINVAL ); frac =kzalloc (sizeof (*frac),GFP_KERNEL );@@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,return ERR_PTR (-ENOMEM ); init.name = name; -if (parent_name) - init.parent_names = &parent_name; -else - init.parent_hws = (const struct clk_hw **)&parent_hw; + init.parent_data = (const struct clk_parent_data *)parent_data; init.num_parents =1 ;if (flags &CLK_SET_RATE_GATE ) init.ops = &sam9x60_frac_pll_ops;@@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,* its rate leading to enabling this PLL with unsupported * rate. This will lead to PLL not being locked at all. */ - parent_rate =clk_hw_get_rate (parent_hw);if (!parent_rate) { hw =ERR_PTR (-EINVAL ); goto free;drivers/clk/at91/pmc.h +3
-2@@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,struct clk_hw *__init sam9x60_clk_register_frac_pll (struct regmap *regmap,spinlock_t *lock, -const char *name,const char *parent_name, -struct clk_hw *parent_hw,u8 id, +const char *name, +const struct clk_parent_data *parent_data, +unsigned long parent_rate,u8 id,const struct clk_pll_characteristics *characteristics,const struct clk_pll_layout *layout,u32 flags);
Re: [PATCH v2 03/32] clk: at91: clk-sam9x60-pll: use clk_parent_data
Quoted 49 lines · Claudiu Beznea
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
Hi, Ryan,
Quoted 10 lines · On 24.06.2025 18:08, [email protected] wrote:
From: Claudiu Beznea <[email protected]>
Use struct
clk_parent_datainstead of structparent_hwas this leads to less usage of__clk_get_hw()in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers fromparent_namesto modernclk_parent_datastructures. As clk-sam9x60-pll need to know parent's rate at initialization we pass it now from SoC specific drivers. This will lead in the end at removing__clk_get_hw()in SoC specific drivers (that will be solved by subsequent commits).Quoted 3 lines
Signed-off-by Claudiu Beznea <[email protected]>[[email protected]: Remove SoC specific driver changes, those will be added in subsequent commits.]
With this, series is not bisectable.
Also, building this patch throws:
../drivers/clk/at91/sama7g5.c: In function ‘sama7g5_pmc_setup’:../drivers/clk/at91/sama7g5.c:1054:12: warning: passing argument 5 of ‘sam9x60_clk_register_frac_pll’ makes integer from pointer without a cast [-Wint-conversion]1054 | NULL, parent_hw, i, | ^~~~~~~~~ | | | struct clk_hw * In file included from ../drivers/clk/at91/sama7g5.c:17: ../drivers/clk/at91/pmc.h:260:24: note: expected ‘long unsigned int’ but argument is of type ‘struct clk_hw *’ 260 | unsigned long parent_rate, u8 id, | ~~~~~~~~~~~~~~^~~~~~~~~~~
../drivers/clk/at91/sama7d65.c: In function ‘sama7d65_pmc_setup’:../drivers/clk/at91/sama7d65.c:1175:12: warning: passing argument 5 of ‘sam9x60_clk_register_frac_pll’ makes integer from pointer without a cast [-Wint-conversion]1175 | NULL, parent_hw, i, | ^~~~~~~~~ | | | struct clk_hw * In file included from ../drivers/clk/at91/sama7d65.c:16: ../drivers/clk/at91/pmc.h:260:24: note: expected ‘long unsigned int’ but argument is of type ‘struct clk_hw *’ 260 | unsigned long parent_rate, u8 id, | ~~~~~~~~~~~~~~^~~~~~~~~~~
Quoted 5 lines
AR
drivers/clk/at91/built-in.aSame for the rest of patches in this series following the "Remove SoC specific driver changes" approach.
Would the best approach be to make every patch atomic and change every SoC to match each clock function change or put back in the sama7g54 clock driver changes that where combined?
Quoted 72 lines
Quoted 71 lines
Signed-off-by Ryan Wanner <[email protected]>--- drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++--------- drivers/clk/at91/pmc.h | 5 +++-- 2 files changed, 8 insertions(+), 11 deletions(-)drivers/clk/at91/clk-sam9x60-pll.c +5
-9@@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = {struct clk_hw *__init sam9x60_clk_register_frac_pll (struct regmap *regmap,spinlock_t *lock, -const char *name,const char *parent_name, -struct clk_hw *parent_hw,u8 id, +const char *name,const struct clk_parent_data *parent_data, +unsigned long parent_rate,u8 id,const struct clk_pll_characteristics *characteristics,const struct clk_pll_layout *layout,u32 flags) {struct sam9x60_frac *frac;struct clk_hw *hw;struct clk_init_data init = {}; -unsigned long parent_rate, irqflags; +unsigned long irqflags;unsigned int val;int ret; -if (id >PLL_MAX_ID || !lock || !parent_hw) +if (id >PLL_MAX_ID || !lock || !parent_data)return ERR_PTR (-EINVAL ); frac =kzalloc (sizeof (*frac),GFP_KERNEL );@@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,return ERR_PTR (-ENOMEM ); init.name = name; -if (parent_name) - init.parent_names = &parent_name; -else - init.parent_hws = (const struct clk_hw **)&parent_hw; + init.parent_data = (const struct clk_parent_data *)parent_data; init.num_parents =1 ;if (flags &CLK_SET_RATE_GATE ) init.ops = &sam9x60_frac_pll_ops;@@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,* its rate leading to enabling this PLL with unsupported * rate. This will lead to PLL not being locked at all. */ - parent_rate =clk_hw_get_rate (parent_hw);if (!parent_rate) { hw =ERR_PTR (-EINVAL ); goto free;drivers/clk/at91/pmc.h +3
-2@@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,struct clk_hw *__init sam9x60_clk_register_frac_pll (struct regmap *regmap,spinlock_t *lock, -const char *name,const char *parent_name, -struct clk_hw *parent_hw,u8 id, +const char *name, +const struct clk_parent_data *parent_data, +unsigned long parent_rate,u8 id,const struct clk_pll_characteristics *characteristics,const struct clk_pll_layout *layout,u32 flags);
Claudiu Beznea
maintainerRe: [PATCH v2 03/32] clk: at91: clk-sam9x60-pll: use clk_parent_data
Hi, Ryan,
Quoted 4 lines · Ryan Wanner
Quoted 2 lines
Same for the rest of patches in this series following the "Remove SoC specific driver changes" approach.
Would the best approach be to make every patch atomic and change every SoC to match each clock function change
Yes, this one.
Thank you,
Claudiu
Quoted 2 lines
or put back in the sama7g54
clock driver changes that where combined?
PATCH v2 4/32 clk: at91: clk-peripheral: switch to clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of parent_hw.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove the SoC specific changes those will be added in a later commit. And adjust commit message]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-peripheral.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-)
drivers/clk/at91/clk-peripheral.c +8 -8
@@ -97,7 +97,7 @@ static const struct clk_ops peripheral_ops = {struct clk_hw *__init at91_clk_register_peripheral (struct regmap *regmap,const char *name, -const char *parent_name,struct clk_hw *parent_hw, +const char *parent_name,struct clk_parent_data *parent_data,u32 id) {struct clk_peripheral *periph;
@@ -105,7 +105,7 @@ at91_clk_register_peripheral(struct regmap *regmap, const char *name,struct clk_hw *hw;int ret; -if (!name || !(parent_name || parent_hw) || id >PERIPHERAL_ID_MAX ) +if (!name || !(parent_name || parent_data) || id >PERIPHERAL_ID_MAX )return ERR_PTR (-EINVAL ); periph =kzalloc (sizeof (*periph),GFP_KERNEL );
@@ -114,8 +114,8 @@ at91_clk_register_peripheral(struct regmap *regmap, const char *name, init.name = name; init.ops = &peripheral_ops; -if (parent_hw) - init.parent_hws = (const struct clk_hw **)&parent_hw; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = &parent_name; init.num_parents =1 ;
@@ -448,7 +448,7 @@ struct clk_hw * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, u32 id, const struct clk_range *range, int chg_pid, unsigned long flags) {
@@ -457,7 +457,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,struct clk_hw *hw;int ret; -if (!name || !(parent_name || parent_hw)) +if (!name || !(parent_name || parent_data))return ERR_PTR (-EINVAL ); periph =kzalloc (sizeof (*periph),GFP_KERNEL );
@@ -465,8 +465,8 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,return ERR_PTR (-ENOMEM ); init.name = name; -if (parent_hw) - init.parent_hws = (const struct clk_hw **)&parent_hw; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = &parent_name; init.num_parents =1 ;
drivers/clk/at91/pmc.h +2 -2
@@ -226,13 +226,13 @@ at91_clk_sama7g5_register_master(struct regmap *regmap,struct clk_hw *__init at91_clk_register_peripheral (struct regmap *regmap,const char *name, -const char *parent_name,struct clk_hw *parent_hw, +const char *parent_name,struct clk_parent_data *parent_data,u32 id);struct clk_hw *__init at91_clk_register_sam9x5_peripheral (struct regmap *regmap,spinlock_t *lock,const struct clk_pcr_layout *layout,const char *name,const char *parent_name, -struct clk_hw *parent_hw, +struct clk_parent_data *parent_data,u32 id,const struct clk_range *range,int chg_pid,unsigned long flags);
Signature · 1 line
2.43.0
PATCH v2 5/32 clk: at91: clk-main: switch to clk parent data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of parent_hw as this leads to the use of modern clock structures.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes will be added in a later patch. Adjust commit message.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-main.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-)
drivers/clk/at91/clk-main.c +8 -8
@@ -402,7 +402,7 @@ struct clk_hw * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw) + struct clk_parent_data *parent_data) { struct clk_rm9200_main *clkmain;struct clk_init_data init = {};
@@ -412,7 +412,7 @@ at91_clk_register_rm9200_main(struct regmap *regmap,if (!name)return ERR_PTR (-EINVAL ); -if (!(parent_name || parent_hw)) +if (!(parent_name || parent_data))return ERR_PTR (-EINVAL ); clkmain =kzalloc (sizeof (*clkmain),GFP_KERNEL );
@@ -421,8 +421,8 @@ at91_clk_register_rm9200_main(struct regmap *regmap, init.name = name; init.ops = &rm9200_main_ops; -if (parent_hw) - init.parent_hws = (const struct clk_hw **)&parent_hw; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = &parent_name; init.num_parents =1 ;
@@ -552,7 +552,7 @@ struct clk_hw * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, int num_parents) { struct clk_sam9x5_main *clkmain;
@@ -564,7 +564,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,if (!name)return ERR_PTR (-EINVAL ); -if (!(parent_hws || parent_names) || !num_parents) +if (!(parent_data || parent_names) || !num_parents)return ERR_PTR (-EINVAL ); clkmain =kzalloc (sizeof (*clkmain),GFP_KERNEL );
@@ -573,8 +573,8 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, init.name = name; init.ops = &sam9x5_main_ops; -if (parent_hws) - init.parent_hws = (const struct clk_hw **)parent_hws; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = parent_names; init.num_parents = num_parents;
drivers/clk/at91/pmc.h +2 -2
@@ -195,11 +195,11 @@ struct clk_hw * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw); + struct clk_parent_data *parent_data);struct clk_hw *__init at91_clk_register_sam9x5_main (struct regmap *regmap,const char *name,const char **parent_names, -struct clk_hw **parent_hws,int num_parents); +struct clk_parent_data *parent_data,int num_parents);struct clk_hw *__init at91_clk_register_master_pres(struct regmap *regmap, const char *name,
Signature · 1 line
2.43.0
PATCH v2 6/32 clk: at91: clk-utmi: use clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes into a separate commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-utmi.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-)
drivers/clk/at91/clk-utmi.c +8 -8
@@ -144,7 +144,7 @@ static struct clk_hw * __init at91_clk_register_utmi_internal(struct regmap *regmap_pmc, struct regmap *regmap_sfr, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, const struct clk_ops *ops, unsigned long flags) { struct clk_utmi *utmi;
@@ -152,7 +152,7 @@ at91_clk_register_utmi_internal(struct regmap *regmap_pmc,struct clk_init_data init = {};int ret; -if (!(parent_name || parent_hw)) +if (!(parent_name || parent_data))return ERR_PTR (-EINVAL ); utmi =kzalloc (sizeof (*utmi),GFP_KERNEL );
@@ -161,8 +161,8 @@ at91_clk_register_utmi_internal(struct regmap *regmap_pmc, init.name = name; init.ops = ops; -if (parent_hw) - init.parent_hws = (const struct clk_hw **)&parent_hw; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = &parent_name; init.num_parents =1 ;
@@ -185,10 +185,10 @@ at91_clk_register_utmi_internal(struct regmap *regmap_pmc,struct clk_hw *__init at91_clk_register_utmi (struct regmap *regmap_pmc,struct regmap *regmap_sfr,const char *name,const char *parent_name, -struct clk_hw *parent_hw) +struct clk_parent_data *parent_data) {return at91_clk_register_utmi_internal (regmap_pmc, regmap_sfr, name, - parent_name, parent_hw, &utmi_ops,CLK_SET_RATE_GATE ); + parent_name, parent_data, &utmi_ops,CLK_SET_RATE_GATE ); }static int clk_utmi_sama7g5_prepare (struct clk_hw *hw)
@@ -287,8 +287,8 @@ static const struct clk_ops sama7g5_utmi_ops = {struct clk_hw *__init at91_clk_sama7g5_register_utmi (struct regmap *regmap_pmc,const char *name, -const char *parent_name,struct clk_hw *parent_hw) +const char *parent_name,struct clk_parent_data *parent_data) {return at91_clk_register_utmi_internal (regmap_pmc,NULL , name, - parent_name, parent_hw, &sama7g5_utmi_ops,0 ); + parent_name, parent_data, &sama7g5_utmi_ops,0 ); }
drivers/clk/at91/pmc.h +2 -2
@@ -299,10 +299,10 @@ at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,struct clk_hw *__init at91_clk_register_utmi (struct regmap *regmap_pmc,struct regmap *regmap_sfr,const char *name,const char *parent_name, -struct clk_hw *parent_hw); +struct clk_parent_data *parent_data);struct clk_hw *__init at91_clk_sama7g5_register_utmi (struct regmap *regmap,const char *name, -const char *parent_name,struct clk_hw *parent_hw); +const char *parent_name,struct clk_parent_data *parent_data);#endif /* __PMC_H_ */
Signature · 1 line
2.43.0
PATCH v2 7/32 clk: at91: clk-master: use clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they will be added later. Adjust commit message to reflect the removal of the SoC specific changes.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-master.c | 24 ++++++++++++------------ drivers/clk/at91/pmc.h | 6 +++--- 2 files changed, 15 insertions(+), 15 deletions(-)
drivers/clk/at91/clk-master.c +12 -12
@@ -473,7 +473,7 @@ static struct clk_hw * __init at91_clk_register_master_internal(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, const struct clk_ops *ops, spinlock_t *lock, u32 flags)
@@ -485,7 +485,7 @@ at91_clk_register_master_internal(struct regmap *regmap,unsigned long irqflags;int ret; -if (!name || !num_parents || !(parent_names || parent_hws) || !lock) +if (!name || !num_parents || !(parent_names || parent_data) || !lock)return ERR_PTR (-EINVAL ); master =kzalloc (sizeof (*master),GFP_KERNEL );
@@ -494,8 +494,8 @@ at91_clk_register_master_internal(struct regmap *regmap, init.name = name; init.ops = ops; -if (parent_hws) - init.parent_hws = (const struct clk_hw **)parent_hws; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = parent_names; init.num_parents = num_parents;
@@ -531,13 +531,13 @@ struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock) { return at91_clk_register_master_internal(regmap, name, num_parents, - parent_names, parent_hws, layout, + parent_names, parent_data, layout, characteristics, &master_pres_ops, lock, CLK_SET_RATE_GATE);
@@ -546,7 +546,7 @@ at91_clk_register_master_pres(struct regmap *regmap,struct clk_hw *__init at91_clk_register_master_div (struct regmap *regmap,const char *name,const char *parent_name, -struct clk_hw *parent_hw,const struct clk_master_layout *layout, +struct clk_parent_data *parent_data,const struct clk_master_layout *layout,const struct clk_master_characteristics *characteristics,spinlock_t *lock,u32 flags,u32 safe_div) {
@@ -560,7 +560,7 @@ at91_clk_register_master_div(struct regmap *regmap, hw =at91_clk_register_master_internal (regmap, name,1 , parent_name ? &parent_name :NULL , - parent_hw ? &parent_hw :NULL , layout, + parent_data, layout, characteristics, ops, lock, flags);
@@ -812,7 +812,7 @@ struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid)
@@ -824,7 +824,7 @@ at91_clk_sama7g5_register_master(struct regmap *regmap,unsigned int val;int ret; -if (!name || !num_parents || !(parent_names || parent_hws) || !mux_table || +if (!name || !num_parents || !(parent_names || parent_data) || !mux_table || !lock || id >MASTER_MAX_ID )return ERR_PTR (-EINVAL );
@@ -834,8 +834,8 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, init.name = name; init.ops = &sama7g5_master_ops; -if (parent_hws) - init.parent_hws = (const struct clk_hw **)parent_hws; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = parent_names; init.num_parents = num_parents;
drivers/clk/at91/pmc.h +3 -3
@@ -204,14 +204,14 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,struct clk_hw *__init at91_clk_register_master_pres (struct regmap *regmap,const char *name,int num_parents,const char **parent_names, -struct clk_hw **parent_hws, +struct clk_parent_data *parent_data,const struct clk_master_layout *layout,const struct clk_master_characteristics *characteristics,spinlock_t *lock);struct clk_hw *__init at91_clk_register_master_div (struct regmap *regmap,const char *name, -const char *parent_names,struct clk_hw *parent_hw, +const char *parent_names,struct clk_parent_data *parent_data,const struct clk_master_layout *layout,const struct clk_master_characteristics *characteristics,spinlock_t *lock,u32 flags,u32 safe_div);
@@ -220,7 +220,7 @@ struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, u32 *mux_table, + struct clk_parent_data *parent_data, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid);
Signature · 1 line
2.43.0
PATCH v2 8/32 clk: at91: clk-programmable: use clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes those will be added in a separate commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-programmable.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-)
drivers/clk/at91/clk-programmable.c +4 -4
@@ -215,7 +215,7 @@ static const struct clk_ops programmable_ops = {struct clk_hw *__init at91_clk_register_programmable (struct regmap *regmap,const char *name,const char **parent_names, -struct clk_hw **parent_hws,u8 num_parents,u8 id, +struct clk_parent_data *parent_data,u8 num_parents,u8 id,const struct clk_programmable_layout *layout,u32 *mux_table) {
@@ -224,7 +224,7 @@ at91_clk_register_programmable(struct regmap *regmap,struct clk_init_data init = {};int ret; -if (id >PROG_ID_MAX || !(parent_names || parent_hws)) +if (id >PROG_ID_MAX || !(parent_names || parent_data))return ERR_PTR (-EINVAL ); prog =kzalloc (sizeof (*prog),GFP_KERNEL );
@@ -233,8 +233,8 @@ at91_clk_register_programmable(struct regmap *regmap, init.name = name; init.ops = &programmable_ops; -if (parent_hws) - init.parent_hws = (const struct clk_hw **)parent_hws; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = parent_names; init.num_parents = num_parents;
drivers/clk/at91/pmc.h +1 -1
@@ -263,7 +263,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,struct clk_hw *__init at91_clk_register_programmable (struct regmap *regmap,const char *name, -const char **parent_names,struct clk_hw **parent_hws, +const char **parent_names,struct clk_parent_data *parent_data,u8 num_parents,u8 id,const struct clk_programmable_layout *layout,u32 *mux_table);
Signature · 1 line
2.43.0
PATCH v2 9/32 clk: at91: clk-generated: use clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-generated.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-)
drivers/clk/at91/clk-generated.c +4 -4
@@ -319,7 +319,7 @@ struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid)
@@ -329,7 +329,7 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,struct clk_hw *hw;int ret; -if (!(parent_names || parent_hws)) +if (!(parent_names || parent_data))return ERR_PTR (-ENOMEM ); gck =kzalloc (sizeof (*gck),GFP_KERNEL );
@@ -338,8 +338,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, init.name = name; init.ops = &generated_ops; -if (parent_hws) - init.parent_hws = (const struct clk_hw **)parent_hws; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = parent_names; init.num_parents = num_parents;
drivers/clk/at91/pmc.h +1 -1
@@ -171,7 +171,7 @@ struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, - struct clk_hw **parent_hws, u32 *mux_table, + struct clk_parent_data *parent_data, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid);
Signature · 1 line
2.43.0
PATCH v2 10/32 clk: at91: clk-usb: add support for clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for clk_parent_data in usb clock driver.
All the SoC based drivers that rely on clk-usb were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/at91rm9200.c | 2 +- drivers/clk/at91/at91sam9260.c | 2 +- drivers/clk/at91/at91sam9g45.c | 2 +- drivers/clk/at91/at91sam9n12.c | 2 +- drivers/clk/at91/at91sam9x5.c | 2 +- drivers/clk/at91/clk-usb.c | 41 ++++++++++++++++++++++------------ drivers/clk/at91/dt-compat.c | 6 ++--- drivers/clk/at91/pmc.h | 11 +++++---- drivers/clk/at91/sam9x60.c | 2 +- drivers/clk/at91/sama5d2.c | 2 +- drivers/clk/at91/sama5d3.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- 12 files changed, 46 insertions(+), 30 deletions(-)
drivers/clk/at91/at91rm9200.c +1 -1
@@ -157,7 +157,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) at91rm9200_pmc->chws[PMC_MCK ] = hw; - hw =at91rm9200_clk_register_usb (regmap,"usbck" ,"pllbck" , usb_div); + hw =at91rm9200_clk_register_usb (regmap,"usbck" ,"pllbck" ,NULL , usb_div);if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/at91sam9260.c +1 -1
@@ -434,7 +434,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, at91sam9260_pmc->chws[PMC_MCK ] = hw; - hw =at91rm9200_clk_register_usb (regmap,"usbck" ,"pllbck" , usb_div); + hw =at91rm9200_clk_register_usb (regmap,"usbck" ,"pllbck" ,NULL , usb_div);if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/at91sam9g45.c +1 -1
@@ -176,7 +176,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) parent_names[0 ] ="plladivck" ; parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,2 ); + hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 );if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/at91sam9n12.c +1 -1
@@ -201,7 +201,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) at91sam9n12_pmc->chws[PMC_MCK ] = hw; - hw =at91sam9n12_clk_register_usb (regmap,"usbck" ,"pllbck" ); + hw =at91sam9n12_clk_register_usb (regmap,"usbck" ,"pllbck" ,NULL );if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/at91sam9x5.c +1 -1
@@ -222,7 +222,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, parent_names[0 ] ="plladivck" ; parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,2 ); + hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 );if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/clk-usb.c +27 -14
98 lines not on this page · raw message
drivers/clk/at91/dt-compat.c +3 -3
@@ -946,7 +946,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91sam9x5_clk_register_usb (regmap, name, parent_names, + hw =at91sam9x5_clk_register_usb (regmap, name, parent_names,NULL , num_parents);if (IS_ERR (hw))return ;
@@ -976,7 +976,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91sam9n12_clk_register_usb (regmap, name, parent_name); + hw =at91sam9n12_clk_register_usb (regmap, name, parent_name,NULL );if (IS_ERR (hw))return ;
@@ -1009,7 +1009,7 @@ static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)of_node_put (parent_np);if (IS_ERR (regmap))return ; - hw =at91rm9200_clk_register_usb (regmap, name, parent_name, divisors); + hw =at91rm9200_clk_register_usb (regmap, name, parent_name,NULL , divisors);if (IS_ERR (hw))return ;
drivers/clk/at91/pmc.h +7 -4
@@ -285,16 +285,19 @@ at91_clk_register_system(struct regmap *regmap, const char *name,struct clk_hw *__init at91sam9x5_clk_register_usb (struct regmap *regmap,const char *name, -const char **parent_names,u8 num_parents); +const char **parent_names,struct clk_parent_data *parent_data, +u8 num_parents);struct clk_hw *__init at91sam9n12_clk_register_usb (struct regmap *regmap,const char *name, -const char *parent_name); +const char *parent_name,struct clk_parent_data *parent_data);struct clk_hw *__init sam9x60_clk_register_usb (struct regmap *regmap,const char *name, -const char **parent_names,u8 num_parents); +const char **parent_names,struct clk_parent_data *parent_data, +u8 num_parents);struct clk_hw *__init at91rm9200_clk_register_usb (struct regmap *regmap,const char *name, -const char *parent_name,const u32 *divisors); +const char *parent_name,struct clk_parent_data *parent_data, +const u32 *divisors);struct clk_hw *__init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
drivers/clk/at91/sam9x60.c +1 -1
@@ -304,7 +304,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) parent_names[0 ] ="pllack_divck" ; parent_names[1 ] ="upllck_divck" ; parent_names[2 ] ="main_osc" ; - hw =sam9x60_clk_register_usb (regmap,"usbck" , parent_names,3 ); + hw =sam9x60_clk_register_usb (regmap,"usbck" , parent_names,NULL ,3 );if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/sama5d2.c +1 -1
@@ -284,7 +284,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) parent_names[0 ] ="plladivck" ; parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,2 ); + hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 );if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/sama5d3.c +1 -1
@@ -201,7 +201,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np) parent_names[0 ] ="plladivck" ; parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,2 ); + hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 );if (IS_ERR (hw)) goto err_free;
drivers/clk/at91/sama5d4.c +1 -1
@@ -222,7 +222,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) parent_names[0 ] ="plladivck" ; parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,2 ); + hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 );if (IS_ERR (hw)) goto err_free;
Signature · 1 line
2.43.0
PATCH v2 11/32 clk: at91: clk-system: use clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-system.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-)
drivers/clk/at91/clk-system.c +4 -4
@@ -105,7 +105,7 @@ static const struct clk_ops system_ops = {struct clk_hw *__init at91_clk_register_system (struct regmap *regmap,const char *name, -const char *parent_name,struct clk_hw *parent_hw,u8 id, +const char *parent_name,struct clk_parent_data *parent_data,u8 id,unsigned long flags) {struct clk_system *sys;
@@ -113,7 +113,7 @@ at91_clk_register_system(struct regmap *regmap, const char *name,struct clk_init_data init = {};int ret; -if (!(parent_name || parent_hw) || id >SYSTEM_MAX_ID ) +if (!(parent_name || parent_data) || id >SYSTEM_MAX_ID )return ERR_PTR (-EINVAL ); sys =kzalloc (sizeof (*sys),GFP_KERNEL );
@@ -122,8 +122,8 @@ at91_clk_register_system(struct regmap *regmap, const char *name, init.name = name; init.ops = &system_ops; -if (parent_hw) - init.parent_hws = (const struct clk_hw **)&parent_hw; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data;else init.parent_names = &parent_name; init.num_parents =1 ;
drivers/clk/at91/pmc.h +1 -1
@@ -280,7 +280,7 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,struct clk_hw *__init at91_clk_register_system (struct regmap *regmap,const char *name, -const char *parent_name,struct clk_hw *parent_hw, +const char *parent_name,struct clk_parent_data *parent_data,u8 id,unsigned long flags); struct clk_hw * __init
Signature · 1 line
2.43.0
PATCH v2 12/32 clk: at91: clk-pll: add support for parent_hw
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for parent_hw in pll clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster.
All the SoC based drivers that rely on clk-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-pll.c | 9 ++++++--- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-)
drivers/clk/at91/clk-pll.c +6 -3
@@ -310,13 +310,13 @@ static const struct clk_ops pll_ops = {struct clk_hw *__init at91_clk_register_pll (struct regmap *regmap,const char *name, -const char *parent_name,u8 id, +const char *parent_name,struct clk_parent_data *parent_data,u8 id,const struct clk_pll_layout *layout,const struct clk_pll_characteristics *characteristics) {struct clk_pll *pll;struct clk_hw *hw; -struct clk_init_data init; +struct clk_init_data init = {};int offset =PLL_REG (id);unsigned int pllr;int ret;
@@ -330,7 +330,10 @@ at91_clk_register_pll(struct regmap *regmap, const char *name, init.name = name; init.ops = &pll_ops; - init.parent_names = &parent_name; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = &parent_name; init.num_parents =1 ; init.flags =CLK_SET_RATE_GATE ;
drivers/clk/at91/dt-compat.c +1 -1
@@ -665,7 +665,7 @@ of_at91_clk_pll_setup(struct device_node *np,if (!characteristics)return ; - hw =at91_clk_register_pll (regmap, name, parent_name, id, layout, + hw =at91_clk_register_pll (regmap, name, parent_name,NULL , id, layout, characteristics);if (IS_ERR (hw)) goto out_free_characteristics;
drivers/clk/at91/pmc.h +1 -1
@@ -238,7 +238,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,struct clk_hw *__init at91_clk_register_pll (struct regmap *regmap,const char *name, -const char *parent_name,u8 id, +const char *parent_name,struct clk_parent_data *parent_data,u8 id,const struct clk_pll_layout *layout,const struct clk_pll_characteristics *characteristics); struct clk_hw * __init
Signature · 1 line
2.43.0
PATCH v2 13/32 clk: at91: clk-audio-pll: add support for parent_hw
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for parent_hw in audio pll clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster.
All the SoC based drivers that rely on clk-audio-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-audio-pll.c | 28 ++++++++++++++++++++-------- drivers/clk/at91/dt-compat.c | 6 +++--- drivers/clk/at91/pmc.h | 6 +++--- 3 files changed, 26 insertions(+), 14 deletions(-)
drivers/clk/at91/clk-audio-pll.c +20 -8
@@ -450,7 +450,8 @@ static const struct clk_ops audio_pll_pmc_ops = {struct clk_hw *__init at91_clk_register_audio_pll_frac (struct regmap *regmap,const char *name, -const char *parent_name) +const char *parent_name, +struct clk_parent_data *parent_data) {struct clk_audio_frac *frac_ck;struct clk_init_data init = {};
@@ -462,7 +463,10 @@ at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, init.name = name; init.ops = &audio_pll_frac_ops; - init.parent_names = &parent_name; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = &parent_name; init.num_parents =1 ; init.flags =CLK_SET_RATE_GATE ;
@@ -480,10 +484,11 @@ at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,struct clk_hw *__init at91_clk_register_audio_pll_pad (struct regmap *regmap,const char *name, -const char *parent_name) +const char *parent_name, +struct clk_parent_data *parent_data) {struct clk_audio_pad *apad_ck; -struct clk_init_data init; +struct clk_init_data init = {};int ret; apad_ck =kzalloc (sizeof (*apad_ck),GFP_KERNEL );
@@ -492,7 +497,10 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, init.name = name; init.ops = &audio_pll_pad_ops; - init.parent_names = &parent_name; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = &parent_name; init.num_parents =1 ; init.flags =CLK_SET_RATE_GATE |CLK_SET_PARENT_GATE |CLK_SET_RATE_PARENT ;
@@ -511,10 +519,11 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,struct clk_hw *__init at91_clk_register_audio_pll_pmc (struct regmap *regmap,const char *name, -const char *parent_name) +const char *parent_name, +struct clk_parent_data *parent_data) {struct clk_audio_pmc *apmc_ck; -struct clk_init_data init; +struct clk_init_data init = {};int ret; apmc_ck =kzalloc (sizeof (*apmc_ck),GFP_KERNEL );
@@ -523,7 +532,10 @@ at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, init.name = name; init.ops = &audio_pll_pmc_ops; - init.parent_names = &parent_name; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = &parent_name; init.num_parents =1 ; init.flags =CLK_SET_RATE_GATE |CLK_SET_PARENT_GATE |CLK_SET_RATE_PARENT ;
drivers/clk/at91/dt-compat.c +3 -3
@@ -43,7 +43,7 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_audio_pll_frac (regmap, name, parent_name); + hw =at91_clk_register_audio_pll_frac (regmap, name, parent_name,NULL );if (IS_ERR (hw))return ;
@@ -69,7 +69,7 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_audio_pll_pad (regmap, name, parent_name); + hw =at91_clk_register_audio_pll_pad (regmap, name, parent_name,NULL );if (IS_ERR (hw))return ;
@@ -95,7 +95,7 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_audio_pll_pmc (regmap, name, parent_name); + hw =at91_clk_register_audio_pll_pmc (regmap, name, parent_name,NULL );if (IS_ERR (hw))return ;
drivers/clk/at91/pmc.h +3 -3
@@ -157,15 +157,15 @@ struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);struct clk_hw *__init at91_clk_register_audio_pll_frac (struct regmap *regmap,const char *name, -const char *parent_name); +const char *parent_name,struct clk_parent_data *parent_data);struct clk_hw *__init at91_clk_register_audio_pll_pad (struct regmap *regmap,const char *name, -const char *parent_name); +const char *parent_name,struct clk_parent_data *parent_data);struct clk_hw *__init at91_clk_register_audio_pll_pmc (struct regmap *regmap,const char *name, -const char *parent_name); +const char *parent_name,struct clk_parent_data *parent_data);struct clk_hw *__init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
Signature · 1 line
2.43.0
PATCH v2 14/32 clk: at91: clk-plldiv: add support for parent_hw
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for parent_hw in plldiv clock driver.
With this parent-child relation is described with pointers rather than strings making registration a bit faster.
All the SoC based drivers that rely on clk-plldiv were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-plldiv.c | 11 +++++++---- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-)
drivers/clk/at91/clk-plldiv.c +7 -4
@@ -72,11 +72,11 @@ static const struct clk_ops plldiv_ops = {struct clk_hw *__init at91_clk_register_plldiv (struct regmap *regmap,const char *name, -const char *parent_name) +const char *parent_name,struct clk_parent_data *parent_data) {struct clk_plldiv *plldiv;struct clk_hw *hw; -struct clk_init_data init; +struct clk_init_data init = {};int ret; plldiv =kzalloc (sizeof (*plldiv),GFP_KERNEL );
@@ -85,8 +85,11 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name, init.name = name; init.ops = &plldiv_ops; - init.parent_names = parent_name ? &parent_name :NULL ; - init.num_parents = parent_name ?1 :0 ; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = &parent_name; + init.num_parents =1 ; init.flags =CLK_SET_RATE_GATE ; plldiv->hw.init = &init;
drivers/clk/at91/dt-compat.c +1 -1
@@ -724,7 +724,7 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91_clk_register_plldiv (regmap, name, parent_name); + hw =at91_clk_register_plldiv (regmap, name, parent_name,NULL );if (IS_ERR (hw))return ;
drivers/clk/at91/pmc.h +1 -1
@@ -243,7 +243,7 @@ at91_clk_register_pll(struct regmap *regmap, const char *name, const struct clk_pll_characteristics *characteristics);struct clk_hw *__init at91_clk_register_plldiv (struct regmap *regmap,const char *name, -const char *parent_name); +const char *parent_name,struct clk_parent_data *parent_data);struct clk_hw *__init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
Signature · 1 line
2.43.0
PATCH v2 15/32 clk: at91: clk-h32mx: add support for parent_hw
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for parent_hw in h32mx clock driver.
With this parent-child relation is described with pointers rather than strings making registration a bit faster.
All the SoC based drivers that rely on clk-h32mx were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-h32mx.c | 11 +++++++---- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-)
drivers/clk/at91/clk-h32mx.c +7 -4
@@ -83,10 +83,10 @@ static const struct clk_ops h32mx_ops = {struct clk_hw *__init at91_clk_register_h32mx (struct regmap *regmap,const char *name, -const char *parent_name) +const char *parent_name,struct clk_parent_data *parent_data) {struct clk_sama5d4_h32mx *h32mxclk; -struct clk_init_data init; +struct clk_init_data init = {};int ret; h32mxclk =kzalloc (sizeof (*h32mxclk),GFP_KERNEL );
@@ -95,8 +95,11 @@ at91_clk_register_h32mx(struct regmap *regmap, const char *name, init.name = name; init.ops = &h32mx_ops; - init.parent_names = parent_name ? &parent_name :NULL ; - init.num_parents = parent_name ?1 :0 ; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = &parent_name; + init.num_parents =1 ; init.flags =CLK_SET_RATE_GATE ; h32mxclk->hw.init = &init;
drivers/clk/at91/dt-compat.c +1 -1
@@ -201,7 +201,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_h32mx (regmap, name, parent_name); + hw =at91_clk_register_h32mx (regmap, name, parent_name,NULL );if (IS_ERR (hw))return ;
drivers/clk/at91/pmc.h +1 -1
@@ -177,7 +177,7 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,struct clk_hw *__init at91_clk_register_h32mx (struct regmap *regmap,const char *name, -const char *parent_name); +const char *parent_name,struct clk_parent_data *parent_data);struct clk_hw *__init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
Signature · 1 line
2.43.0
PATCH v2 16/32 clk: at91: clk-i2s-mux: add support for parent_hw
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for parent_hw in i2s mux clock driver.
With this parent-child relation is described with pointers rather than strings making registration a bit faster.
All the SoC based drivers that rely on clk-i2s-mux were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-i2s-mux.c | 6 +++++- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 1 + 3 files changed, 7 insertions(+), 2 deletions(-)
drivers/clk/at91/clk-i2s-mux.c +5 -1
@@ -51,6 +51,7 @@ static const struct clk_ops clk_i2s_mux_ops = {struct clk_hw *__init at91_clk_i2s_mux_register (struct regmap *regmap,const char *name,const char *const *parent_names, +struct clk_parent_data *parent_data,unsigned int num_parents,u8 bus_id) {struct clk_init_data init = {};
@@ -63,7 +64,10 @@ at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, init.name = name; init.ops = &clk_i2s_mux_ops; - init.parent_names = parent_names; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = parent_names; init.num_parents = num_parents; i2s_ck->hw.init = &init;
drivers/clk/at91/dt-compat.c +1 -1
@@ -239,7 +239,7 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)continue ; hw =at91_clk_i2s_mux_register (regmap_sfr, i2s_mux_np->name, - parent_names,2 , bus_id); + parent_names,NULL ,2 , bus_id);if (IS_ERR (hw))continue ;
drivers/clk/at91/pmc.h +1 -0
@@ -182,6 +182,7 @@ at91_clk_register_h32mx(struct regmap *regmap, const char *name,struct clk_hw *__init at91_clk_i2s_mux_register (struct regmap *regmap,const char *name,const char *const *parent_names, +struct clk_parent_data *parent_data,unsigned int num_parents,u8 bus_id); struct clk_hw * __init
Signature · 1 line
2.43.0
PATCH v2 17/32 clk: at91: clk-smd: add support for clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for parent_hw in smd clock drivers.
With this parent-child relation is described with pointers rather than strings making registration a bit faster.
All the SoC based drivers that rely on clk-smd were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-smd.c | 10 +++++++--- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 3 ++- 3 files changed, 10 insertions(+), 5 deletions(-)
drivers/clk/at91/clk-smd.c +7 -3
@@ -111,11 +111,12 @@ static const struct clk_ops at91sam9x5_smd_ops = {struct clk_hw *__init at91sam9x5_clk_register_smd (struct regmap *regmap,const char *name, -const char **parent_names,u8 num_parents) +const char **parent_names,struct clk_parent_data *parent_data, +u8 num_parents) {struct at91sam9x5_clk_smd *smd;struct clk_hw *hw; -struct clk_init_data init; +struct clk_init_data init = {};int ret; smd =kzalloc (sizeof (*smd),GFP_KERNEL );
@@ -124,7 +125,10 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, init.name = name; init.ops = &at91sam9x5_smd_ops; - init.parent_names = parent_names; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)parent_data; +else + init.parent_names = parent_names; init.num_parents = num_parents; init.flags =CLK_SET_RATE_GATE |CLK_SET_PARENT_GATE ;
drivers/clk/at91/dt-compat.c +1 -1
@@ -859,7 +859,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91sam9x5_clk_register_smd (regmap, name, parent_names, + hw =at91sam9x5_clk_register_smd (regmap, name, parent_names,NULL , num_parents);if (IS_ERR (hw))return ;
drivers/clk/at91/pmc.h +2 -1
@@ -277,7 +277,8 @@ at91_clk_register_sam9260_slow(struct regmap *regmap,struct clk_hw *__init at91sam9x5_clk_register_smd (struct regmap *regmap,const char *name, -const char **parent_names,u8 num_parents); +const char **parent_names,struct clk_parent_data *parent_data, +u8 num_parents);struct clk_hw *__init at91_clk_register_system(struct regmap *regmap, const char *name,
Signature · 1 line
2.43.0
PATCH v2 18/32 clk: at91: clk-slow: add support for parent_hw
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Add support for parent_hw in slow clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster.
All the SoC based drivers that rely on clk-slow were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/clk-slow.c | 8 ++++++-- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 1 + 3 files changed, 8 insertions(+), 3 deletions(-)
drivers/clk/at91/clk-slow.c +6 -2
@@ -39,11 +39,12 @@ struct clk_hw * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, + struct clk_parent_data *parent_data, int num_parents) { struct clk_sam9260_slow *slowck;struct clk_hw *hw; -struct clk_init_data init; +struct clk_init_data init = {};int ret;if (!name)
@@ -58,7 +59,10 @@ at91_clk_register_sam9260_slow(struct regmap *regmap, init.name = name; init.ops = &sam9260_slow_ops; - init.parent_names = parent_names; +if (parent_data) + init.parent_data = (const struct clk_parent_data *)&parent_data; +else + init.parent_names = parent_names; init.num_parents = num_parents; init.flags =0 ;
drivers/clk/at91/dt-compat.c +1 -1
@@ -823,7 +823,7 @@ static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)of_property_read_string (np,"clock-output-names" , &name); - hw =at91_clk_register_sam9260_slow (regmap, name, parent_names, + hw =at91_clk_register_sam9260_slow (regmap, name, parent_names,NULL , num_parents);if (IS_ERR (hw))return ;
drivers/clk/at91/pmc.h +1 -0
@@ -273,6 +273,7 @@ struct clk_hw * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, + struct clk_parent_data *parent_data, int num_parents); struct clk_hw * __init
Signature · 1 line
2.43.0
PATCH v2 19/32 clk: at91: dt-compat: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch old dt-compat clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/dt-compat.c | 80 +++++++++++++++++++++++++----------- 1 file changed, 56 insertions(+), 24 deletions(-)
drivers/clk/at91/dt-compat.c +56 -24
@@ -43,7 +43,8 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_audio_pll_frac (regmap, name, parent_name,NULL ); + hw =at91_clk_register_audio_pll_frac (regmap, name,NULL , + &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
@@ -69,7 +70,8 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_audio_pll_pad (regmap, name, parent_name,NULL ); + hw =at91_clk_register_audio_pll_pad (regmap, name,NULL , + &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
@@ -95,7 +97,7 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_audio_pll_pmc (regmap, name, parent_name,NULL ); + hw =at91_clk_register_audio_pll_pmc (regmap, name,NULL , &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
@@ -129,6 +131,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)struct clk_hw *hw;unsigned int num_parents;const char *parent_names[GENERATED_SOURCE_MAX ]; +struct clk_parent_data parent_data[GENERATED_SOURCE_MAX ];struct device_node *gcknp, *parent_np;struct clk_range range =CLK_RANGE (0 ,0 );struct regmap *regmap;
@@ -149,6 +152,8 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)if (IS_ERR (regmap))return ; +for (unsigned int i =0 ; i < num_parents; i++) + parent_data[i] =AT91_CLK_PD_NAME (parent_names[i], i);for_each_child_of_node (np, gcknp) {int chg_pid =INT_MIN ;
@@ -171,7 +176,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np) hw =at91_clk_register_generated (regmap, &pmc_pcr_lock, &dt_pcr_layout, name, - parent_names,NULL ,NULL , +NULL , parent_data,NULL , num_parents, id, &range, chg_pid);if (IS_ERR (hw))
@@ -201,7 +206,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) parent_name =of_clk_get_parent_name (np,0 ); - hw =at91_clk_register_h32mx (regmap, name, parent_name,NULL ); + hw =at91_clk_register_h32mx (regmap, name,NULL , &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
@@ -228,6 +233,8 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)return ;for_each_child_of_node (np, i2s_mux_np) { +struct clk_parent_data parent_data[2 ]; +if (of_property_read_u8 (i2s_mux_np,"reg" , &bus_id))continue ;
@@ -238,8 +245,10 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)if (ret !=2 )continue ; + parent_data[0 ] =AT91_CLK_PD_NAME (parent_names[0 ],0 ); + parent_data[1 ] =AT91_CLK_PD_NAME (parent_names[1 ],1 ); hw =at91_clk_i2s_mux_register (regmap_sfr, i2s_mux_np->name, - parent_names,NULL ,2 , bus_id); +NULL , parent_data,2 , bus_id);if (IS_ERR (hw))continue ;
@@ -269,7 +278,8 @@ static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91_clk_register_main_osc (regmap, name, parent_name,NULL , bypass); + hw =at91_clk_register_main_osc (regmap, name,NULL , + &AT91_CLK_PD_NAME (parent_name,0 ), bypass);if (IS_ERR (hw))return ;
@@ -323,7 +333,7 @@ static void __init of_at91rm9200_clk_main_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91_clk_register_rm9200_main (regmap, name, parent_name,NULL ); + hw =at91_clk_register_rm9200_main (regmap, name,NULL , &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
@@ -336,6 +346,7 @@ static void __init of_at91sam9x5_clk_main_setup(struct device_node *np) {struct clk_hw *hw;const char *parent_names[2 ]; +struct clk_parent_data parent_data[2 ];unsigned int num_parents;const char *name = np->name;struct regmap *regmap;
@@ -354,7 +365,9 @@ static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)of_property_read_string (np,"clock-output-names" , &name); - hw =at91_clk_register_sam9x5_main (regmap, name, parent_names,NULL , + parent_data[0 ] =AT91_CLK_PD_NAME (parent_names[0 ],0 ); + parent_data[1 ] =AT91_CLK_PD_NAME (parent_names[1 ],1 ); + hw =at91_clk_register_sam9x5_main (regmap, name,NULL , parent_data, num_parents);if (IS_ERR (hw))return ;
@@ -396,6 +409,7 @@ of_at91_clk_master_setup(struct device_node *np,struct clk_hw *hw;unsigned int num_parents;const char *parent_names[MASTER_SOURCE_MAX ]; +struct clk_parent_data parent_data[MASTER_SOURCE_MAX ];const char *name = np->name;struct clk_master_characteristics *characteristics;struct regmap *regmap;
@@ -419,13 +433,15 @@ of_at91_clk_master_setup(struct device_node *np,if (IS_ERR (regmap))return ; +for (unsigned int i =0 ; i <MASTER_SOURCE_MAX ; i++) + parent_data[i] =AT91_CLK_PD_NAME (parent_names[i], i); hw =at91_clk_register_master_pres (regmap,"masterck_pres" , num_parents, - parent_names,NULL , layout, +NULL , parent_data, layout, characteristics, &mck_lock);if (IS_ERR (hw)) goto out_free_characteristics; - hw =at91_clk_register_master_div (regmap, name,"masterck_pres" ,NULL , + hw =at91_clk_register_master_div (regmap, name,NULL , &AT91_CLK_PD_HW (hw), layout, characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );if (IS_ERR (hw))
@@ -489,8 +505,8 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type) name = periphclknp->name;if (type ==PERIPHERAL_AT91RM9200 ) { - hw =at91_clk_register_peripheral (regmap, name, - parent_name,NULL , id); + hw =at91_clk_register_peripheral (regmap, name,NULL , + &AT91_CLK_PD_NAME (parent_name,0 ), id); }else {struct clk_range range =CLK_RANGE (0 ,0 );unsigned long flags =0 ;
@@ -511,8 +527,8 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type) &pmc_pcr_lock, &dt_pcr_layout, name, - parent_name,NULL , + &AT91_CLK_PD_NAME (parent_name,0 ), id, &range,INT_MIN , flags);
@@ -665,7 +681,8 @@ of_at91_clk_pll_setup(struct device_node *np,if (!characteristics)return ; - hw =at91_clk_register_pll (regmap, name, parent_name,NULL , id, layout, + hw =at91_clk_register_pll (regmap, name,NULL , &AT91_CLK_PD_NAME (parent_name,0 ), + id, layout, characteristics);if (IS_ERR (hw)) goto out_free_characteristics;
@@ -724,7 +741,7 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91_clk_register_plldiv (regmap, name, parent_name,NULL ); + hw =at91_clk_register_plldiv (regmap, name,NULL , &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
@@ -743,6 +760,7 @@ of_at91_clk_prog_setup(struct device_node *np,struct clk_hw *hw;unsigned int num_parents;const char *parent_names[PROG_SOURCE_MAX ]; +struct clk_parent_data parent_data[PROG_SOURCE_MAX ];const char *name;struct device_node *progclknp, *parent_np;struct regmap *regmap;
@@ -763,6 +781,8 @@ of_at91_clk_prog_setup(struct device_node *np,if (IS_ERR (regmap))return ; +for (unsigned int i =0 ; i <PROG_SOURCE_MAX ; i++) + parent_data[i] =AT91_CLK_PD_NAME (parent_names[i], i);for_each_child_of_node (np, progclknp) {if (of_property_read_u32 (progclknp,"reg" , &id))continue ;
@@ -771,7 +791,7 @@ of_at91_clk_prog_setup(struct device_node *np, name = progclknp->name; hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL , num_parents, +NULL , parent_data, num_parents, id, layout, mux_table);if (IS_ERR (hw))continue ;
@@ -805,6 +825,7 @@ static void __init of_at91sam9260_clk_slow_setup(struct device_node *np) {struct clk_hw *hw;const char *parent_names[2 ]; +struct clk_parent_data parent_data[2 ];unsigned int num_parents;const char *name = np->name;struct regmap *regmap;
@@ -823,7 +844,9 @@ static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)of_property_read_string (np,"clock-output-names" , &name); - hw =at91_clk_register_sam9260_slow (regmap, name, parent_names,NULL , + parent_data[0 ] =AT91_CLK_PD_NAME (parent_names[0 ],0 ); + parent_data[1 ] =AT91_CLK_PD_NAME (parent_names[1 ],1 ); + hw =at91_clk_register_sam9260_slow (regmap, name,NULL , parent_data, num_parents);if (IS_ERR (hw))return ;
@@ -841,6 +864,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)struct clk_hw *hw;unsigned int num_parents;const char *parent_names[SMD_SOURCE_MAX ]; +struct clk_parent_data parent_data[SMD_SOURCE_MAX ];const char *name = np->name;struct regmap *regmap;struct device_node *parent_np;
@@ -859,7 +883,9 @@ static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91sam9x5_clk_register_smd (regmap, name, parent_names,NULL , +for (unsigned int i =0 ; i <SMD_SOURCE_MAX ; i++) + parent_data[i] =AT91_CLK_PD_NAME (parent_names[i], i); + hw =at91sam9x5_clk_register_smd (regmap, name,NULL , parent_data, num_parents);if (IS_ERR (hw))return ;
@@ -909,7 +935,8 @@ static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)if (!strcmp (sysclknp->name,"ddrck" )) flags =CLK_IS_CRITICAL ; - hw =at91_clk_register_system (regmap, name, parent_name,NULL , + hw =at91_clk_register_system (regmap, name,NULL , + &AT91_CLK_PD_NAME (parent_name,0 ), id, flags);if (IS_ERR (hw))continue ;
@@ -928,6 +955,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)struct clk_hw *hw;unsigned int num_parents;const char *parent_names[USB_SOURCE_MAX ]; +struct clk_parent_data parent_data[USB_SOURCE_MAX ];const char *name = np->name;struct regmap *regmap;struct device_node *parent_np;
@@ -946,7 +974,9 @@ static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91sam9x5_clk_register_usb (regmap, name, parent_names,NULL , +for (unsigned int i =0 ; i <USB_SOURCE_MAX ; i++) + parent_data[i] =AT91_CLK_PD_NAME (parent_names[i], i); + hw =at91sam9x5_clk_register_usb (regmap, name,NULL , parent_data, num_parents);if (IS_ERR (hw))return ;
@@ -976,7 +1006,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)if (IS_ERR (regmap))return ; - hw =at91sam9n12_clk_register_usb (regmap, name, parent_name,NULL ); + hw =at91sam9n12_clk_register_usb (regmap, name,NULL , &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
@@ -1009,7 +1039,8 @@ static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)of_node_put (parent_np);if (IS_ERR (regmap))return ; - hw =at91rm9200_clk_register_usb (regmap, name, parent_name,NULL , divisors); + hw =at91rm9200_clk_register_usb (regmap, name,NULL , &AT91_CLK_PD_NAME (parent_name,0 ), + divisors);if (IS_ERR (hw))return ;
@@ -1056,7 +1087,8 @@ static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np) regmap_sfr =NULL ; } - hw =at91_clk_register_utmi (regmap_pmc, regmap_sfr, name, parent_name,NULL ); + hw =at91_clk_register_utmi (regmap_pmc, regmap_sfr, name,NULL , + &AT91_CLK_PD_NAME (parent_name,0 ));if (IS_ERR (hw))return ;
Signature · 1 line
2.43.0
PATCH v2 20/32 clk: at91: sam9x60: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch SAM9X60 clocks to use modern parent_hw and parent_data.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/sam9x60.c | 117 ++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 61 deletions(-)
drivers/clk/at91/sam9x60.c +56 -61
@@ -79,9 +79,9 @@ static const struct clk_pcr_layout sam9x60_pcr_layout = { .pid_mask = GENMASK(6, 0), }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } sam9x60_systemck[] = {
@@ -89,11 +89,11 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "qspick", .p = "masterck_div", .id = 19 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "uhpck", .id = 6 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, + { .n = "qspick", .id = 19 }, }; static const struct {
@@ -184,32 +184,17 @@ static const struct {static void __init sam9x60_pmc_setup (struct device_node *np) { +const char *td_slck_name ="td_slck" , *md_slck_name ="md_slck" ; +u8 td_slck_index =0 , md_slck_index =1 , main_xtal_index =2 ; +struct clk_hw *hw, *main_rc_hw, *main_osc_hw; +const char *main_xtal_name ="main_xtal" ;struct clk_range range =CLK_RANGE (0 ,0 ); -const char *td_slck_name, *md_slck_name, *mainxtal_name; +struct clk_parent_data parent_data[6 ];struct pmc_data *sam9x60_pmc; -const char *parent_names[6 ]; -struct clk_hw *main_osc_hw; +struct clk_hw *usbck_hw;struct regmap *regmap; -struct clk_hw *hw;int i; - i =of_property_match_string (np,"clock-names" ,"td_slck" ); -if (i <0 ) -return ; - - td_slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"md_slck" ); -if (i <0 ) -return ; - - md_slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); - regmap =device_node_to_regmap (np);if (IS_ERR (regmap))return ;
@@ -221,26 +206,28 @@ static void __init sam9x60_pmc_setup(struct device_node *np)if (!sam9x60_pmc)return ; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -50000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +50000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL ,0 ); + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), +0 );if (IS_ERR (hw)) goto err_free; - main_osc_hw = hw; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; sam9x60_pmc->chws[PMC_MAIN ] = hw; hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", - "mainck", sam9x60_pmc->chws[PMC_MAIN], + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]), + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]), 0, &plla_characteristics, &pll_frac_layout,/*
@@ -253,7 +240,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) goto err_free; hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", - "pllack_fracck", NULL, 0, &plla_characteristics, + NULL, hw, 0, &plla_characteristics, &pll_div_layout,/* * This feeds CPU. It should not
@@ -266,14 +253,15 @@ static void __init sam9x60_pmc_setup(struct device_node *np) sam9x60_pmc->chws[PMC_PLLACK ] = hw; hw =sam9x60_clk_register_frac_pll (regmap, &pmc_pll_lock,"upllck_fracck" , -"main_osc" , main_osc_hw,1 , - &upll_characteristics, + &AT91_CLK_PD_HW (main_osc_hw), +clk_hw_get_rate (main_osc_hw), +1 , &upll_characteristics, &pll_frac_layout,CLK_SET_RATE_GATE );if (IS_ERR (hw)) goto err_free; hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", - "upllck_fracck", NULL, 1, &upll_characteristics, + NULL, hw, 1, &upll_characteristics, &pll_div_layout, CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
@@ -283,17 +271,17 @@ static void __init sam9x60_pmc_setup(struct device_node *np) sam9x60_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = md_slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="pllack_divck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_PLLACK ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,3 , - parent_names,NULL , &sam9x60_master_layout, +NULL , parent_data, &sam9x60_master_layout, &mck_characteristics, &mck_lock);if (IS_ERR (hw)) goto err_free; hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , &sam9x60_master_layout, +NULL , &AT91_CLK_PD_HW (hw), &sam9x60_master_layout, &mck_characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );if (IS_ERR (hw))
@@ -301,26 +289,26 @@ static void __init sam9x60_pmc_setup(struct device_node *np) sam9x60_pmc->chws[PMC_MCK ] = hw; - parent_names[0 ] ="pllack_divck" ; - parent_names[1 ] ="upllck_divck" ; - parent_names[2 ] ="main_osc" ; - hw =sam9x60_clk_register_usb (regmap,"usbck" , parent_names,NULL ,3 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_UTMI ]); + parent_data[2 ] =AT91_CLK_PD_HW (main_osc_hw); + usbck_hw =sam9x60_clk_register_usb (regmap,"usbck" ,NULL , parent_data,3 ); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] = md_slck_name; - parent_names[1 ] = td_slck_name; - parent_names[2 ] ="mainck" ; - parent_names[3 ] ="masterck_div" ; - parent_names[4 ] ="pllack_divck" ; - parent_names[5 ] ="upllck_divck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_MAIN ]); + parent_data[3 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_MCK ]); + parent_data[4 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_PLLACK ]); + parent_data[5 ] =AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_UTMI ]);for (i =0 ; i <2 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,6 , i, +NULL , parent_data,6 , i, &sam9x60_programmable_layout,NULL );if (IS_ERR (hw))
@@ -329,9 +317,15 @@ static void __init sam9x60_pmc_setup(struct device_node *np) sam9x60_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + sam9x60_systemck[0 ].parent_hw = sam9x60_pmc->chws[PMC_MCK ]; + sam9x60_systemck[1 ].parent_hw = usbck_hw; + sam9x60_systemck[2 ].parent_hw = sam9x60_pmc->pchws[0 ]; + sam9x60_systemck[3 ].parent_hw = sam9x60_pmc->pchws[1 ]; + sam9x60_systemck[4 ].parent_hw = sam9x60_pmc->chws[PMC_MCK ];for (i =0 ; i <ARRAY_SIZE (sam9x60_systemck); i++) { hw =at91_clk_register_system (regmap, sam9x60_systemck[i].n, - sam9x60_systemck[i].p,NULL , +NULL , &AT91_CLK_PD_HW (sam9x60_systemck[i].parent_hw), sam9x60_systemck[i].id, sam9x60_systemck[i].flags);if (IS_ERR (hw))
@@ -344,7 +338,8 @@ static void __init sam9x60_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (sam9x60_pmc->chws[PMC_MCK ]), sam9x60_periphck[i].id, &range,INT_MIN , sam9x60_periphck[i].flags);
@@ -358,7 +353,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) hw =at91_clk_register_generated (regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_gck[i].n, - parent_names,NULL ,NULL ,6 , +NULL , parent_data,NULL ,6 , sam9x60_gck[i].id, &sam9x60_gck[i].r,INT_MIN );if (IS_ERR (hw))
Signature · 1 line
2.43.0
PATCH v2 21/32 clk: at91: sama5d2: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch SAMA5D2 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Extra time saved on registration is ~410us when running at 492MHz.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/sama5d2.c | 168 +++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 82 deletions(-)
drivers/clk/at91/sama5d2.c +86 -82
@@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d2_pcr_layout = { .pid_mask = GENMASK(6, 0), }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } sama5d2_systemck[] = {
@@ -47,14 +47,14 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "lcdck", .p = "masterck_div", .id = 3 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, - { .n = "iscck", .p = "masterck_div", .id = 18 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "lcdck", .id = 3 }, + { .n = "uhpck", .id = 6 }, + { .n = "udpck", .id = 7 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, + { .n = "pck2", .id = 10 }, + { .n = "iscck", .id = 18 }, }; static const struct {
@@ -164,25 +164,15 @@ static const struct clk_programmable_layout sama5d2_programmable_layout = {static void __init sama5d2_pmc_setup (struct device_node *np) { +struct clk_hw *hw, *audio_fracck_hw, *usbck_hw, *main_rc_hw, *main_osc_hw; +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +u8 slow_clk_index =0 , main_xtal_index =1 ;struct clk_range range =CLK_RANGE (0 ,0 ); -const char *slck_name, *mainxtal_name; -struct pmc_data *sama5d2_pmc; -const char *parent_names[6 ]; +struct clk_parent_data parent_data[6 ];struct regmap *regmap, *regmap_sfr; -struct clk_hw *hw; -int i; +struct pmc_data *sama5d2_pmc;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -195,51 +185,52 @@ static void __init sama5d2_pmc_setup(struct device_node *np)if (!sama5d2_pmc)return ; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -100000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +100000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , - bypass); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass); +if (IS_ERR (main_osc_hw)) goto err_free; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_MAIN ] = hw; - - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]),0 , &sama5d3_pll_layout, &plla_characteristics);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_plldiv (regmap,"plladivck" ,"pllack" ); + hw =at91_clk_register_plldiv (regmap,"plladivck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_audio_pll_frac (regmap,"audiopll_fracck" , -"mainck" ); -if (IS_ERR (hw)) + audio_fracck_hw =at91_clk_register_audio_pll_frac (regmap,"audiopll_fracck" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ])); +if (IS_ERR (audio_fracck_hw)) goto err_free; - hw =at91_clk_register_audio_pll_pad (regmap,"audiopll_padck" , -"audiopll_fracck" ); + hw =at91_clk_register_audio_pll_pad (regmap,"audiopll_padck" ,NULL , + &AT91_CLK_PD_HW (audio_fracck_hw));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_AUDIOPINCK ] = hw; - hw =at91_clk_register_audio_pll_pmc (regmap,"audiopll_pmcck" , -"audiopll_fracck" ); + hw =at91_clk_register_audio_pll_pmc (regmap,"audiopll_pmcck" ,NULL , + &AT91_CLK_PD_HW (audio_fracck_hw));if (IS_ERR (hw)) goto err_free;
@@ -249,25 +240,26 @@ static void __init sama5d2_pmc_setup(struct device_node *np)if (IS_ERR (regmap_sfr)) regmap_sfr =NULL ; - hw =at91_clk_register_utmi (regmap, regmap_sfr,"utmick" ,"mainck" ,NULL ); + hw =at91_clk_register_utmi (regmap, regmap_sfr,"utmick" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , + hw =at91_clk_register_master_div (regmap,"masterck_div" ,NULL , + &AT91_CLK_PD_HW (hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );
@@ -276,31 +268,32 @@ static void __init sama5d2_pmc_setup(struct device_node *np) sama5d2_pmc->chws[PMC_MCK ] = hw; - hw =at91_clk_register_h32mx (regmap,"h32mxck" ,"masterck_div" ); + hw =at91_clk_register_h32mx (regmap,"h32mxck" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_MCK2 ] = hw; - parent_names[0 ] ="plladivck" ; - parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); + usbck_hw =at91sam9x5_clk_register_usb (regmap,"usbck" ,NULL , parent_data,2 ); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; - parent_names[5 ] ="audiopll_pmcck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]); + parent_data[5 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_AUDIOPLLCK ]);for (i =0 ; i <3 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,6 , i, +NULL , parent_data,6 , i, &sama5d2_programmable_layout,NULL );if (IS_ERR (hw))
@@ -309,9 +302,18 @@ static void __init sama5d2_pmc_setup(struct device_node *np) sama5d2_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + sama5d2_systemck[0 ].parent_hw = sama5d2_pmc->chws[PMC_MCK ]; + sama5d2_systemck[1 ].parent_hw = sama5d2_pmc->chws[PMC_MCK ]; + sama5d2_systemck[2 ].parent_hw = usbck_hw; + sama5d2_systemck[3 ].parent_hw = usbck_hw; + sama5d2_systemck[4 ].parent_hw = sama5d2_pmc->pchws[0 ]; + sama5d2_systemck[5 ].parent_hw = sama5d2_pmc->pchws[1 ]; + sama5d2_systemck[6 ].parent_hw = sama5d2_pmc->pchws[2 ]; + sama5d2_systemck[7 ].parent_hw = sama5d2_pmc->chws[PMC_MCK ];for (i =0 ; i <ARRAY_SIZE (sama5d2_systemck); i++) { - hw =at91_clk_register_system (regmap, sama5d2_systemck[i].n, - sama5d2_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, sama5d2_systemck[i].n,NULL , + &AT91_CLK_PD_HW (sama5d2_systemck[i].parent_hw), sama5d2_systemck[i].id, sama5d2_systemck[i].flags);if (IS_ERR (hw))
@@ -324,7 +326,8 @@ static void __init sama5d2_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]), sama5d2_periphck[i].id, &range,INT_MIN , sama5d2_periphck[i].flags);
@@ -338,7 +341,8 @@ static void __init sama5d2_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periph32ck[i].n, -"h32mxck" ,NULL , +NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK2 ]), sama5d2_periph32ck[i].id, &sama5d2_periph32ck[i].r,INT_MIN ,0 );
@@ -348,17 +352,17 @@ static void __init sama5d2_pmc_setup(struct device_node *np) sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw; } - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; - parent_names[5 ] ="audiopll_pmcck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]); + parent_data[5 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_AUDIOPLLCK ]);for (i =0 ; i <ARRAY_SIZE (sama5d2_gck); i++) { hw =at91_clk_register_generated (regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_gck[i].n, - parent_names,NULL ,NULL ,6 , +NULL , parent_data,NULL ,6 , sama5d2_gck[i].id, &sama5d2_gck[i].r, sama5d2_gck[i].chg_pid);
@@ -369,19 +373,19 @@ static void __init sama5d2_pmc_setup(struct device_node *np) }if (regmap_sfr) { - parent_names[0 ] ="i2s0_clk" ; - parent_names[1 ] ="i2s0_gclk" ; + parent_data[0 ] =AT91_CLK_PD_HW (sama5d2_pmc->phws[54 ]);/* i2s0_clk */ + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->ghws[54 ]);/* i2s0_gclk */ hw =at91_clk_i2s_mux_register (regmap_sfr,"i2s0_muxclk" , - parent_names,2 ,0 ); +NULL , parent_data,2 ,0 );if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_I2S0_MUX ] = hw; - parent_names[0 ] ="i2s1_clk" ; - parent_names[1 ] ="i2s1_gclk" ; + parent_data[0 ] =AT91_CLK_PD_HW (sama5d2_pmc->phws[55 ]);/* i2s1_clk */ + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->ghws[55 ]);/* i2s1_gclk */ hw =at91_clk_i2s_mux_register (regmap_sfr,"i2s1_muxclk" , - parent_names,2 ,1 ); +NULL , parent_data,2 ,1 );if (IS_ERR (hw)) goto err_free;
Signature · 1 line
2.43.0
Claudiu Beznea
maintainerRe: [PATCH v2 21/32] clk: at91: sama5d2: switch to parent_hw and parent_data
Hi, Ryan,
Quoted 6 lines · On 24.06.2025 18:08, [email protected] wrote:
From: Claudiu Beznea <[email protected]>
Switch SAMA5D2 clocks to use
parent_hwandparent_data. Havingparent_hwinstead of parent names improves to clock registration speed and re-parenting. Extra time saved on registration is ~410us when running at 492MHz.
Have you re-check this? I expected to no longer be valid.
Quoted 322 lines
Signed-off-by Claudiu Beznea <[email protected]>Signed-off-by Ryan Wanner <[email protected]>--- drivers/clk/at91/sama5d2.c | 168 +++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 82 deletions(-)drivers/clk/at91/sama5d2.c +86
-82@@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d2_pcr_layout = { .pid_mask = GENMASK(6, 0), }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } sama5d2_systemck[] = {@@ -47,14 +47,14 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "lcdck", .p = "masterck_div", .id = 3 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, - { .n = "iscck", .p = "masterck_div", .id = 18 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "lcdck", .id = 3 }, + { .n = "uhpck", .id = 6 }, + { .n = "udpck", .id = 7 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, + { .n = "pck2", .id = 10 }, + { .n = "iscck", .id = 18 }, }; static const struct {@@ -164,25 +164,15 @@ static const struct clk_programmable_layout sama5d2_programmable_layout = {static void __init sama5d2_pmc_setup (struct device_node *np) { +struct clk_hw *hw, *audio_fracck_hw, *usbck_hw, *main_rc_hw, *main_osc_hw; +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +u8 slow_clk_index =0 , main_xtal_index =1 ;struct clk_range range =CLK_RANGE (0 ,0 ); -const char *slck_name, *mainxtal_name; -struct pmc_data *sama5d2_pmc; -const char *parent_names[6 ]; +struct clk_parent_data parent_data[6 ];struct regmap *regmap, *regmap_sfr; -struct clk_hw *hw; -int i; +struct pmc_data *sama5d2_pmc;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))@@ -195,51 +185,52 @@ static void __init sama5d2_pmc_setup(struct device_node *np)if (!sama5d2_pmc)return ; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -100000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +100000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , - bypass); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass); +if (IS_ERR (main_osc_hw)) goto err_free; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_MAIN ] = hw; - - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]),0 , &sama5d3_pll_layout, &plla_characteristics);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_plldiv (regmap,"plladivck" ,"pllack" ); + hw =at91_clk_register_plldiv (regmap,"plladivck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_audio_pll_frac (regmap,"audiopll_fracck" , -"mainck" ); -if (IS_ERR (hw)) + audio_fracck_hw =at91_clk_register_audio_pll_frac (regmap,"audiopll_fracck" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ])); +if (IS_ERR (audio_fracck_hw)) goto err_free; - hw =at91_clk_register_audio_pll_pad (regmap,"audiopll_padck" , -"audiopll_fracck" ); + hw =at91_clk_register_audio_pll_pad (regmap,"audiopll_padck" ,NULL , + &AT91_CLK_PD_HW (audio_fracck_hw));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_AUDIOPINCK ] = hw; - hw =at91_clk_register_audio_pll_pmc (regmap,"audiopll_pmcck" , -"audiopll_fracck" ); + hw =at91_clk_register_audio_pll_pmc (regmap,"audiopll_pmcck" ,NULL , + &AT91_CLK_PD_HW (audio_fracck_hw));if (IS_ERR (hw)) goto err_free;@@ -249,25 +240,26 @@ static void __init sama5d2_pmc_setup(struct device_node *np)if (IS_ERR (regmap_sfr)) regmap_sfr =NULL ; - hw =at91_clk_register_utmi (regmap, regmap_sfr,"utmick" ,"mainck" ,NULL ); + hw =at91_clk_register_utmi (regmap, regmap_sfr,"utmick" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , + hw =at91_clk_register_master_div (regmap,"masterck_div" ,NULL , + &AT91_CLK_PD_HW (hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );@@ -276,31 +268,32 @@ static void __init sama5d2_pmc_setup(struct device_node *np) sama5d2_pmc->chws[PMC_MCK ] = hw; - hw =at91_clk_register_h32mx (regmap,"h32mxck" ,"masterck_div" ); + hw =at91_clk_register_h32mx (regmap,"h32mxck" ,NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]));if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_MCK2 ] = hw; - parent_names[0 ] ="plladivck" ; - parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); + usbck_hw =at91sam9x5_clk_register_usb (regmap,"usbck" ,NULL , parent_data,2 ); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; - parent_names[5 ] ="audiopll_pmcck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]); + parent_data[5 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_AUDIOPLLCK ]);for (i =0 ; i <3 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,6 , i, +NULL , parent_data,6 , i, &sama5d2_programmable_layout,NULL );if (IS_ERR (hw))@@ -309,9 +302,18 @@ static void __init sama5d2_pmc_setup(struct device_node *np) sama5d2_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + sama5d2_systemck[0 ].parent_hw = sama5d2_pmc->chws[PMC_MCK ]; + sama5d2_systemck[1 ].parent_hw = sama5d2_pmc->chws[PMC_MCK ]; + sama5d2_systemck[2 ].parent_hw = usbck_hw; + sama5d2_systemck[3 ].parent_hw = usbck_hw; + sama5d2_systemck[4 ].parent_hw = sama5d2_pmc->pchws[0 ]; + sama5d2_systemck[5 ].parent_hw = sama5d2_pmc->pchws[1 ]; + sama5d2_systemck[6 ].parent_hw = sama5d2_pmc->pchws[2 ]; + sama5d2_systemck[7 ].parent_hw = sama5d2_pmc->chws[PMC_MCK ];for (i =0 ; i <ARRAY_SIZE (sama5d2_systemck); i++) { - hw =at91_clk_register_system (regmap, sama5d2_systemck[i].n, - sama5d2_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, sama5d2_systemck[i].n,NULL , + &AT91_CLK_PD_HW (sama5d2_systemck[i].parent_hw), sama5d2_systemck[i].id, sama5d2_systemck[i].flags);if (IS_ERR (hw))@@ -324,7 +326,8 @@ static void __init sama5d2_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]), sama5d2_periphck[i].id, &range,INT_MIN , sama5d2_periphck[i].flags);@@ -338,7 +341,8 @@ static void __init sama5d2_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periph32ck[i].n, -"h32mxck" ,NULL , +NULL , + &AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK2 ]), sama5d2_periph32ck[i].id, &sama5d2_periph32ck[i].r,INT_MIN ,0 );@@ -348,17 +352,17 @@ static void __init sama5d2_pmc_setup(struct device_node *np) sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw; } - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; - parent_names[5 ] ="audiopll_pmcck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_MCK ]); + parent_data[5 ] =AT91_CLK_PD_HW (sama5d2_pmc->chws[PMC_AUDIOPLLCK ]);for (i =0 ; i <ARRAY_SIZE (sama5d2_gck); i++) { hw =at91_clk_register_generated (regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_gck[i].n, - parent_names,NULL ,NULL ,6 , +NULL , parent_data,NULL ,6 , sama5d2_gck[i].id, &sama5d2_gck[i].r, sama5d2_gck[i].chg_pid);@@ -369,19 +373,19 @@ static void __init sama5d2_pmc_setup(struct device_node *np) }if (regmap_sfr) { - parent_names[0 ] ="i2s0_clk" ; - parent_names[1 ] ="i2s0_gclk" ; + parent_data[0 ] =AT91_CLK_PD_HW (sama5d2_pmc->phws[54 ]);/* i2s0_clk */ + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->ghws[54 ]);/* i2s0_gclk */ hw =at91_clk_i2s_mux_register (regmap_sfr,"i2s0_muxclk" , - parent_names,2 ,0 ); +NULL , parent_data,2 ,0 );if (IS_ERR (hw)) goto err_free; sama5d2_pmc->chws[PMC_I2S0_MUX ] = hw; - parent_names[0 ] ="i2s1_clk" ; - parent_names[1 ] ="i2s1_gclk" ; + parent_data[0 ] =AT91_CLK_PD_HW (sama5d2_pmc->phws[55 ]);/* i2s1_clk */ + parent_data[1 ] =AT91_CLK_PD_HW (sama5d2_pmc->ghws[55 ]);/* i2s1_gclk */ hw =at91_clk_i2s_mux_register (regmap_sfr,"i2s1_muxclk" , - parent_names,2 ,1 ); +NULL , parent_data,2 ,1 );if (IS_ERR (hw)) goto err_free;
PATCH v2 22/32 clk: at91: sama5d3: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch SAMA5D3 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/sama5d3.c | 122 +++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 59 deletions(-)
drivers/clk/at91/sama5d3.c +63 -59
@@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d3_pcr_layout = { .div_mask = GENMASK(17, 16), }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } sama5d3_systemck[] = {
@@ -47,14 +47,14 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "lcdck", .p = "masterck_div", .id = 3 }, - { .n = "smdck", .p = "smdclk", .id = 4 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "lcdck", .id = 3 }, + { .n = "smdck", .id = 4 }, + { .n = "uhpck", .id = 6 }, + { .n = "udpck", .id = 7 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, + { .n = "pck2", .id = 10 }, }; static const struct {
@@ -114,24 +114,15 @@ static const struct {static void __init sama5d3_pmc_setup (struct device_node *np) { -const char *slck_name, *mainxtal_name; +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw; +u8 slow_clk_index =0 , main_xtal_index =1 ; +struct clk_hw *smdck_hw, *usbck_hw, *hw; +struct clk_parent_data parent_data[5 ];struct pmc_data *sama5d3_pmc; -const char *parent_names[5 ];struct regmap *regmap; -struct clk_hw *hw; -int i;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -143,54 +134,55 @@ static void __init sama5d3_pmc_setup(struct device_node *np)if (!sama5d3_pmc)return ; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -50000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +50000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , - bypass); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass); +if (IS_ERR (main_osc_hw)) goto err_free; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + mainck_hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 ); +if (IS_ERR (mainck_hw)) goto err_free; - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , &AT91_CLK_PD_HW (mainck_hw),0 , &sama5d3_pll_layout, &plla_characteristics);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_plldiv (regmap,"plladivck" ,"pllack" ); + hw =at91_clk_register_plldiv (regmap,"plladivck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; sama5d3_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,"mainck" ,NULL ); + hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,NULL , &AT91_CLK_PD_HW (mainck_hw));if (IS_ERR (hw)) goto err_free; sama5d3_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (mainck_hw); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_UTMI ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock);if (IS_ERR (hw)) goto err_free; hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , +NULL , &AT91_CLK_PD_HW (hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );
@@ -199,28 +191,30 @@ static void __init sama5d3_pmc_setup(struct device_node *np) sama5d3_pmc->chws[PMC_MCK ] = hw; - parent_names[0 ] ="plladivck" ; - parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_UTMI ]); + usbck_hw =at91sam9x5_clk_register_usb (regmap,"usbck" ,NULL , parent_data,2 ); +if (IS_ERR (usbck_hw)) goto err_free; - hw =at91sam9x5_clk_register_smd (regmap,"smdclk" , parent_names,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_UTMI ]); + smdck_hw =at91sam9x5_clk_register_smd (regmap,"smdclk" ,NULL , parent_data,2 ); +if (IS_ERR (smdck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (mainck_hw); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (sama5d3_pmc->chws[PMC_MCK ]);for (i =0 ; i <3 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,5 , i, +NULL , parent_data,5 , i, &at91sam9x5_programmable_layout,NULL );if (IS_ERR (hw))
@@ -229,9 +223,18 @@ static void __init sama5d3_pmc_setup(struct device_node *np) sama5d3_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + sama5d3_systemck[0 ].parent_hw = sama5d3_pmc->chws[PMC_MCK ]; + sama5d3_systemck[1 ].parent_hw = sama5d3_pmc->chws[PMC_MCK ]; + sama5d3_systemck[2 ].parent_hw = smdck_hw; + sama5d3_systemck[3 ].parent_hw = usbck_hw; + sama5d3_systemck[4 ].parent_hw = usbck_hw; + sama5d3_systemck[5 ].parent_hw = sama5d3_pmc->pchws[0 ]; + sama5d3_systemck[6 ].parent_hw = sama5d3_pmc->pchws[1 ]; + sama5d3_systemck[7 ].parent_hw = sama5d3_pmc->pchws[2 ];for (i =0 ; i <ARRAY_SIZE (sama5d3_systemck); i++) { - hw =at91_clk_register_system (regmap, sama5d3_systemck[i].n, - sama5d3_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, sama5d3_systemck[i].n,NULL , + &AT91_CLK_PD_HW (sama5d3_systemck[i].parent_hw), sama5d3_systemck[i].id, sama5d3_systemck[i].flags);if (IS_ERR (hw))
@@ -244,7 +247,8 @@ static void __init sama5d3_pmc_setup(struct device_node *np) hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d3_pcr_layout, sama5d3_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]), sama5d3_periphck[i].id, &sama5d3_periphck[i].r, INT_MIN,
Signature · 1 line
2.43.0
PATCH v2 23/32 clk: at91: sama5d4: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch SAMA5D4 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/sama5d4.c | 129 +++++++++++++++++++------------------ 1 file changed, 66 insertions(+), 63 deletions(-)
drivers/clk/at91/sama5d4.c +66 -63
@@ -36,9 +36,9 @@ static const struct clk_pcr_layout sama5d4_pcr_layout = { .pid_mask = GENMASK(6, 0), }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } sama5d4_systemck[] = {
@@ -46,14 +46,14 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "lcdck", .p = "masterck_div", .id = 3 }, - { .n = "smdck", .p = "smdclk", .id = 4 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "lcdck", .id = 3 }, + { .n = "smdck", .id = 4 }, + { .n = "uhpck", .id = 6 }, + { .n = "udpck", .id = 7 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, + { .n = "pck2", .id = 10 }, }; static const struct {
@@ -128,25 +128,16 @@ static const struct {static void __init sama5d4_pmc_setup (struct device_node *np) { +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw; +u8 slow_clk_index =0 , main_xtal_index =1 ; +struct clk_hw *smdck_hw, *usbck_hw, *hw;struct clk_range range =CLK_RANGE (0 ,0 ); -const char *slck_name, *mainxtal_name; +struct clk_parent_data parent_data[5 ];struct pmc_data *sama5d4_pmc; -const char *parent_names[5 ];struct regmap *regmap; -struct clk_hw *hw; -int i;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -158,54 +149,54 @@ static void __init sama5d4_pmc_setup(struct device_node *np)if (!sama5d4_pmc)return ; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -100000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +100000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , - bypass); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass); +if (IS_ERR (main_osc_hw)) goto err_free; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + mainck_hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , &AT91_CLK_PD_HW (mainck_hw),0 , &sama5d3_pll_layout, &plla_characteristics);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_plldiv (regmap,"plladivck" ,"pllack" ); + hw =at91_clk_register_plldiv (regmap,"plladivck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; sama5d4_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,"mainck" ,NULL ); + hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,NULL , &AT91_CLK_PD_HW (mainck_hw));if (IS_ERR (hw)) goto err_free; sama5d4_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (mainck_hw); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_UTMI ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , + hw =at91_clk_register_master_div (regmap,"masterck_div" ,NULL , &AT91_CLK_PD_HW (hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );
@@ -214,36 +205,37 @@ static void __init sama5d4_pmc_setup(struct device_node *np) sama5d4_pmc->chws[PMC_MCK ] = hw; - hw =at91_clk_register_h32mx (regmap,"h32mxck" ,"masterck_div" ); + hw =at91_clk_register_h32mx (regmap,"h32mxck" ,NULL , + &AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_MCK ]));if (IS_ERR (hw)) goto err_free; sama5d4_pmc->chws[PMC_MCK2 ] = hw; - parent_names[0 ] ="plladivck" ; - parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_UTMI ]); + usbck_hw =at91sam9x5_clk_register_usb (regmap,"usbck" ,NULL , parent_data,2 ); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] ="plladivck" ; - parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_smd (regmap,"smdclk" , parent_names,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_UTMI ]); + smdck_hw =at91sam9x5_clk_register_smd (regmap,"smdclk" ,NULL , parent_data,2 ); +if (IS_ERR (smdck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (mainck_hw); + parent_data[2 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_MCK ]);for (i =0 ; i <3 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,5 , i, +NULL , parent_data,5 , i, &at91sam9x5_programmable_layout,NULL );if (IS_ERR (hw))
@@ -252,9 +244,18 @@ static void __init sama5d4_pmc_setup(struct device_node *np) sama5d4_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + sama5d4_systemck[0 ].parent_hw = sama5d4_pmc->chws[PMC_MCK ]; + sama5d4_systemck[1 ].parent_hw = sama5d4_pmc->chws[PMC_MCK ]; + sama5d4_systemck[2 ].parent_hw = smdck_hw; + sama5d4_systemck[3 ].parent_hw = usbck_hw; + sama5d4_systemck[4 ].parent_hw = usbck_hw; + sama5d4_systemck[5 ].parent_hw = sama5d4_pmc->pchws[0 ]; + sama5d4_systemck[6 ].parent_hw = sama5d4_pmc->pchws[1 ]; + sama5d4_systemck[7 ].parent_hw = sama5d4_pmc->pchws[2 ];for (i =0 ; i <ARRAY_SIZE (sama5d4_systemck); i++) { - hw =at91_clk_register_system (regmap, sama5d4_systemck[i].n, - sama5d4_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, sama5d4_systemck[i].n,NULL , + &AT91_CLK_PD_HW (sama5d4_systemck[i].parent_hw), sama5d4_systemck[i].id, sama5d4_systemck[i].flags);if (IS_ERR (hw))
@@ -267,7 +268,8 @@ static void __init sama5d4_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_MCK ]), sama5d4_periphck[i].id, &range,INT_MIN , sama5d4_periphck[i].flags);
@@ -281,7 +283,8 @@ static void __init sama5d4_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periph32ck[i].n, -"h32mxck" ,NULL , +NULL , + &AT91_CLK_PD_HW (sama5d4_pmc->chws[PMC_MCK2 ]), sama5d4_periph32ck[i].id, &range,INT_MIN ,0 );if (IS_ERR (hw))
Signature · 1 line
2.43.0
PATCH v2 24/32 clk: at91: at91sam9x5: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch AT91SAM9X5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/at91sam9x5.c | 125 ++++++++++++++++++---------------- 1 file changed, 65 insertions(+), 60 deletions(-)
drivers/clk/at91/at91sam9x5.c +65 -60
@@ -38,9 +38,9 @@ static const struct clk_pll_characteristics plla_characteristics = { .out = plla_out, }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } at91sam9x5_systemck[] = {
@@ -48,12 +48,12 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "smdck", .p = "smdclk", .id = 4 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "smdck", .id = 4 }, + { .n = "uhpck", .id = 6 }, + { .n = "udpck", .id = 7 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, }; static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
@@ -133,25 +133,16 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,const struct pck *extra_pcks, bool has_lcdck) { + const char *slow_clk_name = "slowck", *main_xtal_name = "main_xtal"; +struct clk_hw *main_rc_hw, *main_osc_hw, *hw; +u8 slow_clk_index =0 , main_xtal_index =0 ;struct clk_range range =CLK_RANGE (0 ,0 ); -const char *slck_name, *mainxtal_name; +struct clk_parent_data parent_data[6 ]; +struct clk_hw *smdck_hw, *usbck_hw;struct pmc_data *at91sam9x5_pmc; -const char *parent_names[6 ];struct regmap *regmap; -struct clk_hw *hw; -int i;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -162,56 +153,59 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,if (!at91sam9x5_pmc)return ; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -50000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +50000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , - bypass); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass); +if (IS_ERR (main_osc_hw)) goto err_free; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; at91sam9x5_pmc->chws[PMC_MAIN ] = hw; - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MAIN ]),0 , &at91rm9200_pll_layout, &plla_characteristics);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_plldiv (regmap,"plladivck" ,"pllack" ); + hw =at91_clk_register_plldiv (regmap,"plladivck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; at91sam9x5_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,"mainck" ,NULL ); + hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,NULL , + &AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MAIN ]));if (IS_ERR (hw)) goto err_free; at91sam9x5_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_UTMI ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , + hw =at91_clk_register_master_div (regmap,"masterck_div" ,NULL , + &AT91_CLK_PD_HW (hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );
@@ -220,28 +214,30 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, at91sam9x5_pmc->chws[PMC_MCK ] = hw; - parent_names[0 ] ="plladivck" ; - parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_UTMI ]); + usbck_hw =at91sam9x5_clk_register_usb (regmap,"usbck" ,NULL , parent_data,2 ); +if (IS_ERR (usbck_hw)) goto err_free; - hw =at91sam9x5_clk_register_smd (regmap,"smdclk" , parent_names,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_UTMI ]); + smdck_hw =at91sam9x5_clk_register_smd (regmap,"smdclk" ,NULL , parent_data,2 ); +if (IS_ERR (smdck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MCK ]);for (i =0 ; i <2 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,5 , i, +NULL , parent_data,5 , i, &at91sam9x5_programmable_layout,NULL );if (IS_ERR (hw))
@@ -250,9 +246,16 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, at91sam9x5_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + at91sam9x5_systemck[0 ].parent_hw = at91sam9x5_pmc->chws[PMC_MCK ]; + at91sam9x5_systemck[1 ].parent_hw = smdck_hw; + at91sam9x5_systemck[2 ].parent_hw = usbck_hw; + at91sam9x5_systemck[3 ].parent_hw = usbck_hw; + at91sam9x5_systemck[4 ].parent_hw = at91sam9x5_pmc->pchws[0 ]; + at91sam9x5_systemck[5 ].parent_hw = at91sam9x5_pmc->pchws[1 ];for (i =0 ; i <ARRAY_SIZE (at91sam9x5_systemck); i++) { - hw =at91_clk_register_system (regmap, at91sam9x5_systemck[i].n, - at91sam9x5_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, at91sam9x5_systemck[i].n,NULL , + &AT91_CLK_PD_HW (at91sam9x5_systemck[i].parent_hw), at91sam9x5_systemck[i].id, at91sam9x5_systemck[i].flags);if (IS_ERR (hw))
@@ -262,8 +265,8 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, }if (has_lcdck) { - hw =at91_clk_register_system (regmap,"lcdck" ,"masterck_div" , -NULL ,3 ,0 ); + hw =at91_clk_register_system (regmap,"lcdck" ,NULL , + &AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MCK ]),3 ,0 );if (IS_ERR (hw)) goto err_free;
@@ -274,7 +277,8 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, at91sam9x5_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MCK ]), at91sam9x5_periphck[i].id, &range,INT_MIN ,0 );if (IS_ERR (hw))
@@ -287,7 +291,8 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, extra_pcks[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (at91sam9x5_pmc->chws[PMC_MCK ]), extra_pcks[i].id, &range,INT_MIN ,0 );if (IS_ERR (hw))
Signature · 1 line
2.43.0
PATCH v2 25/32 clk: at91: at91rm9200: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch AT91RM9200 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/at91rm9200.c | 95 ++++++++++++++++++----------------- 1 file changed, 49 insertions(+), 46 deletions(-)
drivers/clk/at91/at91rm9200.c +49 -46
@@ -11,7 +11,7 @@ static DEFINE_SPINLOCK(rm9200_mck_lock);struct sck {char *n; -char *p; +struct clk_hw *parent_hw;u8 id; };
@@ -39,13 +39,13 @@ static const struct clk_pll_characteristics rm9200_pll_characteristics = { .out = rm9200_pll_out, }; -static const struct sck at91rm9200_systemck[] = { - { .n ="udpck" , .p ="usbck" , .id =1 }, - { .n ="uhpck" , .p ="usbck" , .id =4 }, - { .n ="pck0" , .p ="prog0" , .id =8 }, - { .n ="pck1" , .p ="prog1" , .id =9 }, - { .n ="pck2" , .p ="prog2" , .id =10 }, - { .n ="pck3" , .p ="prog3" , .id =11 }, +static struct sck at91rm9200_systemck[] = { + { .n ="udpck" , .id =1 }, + { .n ="uhpck" , .id =4 }, + { .n ="pck0" , .id =8 }, + { .n ="pck1" , .id =9 }, + { .n ="pck2" , .id =10 }, + { .n ="pck3" , .id =11 }, };static const struct pck at91rm9200_periphck[] = {
@@ -76,25 +76,15 @@ static const struct pck at91rm9200_periphck[] = {static void __init at91rm9200_pmc_setup (struct device_node *np) { -const char *slowxtal_name, *mainxtal_name; +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +struct clk_hw *usbck_hw, *main_osc_hw, *hw; +u8 slow_clk_index =0 , main_xtal_index =1 ; +struct clk_parent_data parent_data[6 ];struct pmc_data *at91rm9200_pmc;u32 usb_div[] = {1 ,2 ,0 ,0 }; -const char *parent_names[6 ];struct regmap *regmap; -struct clk_hw *hw; -int i;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_xtal" ); -if (i <0 ) -return ; - - slowxtal_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -108,18 +98,21 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , - bypass); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass); +if (IS_ERR (main_osc_hw)) goto err_free; - hw =at91_clk_register_rm9200_main (regmap,"mainck" ,"main_osc" ,NULL ); + hw =at91_clk_register_rm9200_main (regmap,"mainck" ,NULL , + &AT91_CLK_PD_HW (main_osc_hw));if (IS_ERR (hw)) goto err_free; at91rm9200_pmc->chws[PMC_MAIN ] = hw; - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_MAIN ]),0 , &at91rm9200_pll_layout, &rm9200_pll_characteristics);if (IS_ERR (hw))
@@ -127,7 +120,8 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) at91rm9200_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_pll (regmap,"pllbck" ,"mainck" ,1 , + hw =at91_clk_register_pll (regmap,"pllbck" ,NULL , + &AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_MAIN ]),1 , &at91rm9200_pll_layout, &rm9200_pll_characteristics);if (IS_ERR (hw))
@@ -135,20 +129,19 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) at91rm9200_pmc->chws[PMC_PLLBCK ] = hw; - parent_names[0 ] = slowxtal_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="pllack" ; - parent_names[3 ] ="pllbck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_PLLBCK ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , + hw =at91_clk_register_master_div (regmap,"masterck_div" ,NULL , &AT91_CLK_PD_HW (hw), &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock,CLK_SET_RATE_GATE ,0 );
@@ -157,21 +150,23 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) at91rm9200_pmc->chws[PMC_MCK ] = hw; - hw =at91rm9200_clk_register_usb (regmap,"usbck" ,"pllbck" ,NULL , usb_div); -if (IS_ERR (hw)) + usbck_hw =at91rm9200_clk_register_usb (regmap,"usbck" ,NULL , + &AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_PLLBCK ]), + usb_div); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] = slowxtal_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="pllack" ; - parent_names[3 ] ="pllbck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_PLLBCK ]);for (i =0 ; i <4 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,4 , i, +NULL , parent_data,4 , i, &at91rm9200_programmable_layout,NULL );if (IS_ERR (hw))
@@ -180,9 +175,16 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) at91rm9200_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + at91rm9200_systemck[0 ].parent_hw = usbck_hw; + at91rm9200_systemck[1 ].parent_hw = usbck_hw; + at91rm9200_systemck[2 ].parent_hw = at91rm9200_pmc->pchws[0 ]; + at91rm9200_systemck[3 ].parent_hw = at91rm9200_pmc->pchws[1 ]; + at91rm9200_systemck[4 ].parent_hw = at91rm9200_pmc->pchws[2 ]; + at91rm9200_systemck[5 ].parent_hw = at91rm9200_pmc->pchws[3 ];for (i =0 ; i <ARRAY_SIZE (at91rm9200_systemck); i++) { - hw =at91_clk_register_system (regmap, at91rm9200_systemck[i].n, - at91rm9200_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, at91rm9200_systemck[i].n,NULL , + &AT91_CLK_PD_HW (at91rm9200_systemck[i].parent_hw), at91rm9200_systemck[i].id,0 );if (IS_ERR (hw)) goto err_free;
@@ -193,7 +195,8 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)for (i =0 ; i <ARRAY_SIZE (at91rm9200_periphck); i++) { hw =at91_clk_register_peripheral (regmap, at91rm9200_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (at91rm9200_pmc->chws[PMC_MCK ]), at91rm9200_periphck[i].id);if (IS_ERR (hw)) goto err_free;
Signature · 1 line
2.43.0
PATCH v2 26/32 clk: at91: at91sam9260: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch AT91SAM92600 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/at91sam9260.c | 136 +++++++++++++++++---------------- 1 file changed, 70 insertions(+), 66 deletions(-)
drivers/clk/at91/at91sam9260.c +70 -66
@@ -9,7 +9,7 @@struct sck {char *n; -char *p; +struct clk_hw *parent_hw;u8 id; };
@@ -24,7 +24,7 @@ struct at91sam926x_data {const struct clk_pll_layout *pllb_layout;const struct clk_pll_characteristics *pllb_characteristics;const struct clk_master_characteristics *mck_characteristics; -const struct sck *sck; +struct sck *sck;const struct pck *pck;u8 num_sck;u8 num_pck;
@@ -72,11 +72,11 @@ static const struct clk_pll_characteristics sam9260_pllb_characteristics = { .out = sam9260_pllb_out, }; -static const struct sck at91sam9260_systemck[] = { - { .n ="uhpck" , .p ="usbck" , .id =6 }, - { .n ="udpck" , .p ="usbck" , .id =7 }, - { .n ="pck0" , .p ="prog0" , .id =8 }, - { .n ="pck1" , .p ="prog1" , .id =9 }, +static struct sck at91sam9260_systemck[] = { + { .n ="uhpck" , .id =6 }, + { .n ="udpck" , .id =7 }, + { .n ="pck0" , .id =8 }, + { .n ="pck1" , .id =9 }, };static const struct pck at91sam9260_periphck[] = {
@@ -213,15 +213,15 @@ static const struct clk_pll_characteristics sam9261_pllb_characteristics = { .out = sam9261_pllb_out, }; -static const struct sck at91sam9261_systemck[] = { - { .n ="uhpck" , .p ="usbck" , .id =6 }, - { .n ="udpck" , .p ="usbck" , .id =7 }, - { .n ="pck0" , .p ="prog0" , .id =8 }, - { .n ="pck1" , .p ="prog1" , .id =9 }, - { .n ="pck2" , .p ="prog2" , .id =10 }, - { .n ="pck3" , .p ="prog3" , .id =11 }, - { .n ="hclk0" , .p ="masterck_div" , .id =16 }, - { .n ="hclk1" , .p ="masterck_div" , .id =17 }, +static struct sck at91sam9261_systemck[] = { + { .n ="uhpck" , .id =6 }, + { .n ="udpck" , .id =7 }, + { .n ="pck0" , .id =8 }, + { .n ="pck1" , .id =9 }, + { .n ="pck2" , .id =10 }, + { .n ="pck3" , .id =11 }, + { .n ="hclk0" , .id =16 }, + { .n ="hclk1" , .id =17 }, };static const struct pck at91sam9261_periphck[] = {
@@ -277,13 +277,13 @@ static const struct clk_pll_characteristics sam9263_pll_characteristics = { .out = sam9260_plla_out, }; -static const struct sck at91sam9263_systemck[] = { - { .n ="uhpck" , .p ="usbck" , .id =6 }, - { .n ="udpck" , .p ="usbck" , .id =7 }, - { .n ="pck0" , .p ="prog0" , .id =8 }, - { .n ="pck1" , .p ="prog1" , .id =9 }, - { .n ="pck2" , .p ="prog2" , .id =10 }, - { .n ="pck3" , .p ="prog3" , .id =11 }, +static struct sck at91sam9263_systemck[] = { + { .n ="uhpck" , .id =6 }, + { .n ="udpck" , .id =7 }, + { .n ="pck0" , .id =8 }, + { .n ="pck1" , .id =9 }, + { .n ="pck2" , .id =10 }, + { .n ="pck3" , .id =11 }, };static const struct pck at91sam9263_periphck[] = {
@@ -329,26 +329,15 @@ static struct at91sam926x_data at91sam9263_data = {static void __init at91sam926x_pmc_setup (struct device_node *np,struct at91sam926x_data *data) { -const char *slowxtal_name, *mainxtal_name; +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +u8 slow_clk_index =0 , main_xtal_index =1 ; +struct clk_parent_data parent_data[4 ];struct pmc_data *at91sam9260_pmc;u32 usb_div[] = {1 ,2 ,4 ,0 }; -const char *parent_names[6 ]; -const char *slck_name; +struct clk_hw *usbck_hw, *hw;struct regmap *regmap; -struct clk_hw *hw; -int i;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_xtal" ); -if (i <0 ) -return ; - - slowxtal_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -363,12 +352,13 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , + hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), bypass);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_rm9200_main (regmap,"mainck" ,"main_osc" ,NULL ); + hw =at91_clk_register_rm9200_main (regmap,"mainck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free;
@@ -382,20 +372,17 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,if (IS_ERR (hw)) goto err_free; - parent_names[0 ] ="slow_rc_osc" ; - parent_names[1 ] ="slow_xtal" ; - hw =at91_clk_register_sam9260_slow (regmap,"slck" , - parent_names,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (hw); + parent_data[1 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + hw =at91_clk_register_sam9260_slow (regmap,"slck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; at91sam9260_pmc->chws[PMC_SLOW ] = hw; - slck_name ="slck" ; - }else { - slck_name = slowxtal_name; } - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_MAIN ]),0 , data->plla_layout, data->plla_characteristics);if (IS_ERR (hw))
@@ -403,7 +390,8 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, at91sam9260_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_pll (regmap,"pllbck" ,"mainck" ,1 , + hw =at91_clk_register_pll (regmap,"pllbck" ,NULL , + &AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_MAIN ]),1 , data->pllb_layout, data->pllb_characteristics);if (IS_ERR (hw))
@@ -411,12 +399,12 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, at91sam9260_pmc->chws[PMC_PLLBCK ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="pllack" ; - parent_names[3 ] ="pllbck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_PLLACK ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock);
@@ -424,7 +412,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock,
@@ -434,21 +422,23 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, at91sam9260_pmc->chws[PMC_MCK ] = hw; - hw =at91rm9200_clk_register_usb (regmap,"usbck" ,"pllbck" ,NULL , usb_div); -if (IS_ERR (hw)) + usbck_hw =at91rm9200_clk_register_usb (regmap,"usbck" ,NULL , + &AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_PLLBCK ]), + usb_div); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="pllack" ; - parent_names[3 ] ="pllbck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_PLLBCK ]);for (i =0 ; i < data->num_progck; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,4 , i, +NULL , parent_data,4 , i, &at91rm9200_programmable_layout,NULL );if (IS_ERR (hw))
@@ -457,9 +447,22 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, at91sam9260_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + data->sck[0 ].parent_hw = usbck_hw; + data->sck[1 ].parent_hw = usbck_hw; + data->sck[2 ].parent_hw = at91sam9260_pmc->pchws[0 ]; + data->sck[3 ].parent_hw = at91sam9260_pmc->pchws[1 ]; +if (data->num_sck ==6 ) { + data->sck[4 ].parent_hw = at91sam9260_pmc->pchws[2 ]; + data->sck[5 ].parent_hw = at91sam9260_pmc->pchws[3 ]; + } +if (data->num_sck ==8 ) { + data->sck[6 ].parent_hw = at91sam9260_pmc->chws[PMC_MCK ]; + data->sck[7 ].parent_hw = at91sam9260_pmc->chws[PMC_MCK ]; + }for (i =0 ; i < data->num_sck; i++) { - hw =at91_clk_register_system (regmap, data->sck[i].n, - data->sck[i].p,NULL , + hw =at91_clk_register_system (regmap, data->sck[i].n,NULL , + &AT91_CLK_PD_HW (data->sck[i].parent_hw), data->sck[i].id,0 );if (IS_ERR (hw)) goto err_free;
@@ -470,7 +473,8 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,for (i =0 ; i < data->num_pck; i++) { hw =at91_clk_register_peripheral (regmap, data->pck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (at91sam9260_pmc->chws[PMC_MCK ]), data->pck[i].id);if (IS_ERR (hw)) goto err_free;
Signature · 1 line
2.43.0
PATCH v2 27/32 clk: at91: at91sam9g45: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch AT91SAM9G45 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/at91sam9g45.c | 89 +++++++++++++++++----------------- 1 file changed, 44 insertions(+), 45 deletions(-)
drivers/clk/at91/at91sam9g45.c +44 -45
@@ -37,9 +37,9 @@ static const struct clk_pll_characteristics plla_characteristics = { .out = plla_out, }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } at91sam9g45_systemck[] = {
@@ -47,10 +47,10 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "uhpck", .id = 6 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, }; struct pck {
@@ -92,24 +92,14 @@ static const struct pck at91sam9g45_periphck[] = {static void __init at91sam9g45_pmc_setup (struct device_node *np) { -const char *slck_name, *mainxtal_name; +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +u8 slow_clk_index =0 , main_xtal_index =1 ; +struct clk_parent_data parent_data[5 ];struct pmc_data *at91sam9g45_pmc; -const char *parent_names[6 ]; +struct clk_hw *usbck_hw, *hw;struct regmap *regmap; -struct clk_hw *hw; -int i;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -123,40 +113,43 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , + hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), bypass);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_rm9200_main (regmap,"mainck" ,"main_osc" ,NULL ); + hw =at91_clk_register_rm9200_main (regmap,"mainck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; at91sam9g45_pmc->chws[PMC_MAIN ] = hw; - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_MAIN ]),0 , &at91rm9200_pll_layout, &plla_characteristics);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_plldiv (regmap,"plladivck" ,"pllack" ); + hw =at91_clk_register_plldiv (regmap,"plladivck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; at91sam9g45_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,"mainck" ,NULL ); + hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,NULL , + &AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_MAIN ]));if (IS_ERR (hw)) goto err_free; at91sam9g45_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_UTMI ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock);
@@ -164,7 +157,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock,
@@ -174,24 +167,24 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) at91sam9g45_pmc->chws[PMC_MCK ] = hw; - parent_names[0 ] ="plladivck" ; - parent_names[1 ] ="utmick" ; - hw =at91sam9x5_clk_register_usb (regmap,"usbck" , parent_names,NULL ,2 ); -if (IS_ERR (hw)) + parent_data[0 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_PLLACK ]); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_UTMI ]); + usbck_hw =at91sam9x5_clk_register_usb (regmap,"usbck" ,NULL , parent_data,2 ); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_MCK ]);for (i =0 ; i <2 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,5 , i, +NULL , parent_data,5 , i, &at91sam9g45_programmable_layout,NULL );if (IS_ERR (hw))
@@ -200,9 +193,14 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) at91sam9g45_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + at91sam9g45_systemck[0 ].parent_hw = at91sam9g45_pmc->chws[PMC_MCK ]; + at91sam9g45_systemck[1 ].parent_hw = usbck_hw; + at91sam9g45_systemck[2 ].parent_hw = at91sam9g45_pmc->pchws[0 ]; + at91sam9g45_systemck[3 ].parent_hw = at91sam9g45_pmc->pchws[1 ];for (i =0 ; i <ARRAY_SIZE (at91sam9g45_systemck); i++) { - hw =at91_clk_register_system (regmap, at91sam9g45_systemck[i].n, - at91sam9g45_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, at91sam9g45_systemck[i].n,NULL , + &AT91_CLK_PD_HW (at91sam9g45_systemck[i].parent_hw), at91sam9g45_systemck[i].id, at91sam9g45_systemck[i].flags);if (IS_ERR (hw))
@@ -214,7 +212,8 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)for (i =0 ; i <ARRAY_SIZE (at91sam9g45_periphck); i++) { hw =at91_clk_register_peripheral (regmap, at91sam9g45_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (at91sam9g45_pmc->chws[PMC_MCK ]), at91sam9g45_periphck[i].id);if (IS_ERR (hw)) goto err_free;
Signature · 1 line
2.43.0
PATCH v2 28/32 clk: at91: at91sam9n12: switch to parent_hw and parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch AT91SAM9N12 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/at91sam9n12.c | 106 +++++++++++++++++---------------- 1 file changed, 54 insertions(+), 52 deletions(-)
drivers/clk/at91/at91sam9n12.c +54 -52
@@ -51,9 +51,9 @@ static const struct clk_pll_characteristics pllb_characteristics = { .out = pllb_out, }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;unsigned long flags;u8 id; } at91sam9n12_systemck[] = {
@@ -61,12 +61,12 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "lcdck", .p = "masterck_div", .id = 3 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "lcdck", .id = 3 }, + { .n = "uhpck", .id = 6 }, + { .n = "udpck", .id = 7 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, }; static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
@@ -111,25 +111,15 @@ static const struct pck at91sam9n12_periphck[] = {static void __init at91sam9n12_pmc_setup (struct device_node *np) { +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +struct clk_hw *usbck_hw, *hw, *main_rc_hw, *main_osc_hw; +u8 slow_clk_index =0 , main_xtal_index =1 ;struct clk_range range =CLK_RANGE (0 ,0 ); -const char *slck_name, *mainxtal_name; +struct clk_parent_data parent_data[5 ];struct pmc_data *at91sam9n12_pmc; -const char *parent_names[6 ];struct regmap *regmap; -struct clk_hw *hw; -int i;bool bypass; - - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); +int i; regmap =device_node_to_regmap (np);if (IS_ERR (regmap))
@@ -140,50 +130,53 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)if (!at91sam9n12_pmc)return ; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -50000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +50000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL , - bypass); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass); +if (IS_ERR (main_osc_hw)) goto err_free; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; at91sam9n12_pmc->chws[PMC_MAIN ] = hw; - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_MAIN ]),0 , &at91rm9200_pll_layout, &plla_characteristics);if (IS_ERR (hw)) goto err_free; - hw =at91_clk_register_plldiv (regmap,"plladivck" ,"pllack" ); + hw =at91_clk_register_plldiv (regmap,"plladivck" ,NULL , &AT91_CLK_PD_HW (hw));if (IS_ERR (hw)) goto err_free; at91sam9n12_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_pll (regmap,"pllbck" ,"mainck" ,1 , + hw =at91_clk_register_pll (regmap,"pllbck" ,NULL , + &AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_MAIN ]),1 , &at91rm9200_pll_layout, &pllb_characteristics);if (IS_ERR (hw)) goto err_free; at91sam9n12_pmc->chws[PMC_PLLBCK ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="pllbck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_PLLBCK ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock);
@@ -191,7 +184,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock,
@@ -201,22 +194,23 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) at91sam9n12_pmc->chws[PMC_MCK ] = hw; - hw =at91sam9n12_clk_register_usb (regmap,"usbck" ,"pllbck" ,NULL ); -if (IS_ERR (hw)) + usbck_hw =at91sam9n12_clk_register_usb (regmap,"usbck" ,NULL , + &AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_PLLBCK ])); +if (IS_ERR (usbck_hw)) goto err_free; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plladivck" ; - parent_names[3 ] ="pllbck" ; - parent_names[4 ] ="masterck_div" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_PLLBCK ]); + parent_data[4 ] =AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_MCK ]);for (i =0 ; i <2 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,5 , i, +NULL , parent_data,5 , i, &at91sam9x5_programmable_layout,NULL );if (IS_ERR (hw))
@@ -225,9 +219,16 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) at91sam9n12_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + at91sam9n12_systemck[0 ].parent_hw = at91sam9n12_pmc->chws[PMC_MCK ]; + at91sam9n12_systemck[1 ].parent_hw = at91sam9n12_pmc->chws[PMC_MCK ]; + at91sam9n12_systemck[2 ].parent_hw = usbck_hw; + at91sam9n12_systemck[3 ].parent_hw = usbck_hw; + at91sam9n12_systemck[4 ].parent_hw = at91sam9n12_pmc->pchws[0 ]; + at91sam9n12_systemck[5 ].parent_hw = at91sam9n12_pmc->pchws[1 ];for (i =0 ; i <ARRAY_SIZE (at91sam9n12_systemck); i++) { - hw =at91_clk_register_system (regmap, at91sam9n12_systemck[i].n, - at91sam9n12_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, at91sam9n12_systemck[i].n,NULL , + &AT91_CLK_PD_HW (at91sam9n12_systemck[i].parent_hw), at91sam9n12_systemck[i].id, at91sam9n12_systemck[i].flags);if (IS_ERR (hw))
@@ -240,7 +241,8 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &at91sam9n12_pcr_layout, at91sam9n12_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (at91sam9n12_pmc->chws[PMC_MCK ]), at91sam9n12_periphck[i].id, &range,INT_MIN ,0 );if (IS_ERR (hw))
Signature · 1 line
2.43.0
PATCH v2 29/32 clk: at91: at91sam9rl: switch to clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch AT91SAM9RL clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/at91sam9rl.c | 63 ++++++++++++++++------------------- 1 file changed, 28 insertions(+), 35 deletions(-)
drivers/clk/at91/at91sam9rl.c +28 -35
@@ -28,13 +28,12 @@ static const struct clk_pll_characteristics sam9rl_plla_characteristics = { .out = sam9rl_plla_out, }; -static const struct { +static struct {char *n; -char *p;u8 id; } at91sam9rl_systemck[] = { - { .n ="pck0" , .p ="prog0" , .id =8 }, - { .n ="pck1" , .p ="prog1" , .id =9 }, + { .n ="pck0" , .id =8 }, + { .n ="pck1" , .id =9 }, }; static const struct {
@@ -67,24 +66,14 @@ static const struct {static void __init at91sam9rl_pmc_setup (struct device_node *np) { -const char *slck_name, *mainxtal_name; +const char *slow_clk_name ="slowck" , *main_xtal_name ="main_xtal" ; +u8 slow_clk_index =0 , main_xtal_index =1 ; +struct clk_parent_data parent_data[6 ];struct pmc_data *at91sam9rl_pmc; -const char *parent_names[6 ];struct regmap *regmap;struct clk_hw *hw;int i; - i =of_property_match_string (np,"clock-names" ,"slow_clk" ); -if (i <0 ) -return ; - - slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); - regmap =device_node_to_regmap (np);if (IS_ERR (regmap))return ;
@@ -95,13 +84,15 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)if (!at91sam9rl_pmc)return ; - hw =at91_clk_register_rm9200_main (regmap,"mainck" , mainxtal_name,NULL ); + hw =at91_clk_register_rm9200_main (regmap,"mainck" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index));if (IS_ERR (hw)) goto err_free; at91sam9rl_pmc->chws[PMC_MAIN ] = hw; - hw =at91_clk_register_pll (regmap,"pllack" ,"mainck" ,0 , + hw =at91_clk_register_pll (regmap,"pllack" ,NULL , + &AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_MAIN ]),0 , &at91rm9200_pll_layout, &sam9rl_plla_characteristics);if (IS_ERR (hw))
@@ -109,18 +100,19 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) at91sam9rl_pmc->chws[PMC_PLLACK ] = hw; - hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,"mainck" ,NULL ); + hw =at91_clk_register_utmi (regmap,NULL ,"utmick" ,NULL , + &AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_MAIN ]));if (IS_ERR (hw)) goto err_free; at91sam9rl_pmc->chws[PMC_UTMI ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="pllack" ; - parent_names[3 ] ="utmick" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_UTMI ]); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , +NULL , parent_data, &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock);
@@ -128,7 +120,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) goto err_free; hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , +NULL , &AT91_CLK_PD_HW (hw), &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock,CLK_SET_RATE_GATE ,0 );
@@ -137,18 +129,18 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) at91sam9rl_pmc->chws[PMC_MCK ] = hw; - parent_names[0 ] = slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="pllack" ; - parent_names[3 ] ="utmick" ; - parent_names[4 ] ="masterck_div" ; + parent_data[0 ] =AT91_CLK_PD_NAME (slow_clk_name, slow_clk_index); + parent_data[1 ] =AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_PLLACK ]); + parent_data[3 ] =AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_UTMI ]); + parent_data[4 ] =AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_MCK ]);for (i =0 ; i <2 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,5 , i, +NULL , parent_data,5 , i, &at91rm9200_programmable_layout,NULL );if (IS_ERR (hw))
@@ -158,8 +150,8 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) }for (i =0 ; i <ARRAY_SIZE (at91sam9rl_systemck); i++) { - hw =at91_clk_register_system (regmap, at91sam9rl_systemck[i].n, - at91sam9rl_systemck[i].p,NULL , + hw =at91_clk_register_system (regmap, at91sam9rl_systemck[i].n,NULL , + &AT91_CLK_PD_HW (at91sam9rl_pmc->pchws[0 ]), at91sam9rl_systemck[i].id,0 );if (IS_ERR (hw)) goto err_free;
@@ -170,7 +162,8 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)for (i =0 ; i <ARRAY_SIZE (at91sam9rl_periphck); i++) { hw =at91_clk_register_peripheral (regmap, at91sam9rl_periphck[i].n, -"masterck_div" ,NULL , +NULL , + &AT91_CLK_PD_HW (at91sam9rl_pmc->chws[PMC_MCK ]), at91sam9rl_periphck[i].id);if (IS_ERR (hw)) goto err_free;
Signature · 1 line
2.43.0
PATCH v2 30/32 clk: at91: sam9x75: switch to parent_hw and parent_data
In reply to [email protected]From: Ryan Wanner <[email protected]>
Switch SAM9X75 clocks to use modern parent_hw and parent_data.
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/sam9x7.c | 330 +++++++++++++++++++++----------------- 1 file changed, 186 insertions(+), 144 deletions(-)
drivers/clk/at91/sam9x7.c +186 -144
@@ -33,10 +33,22 @@ enum pll_ids {PLL_ID_UPLL ,PLL_ID_AUDIO ,PLL_ID_LVDS , -PLL_ID_PLLA_DIV2 , PLL_ID_MAX, }; +/* +* PLL component identifier +* @PLL_COMPID_FRAC: Fractional PLL component identifier +* @PLL_COMPID_DIV0: 1st PLL divider component identifier +* @PLL_COMPID_DIV1: 2nd PLL divider component identifier +*/ +enum pll_component_id { +PLL_COMPID_FRAC , +PLL_COMPID_DIV0 , +PLL_COMPID_DIV1 , +PLL_COMPID_MAX , +}; +/** * enum pll_type - PLL type identifiers * @PLL_TYPE_FRAC: fractional PLL identifier
@@ -180,6 +192,18 @@ static const struct clk_pll_layout pll_divio_layout = { .endiv_shift = 30, }; +/* +* SAM9X7 PLL possible parents +* @SAM9X7_PLL_PARENT_MAINCK: MAINCK is PLL a parent +* @SAM9X7_PLL_PARENT_MAIN_XTAL: MAIN XTAL is a PLL parent +* @SAM9X7_PLL_PARENT_FRACCK: Frac PLL is a PLL parent (for PLL dividers) +*/ +enum sam9x7_pll_parent { +SAM9X7_PLL_PARENT_MAINCK , +SAM9X7_PLL_PARENT_MAIN_XTAL , +SAM9X7_PLL_PARENT_FRACCK +}; +/* * PLL clocks description * @n: clock name
@@ -187,22 +211,24 @@ static const struct clk_pll_layout pll_divio_layout = {* @l: clock layout * @t: clock type * @c: pll characteristics +* @hw: pointer to clk_hw * @f: clock flags * @eid: export index in sam9x7->chws[] array */ -static const struct { +static struct {const char *n; -const char *p;const struct clk_pll_layout *l;u8 t;const struct clk_pll_characteristics *c; +struct clk_hw *hw;unsigned long f; +enum sam9x7_pll_parent p;u8 eid; -} sam9x7_plls[][3 ] = { +} sam9x7_plls[][PLL_COMPID_MAX ] = { [PLL_ID_PLLA ] = { - { + [PLL_COMPID_FRAC ] = { .n ="plla_fracck" , - .p ="mainck" , + .p =SAM9X7_PLL_PARENT_MAINCK , .l = &plla_frac_layout, .t =PLL_TYPE_FRAC ,/*
@@ -213,9 +239,9 @@ static const struct { .c = &plla_characteristics, }, - { + [PLL_COMPID_DIV0] = { .n = "plla_divpmcck", - .p = "plla_fracck", + .p = SAM9X7_PLL_PARENT_FRACCK, .l = &pll_divpmc_layout, .t = PLL_TYPE_DIV,/* This feeds CPU. It should not be disabled */
@@ -223,21 +249,35 @@ static const struct { .eid = PMC_PLLACK, .c = &plla_characteristics, }, + + [PLL_COMPID_DIV1] = { + .n = "plla_div2pmcck", + .p = SAM9X7_PLL_PARENT_FRACCK, + .l = &plladiv2_divpmc_layout, +/* +* This may feed critical parts of the system like timers. +* It should not be disabled. +*/ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c = &plladiv2_characteristics, + .eid = PMC_PLLADIV2, + .t = PLL_TYPE_DIV, + }, }, [PLL_ID_UPLL] = { - { + [PLL_COMPID_FRAC] = { .n = "upll_fracck", - .p ="main_osc" , + .p = SAM9X7_PLL_PARENT_MAIN_XTAL, .l = &pll_frac_layout, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, .c = &upll_characteristics, }, - { + [PLL_COMPID_DIV0] = { .n = "upll_divpmcck", - .p ="upll_fracck" , + .p = SAM9X7_PLL_PARENT_FRACCK, .l = &pll_divpmc_layout, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
@@ -248,18 +288,18 @@ static const struct { }, [PLL_ID_AUDIO] = { - { + [PLL_COMPID_FRAC] = { .n = "audiopll_fracck", - .p = "main_osc", + .p = SAM9X7_PLL_PARENT_MAIN_XTAL, .l = &pll_frac_layout, .f = CLK_SET_RATE_GATE, .c = &audiopll_characteristics, .t = PLL_TYPE_FRAC, }, - { + [PLL_COMPID_DIV0] = { .n = "audiopll_divpmcck", - .p = "audiopll_fracck", + .p = SAM9X7_PLL_PARENT_FRACCK, .l = &pll_divpmc_layout, .f =CLK_SET_RATE_GATE |CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT,
@@ -268,9 +308,9 @@ static const struct { .t = PLL_TYPE_DIV, }, - { + [PLL_COMPID_DIV1] = { .n = "audiopll_diviock", - .p = "audiopll_fracck", + .p = SAM9X7_PLL_PARENT_FRACCK, .l = &pll_divio_layout, .f =CLK_SET_RATE_GATE |CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT,
@@ -281,18 +321,18 @@ static const struct { }, [PLL_ID_LVDS] = { - { + [PLL_COMPID_FRAC] = { .n = "lvdspll_fracck", - .p = "main_osc", + .p = SAM9X7_PLL_PARENT_MAIN_XTAL, .l = &pll_frac_layout, .f = CLK_SET_RATE_GATE, .c = &lvdspll_characteristics, .t = PLL_TYPE_FRAC, }, - { + [PLL_COMPID_DIV0] = { .n = "lvdspll_divpmcck", - .p = "lvdspll_fracck", + .p = SAM9X7_PLL_PARENT_FRACCK, .l = &pll_divpmc_layout, .f =CLK_SET_RATE_GATE |CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT,
@@ -301,22 +341,6 @@ static const struct { .t = PLL_TYPE_DIV, }, }, - - [PLL_ID_PLLA_DIV2 ] = { - { - .n ="plla_div2pmcck" , - .p ="plla_fracck" , - .l = &plladiv2_divpmc_layout, -/* -* This may feed critical parts of the system like timers. -* It should not be disabled. -*/ - .f =CLK_IS_CRITICAL |CLK_SET_RATE_GATE , - .c = &plladiv2_characteristics, - .eid =PMC_PLLADIV2 , - .t =PLL_TYPE_DIV , - }, - }, }; static const struct clk_programmable_layout sam9x7_programmable_layout = {
@@ -334,9 +358,9 @@ static const struct clk_pcr_layout sam9x7_pcr_layout = { .pid_mask = GENMASK(6, 0), }; -static const struct { +static struct {char *n; -char *p; +struct clk_hw *parent_hw;u8 id;unsigned long flags; } sam9x7_systemck[] = {
@@ -344,10 +368,10 @@ static const struct {* ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "uhpck", .id = 6 }, + { .n = "pck0", .id = 8 }, + { .n = "pck1", .id = 9 }, };/*
@@ -420,16 +444,21 @@ static const struct {/* * Generic clock description * @n: clock name -* @pp: PLL parents +* @pp: PLL parents (entry formed by PLL components identifiers +* (see enum pll_component_id)) * @pp_mux_table: PLL parents mux table * @r: clock output range * @pp_chg_id: id in parent array of changeable PLL parent * @pp_count: PLL parents count * @id: clock id */ + static const struct { const char *n; - const char *pp[8]; + struct { + int pll_id; + int pll_compid; + } pp[8]; const char pp_mux_table[8]; struct clk_range r; int pp_chg_id;
@@ -439,7 +468,7 @@ static const struct { { .n = "flex0_gclk", .id = 5, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -448,7 +477,7 @@ static const struct { { .n = "flex1_gclk", .id = 6, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -457,7 +486,7 @@ static const struct { { .n = "flex2_gclk", .id = 7, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -466,7 +495,7 @@ static const struct { { .n = "flex3_gclk", .id = 8, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -475,7 +504,7 @@ static const struct { { .n = "flex6_gclk", .id = 9, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -484,7 +513,7 @@ static const struct { { .n = "flex7_gclk", .id = 10, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -493,7 +522,7 @@ static const struct { { .n = "flex8_gclk", .id = 11, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -503,7 +532,7 @@ static const struct { .n = "sdmmc0_gclk", .id = 12, .r = { .max = 105000000 }, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -512,7 +541,7 @@ static const struct { { .n = "flex4_gclk", .id = 13, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -521,7 +550,7 @@ static const struct { { .n = "flex5_gclk", .id = 14, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -530,7 +559,7 @@ static const struct { { .n = "flex9_gclk", .id = 15, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -539,7 +568,7 @@ static const struct { { .n = "flex10_gclk", .id = 16, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -548,7 +577,7 @@ static const struct { { .n = "tcb0_gclk", .id = 17, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -557,7 +586,7 @@ static const struct { { .n = "adc_gclk", .id = 19, - .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 5, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -567,7 +596,7 @@ static const struct { .n = "lcd_gclk", .id = 25, .r = { .max = 75000000 }, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -577,7 +606,7 @@ static const struct { .n = "sdmmc1_gclk", .id = 26, .r = { .max = 105000000 }, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -587,7 +616,7 @@ static const struct { .n = "mcan0_gclk", .id = 29, .r = { .max = 80000000 }, - .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 5, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -597,7 +626,7 @@ static const struct { .n = "mcan1_gclk", .id = 30, .r = { .max = 80000000 }, - .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 5, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -606,7 +635,7 @@ static const struct { { .n = "flex11_gclk", .id = 32, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -615,7 +644,7 @@ static const struct { { .n = "flex12_gclk", .id = 33, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -625,7 +654,7 @@ static const struct { .n = "i2s_gclk", .id = 34, .r = { .max = 100000000 }, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -635,7 +664,7 @@ static const struct { .n = "qspi_gclk", .id = 35, .r = { .max = 200000000 }, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -644,7 +673,7 @@ static const struct { { .n = "pit64b0_gclk", .id = 37, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -654,7 +683,7 @@ static const struct { .n = "classd_gclk", .id = 42, .r = { .max = 100000000 }, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -663,7 +692,7 @@ static const struct { { .n = "tcb1_gclk", .id = 45, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -672,7 +701,7 @@ static const struct { { .n = "dbgu_gclk", .id = 47, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -682,7 +711,7 @@ static const struct { .n = "mipiphy_gclk", .id = 55, .r = { .max = 27000000 }, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -691,7 +720,7 @@ static const struct { { .n = "pit64b1_gclk", .id = 58, - .pp = { "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 8, }, .pp_count = 1, .pp_chg_id = INT_MIN,
@@ -700,7 +729,7 @@ static const struct { { .n = "gmac_gclk", .id = 67, - .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table = { 6, 8, }, .pp_count =2 , .pp_chg_id = INT_MIN,
@@ -709,34 +738,25 @@ static const struct {static void __init sam9x7_pmc_setup (struct device_node *np) { +u8 td_slck_index =0 , md_slck_index =1 , main_xtal_index =2 ; +const char *const main_xtal_name ="main_xtal" ; +const char *const td_slck_name ="td_slck" ; +const char *const md_slck_name ="md_slck" ; +struct clk_hw *hw, *main_rc_hw, *main_osc_hw; +struct clk_parent_data parent_data[9 ];struct clk_range range =CLK_RANGE (0 ,0 ); -const char *td_slck_name, *md_slck_name, *mainxtal_name;struct pmc_data *sam9x7_pmc; -const char *parent_names[9 ];void **clk_mux_buffer =NULL ;int clk_mux_buffer_size =0 ; -struct clk_hw *main_osc_hw; +struct clk *main_xtal;struct regmap *regmap; -struct clk_hw *hw; +struct clk_hw *usbck_hw;int i, j; - i =of_property_match_string (np,"clock-names" ,"td_slck" ); -if (i <0 ) + main_xtal =of_clk_get (np, main_xtal_index); +if (IS_ERR (main_xtal))return ; - td_slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"md_slck" ); -if (i <0 ) -return ; - - md_slck_name =of_clk_get_parent_name (np, i); - - i =of_property_match_string (np,"clock-names" ,"main_xtal" ); -if (i <0 ) -return ; - mainxtal_name =of_clk_get_parent_name (np, i); - regmap =device_node_to_regmap (np);if (IS_ERR (regmap))return ;
@@ -754,46 +774,55 @@ static void __init sam9x7_pmc_setup(struct device_node *np)if (!clk_mux_buffer) goto err_free; - hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , -50000000 ); -if (IS_ERR (hw)) + main_rc_hw =at91_clk_register_main_rc_osc (regmap,"main_rc_osc" ,12000000 , +50000000 ); +if (IS_ERR (main_rc_hw)) goto err_free; - hw =at91_clk_register_main_osc (regmap,"main_osc" , mainxtal_name,NULL ,0 ); -if (IS_ERR (hw)) + main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index),0 ); +if (IS_ERR (main_osc_hw)) goto err_free; - main_osc_hw = hw; - parent_names[0 ] ="main_rc_osc" ; - parent_names[1 ] ="main_osc" ; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" , parent_names,NULL ,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free; sam9x7_pmc->chws[PMC_MAIN ] = hw;for (i =0 ; i <PLL_ID_MAX ; i++) { -for (j =0 ; j <3 ; j++) { -struct clk_hw *parent_hw; +for (j =0 ; j <PLL_COMPID_MAX ; j++) { +unsigned long parent_rate =0 ;if (!sam9x7_plls[i][j].n)continue ;switch (sam9x7_plls[i][j].t) {case PLL_TYPE_FRAC : -if (!strcmp (sam9x7_plls[i][j].p,"mainck" )) - parent_hw = sam9x7_pmc->chws[PMC_MAIN ]; -else if (!strcmp (sam9x7_plls[i][j].p,"main_osc" )) - parent_hw = main_osc_hw; -else - parent_hw =__clk_get_hw (of_clk_get_by_name - (np, sam9x7_plls[i][j].p)); - +switch (sam9x7_plls[i][j].p) { +case SAM9X7_PLL_PARENT_MAINCK : + parent_data[0 ] =AT91_CLK_PD_NAME ("mainck" ,-1 ); + parent_rate =clk_hw_get_rate (sam9x7_pmc->chws[PMC_MAIN ]); +break ; +case SAM9X7_PLL_PARENT_MAIN_XTAL : + parent_data[0 ] =AT91_CLK_PD_NAME (main_xtal_name, + main_xtal_index); + parent_rate =clk_get_rate (main_xtal); +break ; +default : +/* Should not happen. */ +break ; + } + +if (!parent_rate) +return ; hw =sam9x60_clk_register_frac_pll (regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p, - parent_hw, i, + parent_data, + parent_rate, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f);
@@ -803,7 +832,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) hw =sam9x60_clk_register_div_pll (regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p,NULL , i, +NULL , sam9x7_plls[i][0 ].hw, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f,0 );
@@ -816,23 +845,24 @@ static void __init sam9x7_pmc_setup(struct device_node *np)if (IS_ERR (hw)) goto err_free; + sam9x7_plls[i][j].hw = hw;if (sam9x7_plls[i][j].eid) sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw; } } - parent_names[0 ] = md_slck_name; - parent_names[1 ] ="mainck" ; - parent_names[2 ] ="plla_divpmcck" ; - parent_names[3 ] ="upll_divpmcck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_HW (sam9x7_pmc->chws[PMC_MAIN ]); + parent_data[2 ] =AT91_CLK_PD_HW (sam9x7_plls[PLL_ID_PLLA ][PLL_COMPID_DIV0 ].hw); + parent_data[3 ] =AT91_CLK_PD_HW (sam9x7_plls[PLL_ID_UPLL ][PLL_COMPID_DIV0 ].hw); hw =at91_clk_register_master_pres (regmap,"masterck_pres" ,4 , - parent_names,NULL , &sam9x7_master_layout, +NULL , parent_data, &sam9x7_master_layout, &mck_characteristics, &mck_lock);if (IS_ERR (hw)) goto err_free; hw =at91_clk_register_master_div (regmap,"masterck_div" , -"masterck_pres" ,NULL , &sam9x7_master_layout, +NULL , &AT91_CLK_PD_HW (hw), &sam9x7_master_layout, &mck_characteristics, &mck_lock,CLK_SET_RATE_GATE ,0 );if (IS_ERR (hw))
@@ -840,27 +870,27 @@ static void __init sam9x7_pmc_setup(struct device_node *np) sam9x7_pmc->chws[PMC_MCK ] = hw; - parent_names[0 ] ="plla_divpmcck" ; - parent_names[1 ] ="upll_divpmcck" ; - parent_names[2 ] ="main_osc" ; - hw =sam9x60_clk_register_usb (regmap,"usbck" , parent_names,3 ); + parent_data[0 ] =AT91_CLK_PD_HW (sam9x7_plls[PLL_ID_PLLA ][PLL_COMPID_DIV0 ].hw); + parent_data[1 ] =AT91_CLK_PD_HW (sam9x7_plls[PLL_ID_UPLL ][PLL_COMPID_DIV0 ].hw); + parent_data[2 ] =AT91_CLK_PD_HW (main_osc_hw); + usbck_hw =sam9x60_clk_register_usb (regmap,"usbck" ,NULL , parent_data,3 );if (IS_ERR (hw)) goto err_free; - parent_names[0 ] = md_slck_name; - parent_names[1 ] = td_slck_name; - parent_names[2 ] ="mainck" ; - parent_names[3 ] ="masterck_div" ; - parent_names[4 ] ="plla_divpmcck" ; - parent_names[5 ] ="upll_divpmcck" ; - parent_names[6 ] ="audiopll_divpmcck" ; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sam9x7_pmc->chws[PMC_MAIN ]); + parent_data[3 ] =AT91_CLK_PD_HW (sam9x7_pmc->chws[PMC_MCK ]); + parent_data[4 ] =AT91_CLK_PD_HW (sam9x7_plls[PLL_ID_PLLA ][PLL_COMPID_DIV0 ].hw); + parent_data[5 ] =AT91_CLK_PD_HW (sam9x7_plls[PLL_ID_UPLL ][PLL_COMPID_DIV0 ].hw); + parent_data[6 ] =AT91_CLK_PD_HW (sam9x7_plls[PLL_ID_AUDIO ][PLL_COMPID_DIV0 ].hw);for (i =0 ; i <2 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); hw =at91_clk_register_programmable (regmap, name, - parent_names,NULL ,7 , i, +NULL , parent_data,7 , i, &sam9x7_programmable_layout,NULL );if (IS_ERR (hw))
@@ -869,9 +899,14 @@ static void __init sam9x7_pmc_setup(struct device_node *np) sam9x7_pmc->pchws[i] = hw; } +/* Set systemck parent hws. */ + sam9x7_systemck[0 ].parent_hw = sam9x7_pmc->chws[PMC_MCK ]; + sam9x7_systemck[1 ].parent_hw = usbck_hw; + sam9x7_systemck[2 ].parent_hw = sam9x7_pmc->pchws[0 ]; + sam9x7_systemck[3 ].parent_hw = sam9x7_pmc->pchws[1 ];for (i =0 ; i <ARRAY_SIZE (sam9x7_systemck); i++) { hw =at91_clk_register_system (regmap, sam9x7_systemck[i].n, - sam9x7_systemck[i].p,NULL , +NULL , &AT91_CLK_PD_HW (sam9x7_systemck[i].parent_hw), sam9x7_systemck[i].id, sam9x7_systemck[i].flags);if (IS_ERR (hw))
@@ -884,7 +919,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np) hw =at91_clk_register_sam9x5_peripheral (regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_periphck[i].n, -"masterck_div" ,NULL , +NULL , &AT91_CLK_PD_HW (sam9x7_pmc->chws[PMC_MCK ]), sam9x7_periphck[i].id, &range,INT_MIN , sam9x7_periphck[i].f);
@@ -894,10 +929,10 @@ static void __init sam9x7_pmc_setup(struct device_node *np) sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw; } - parent_names[0 ] = md_slck_name; - parent_names[1 ] = td_slck_name; - parent_names[2 ] ="mainck" ; - parent_names[3 ] ="masterck_div" ; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sam9x7_pmc->chws[PMC_MAIN ]); + parent_data[3 ] =AT91_CLK_PD_HW (sam9x7_pmc->chws[PMC_MCK ]);for (i =0 ; i <ARRAY_SIZE (sam9x7_gck); i++) {u8 num_parents =4 + sam9x7_gck[i].pp_count;u32 *mux_table;
@@ -910,13 +945,18 @@ static void __init sam9x7_pmc_setup(struct device_node *np)PMC_INIT_TABLE (mux_table,4 );PMC_FILL_TABLE (&mux_table[4 ], sam9x7_gck[i].pp_mux_table, sam9x7_gck[i].pp_count); -PMC_FILL_TABLE (&parent_names[4 ], sam9x7_gck[i].pp, - sam9x7_gck[i].pp_count); + +for (j =0 ; j < sam9x7_gck[i].pp_count; j++) { +u8 pll_id = sam9x7_gck[i].pp[j].pll_id; +u8 pll_compid = sam9x7_gck[i].pp[j].pll_compid; + + parent_data[4 + j] =AT91_CLK_PD_HW (sam9x7_plls[pll_id][pll_compid].hw); + } hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_gck[i].n, - parent_names, NULL, mux_table, + NULL, parent_data, mux_table, num_parents, sam9x7_gck[i].id, &sam9x7_gck[i].r,
@@ -931,7 +971,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)of_clk_add_hw_provider (np, of_clk_hw_pmc_get, sam9x7_pmc);kfree (clk_mux_buffer); -return ; + goto put_main_xtal; err_free:if (clk_mux_buffer) {
@@ -940,6 +980,8 @@ static void __init sam9x7_pmc_setup(struct device_node *np)kfree (clk_mux_buffer); }kfree (sam9x7_pmc); +put_main_xtal: +clk_put (main_xtal); }/* Some clks are used for a clocksource */
Signature · 1 line
2.43.0
PATCH v2 31/32 clk: at91: sama7g5: switch to clk_parent_data
In reply to [email protected]From: Claudiu Beznea <[email protected]>
Switch SAMA7G5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Claudiu Beznea <[email protected]>
[[email protected]: Took all the small changes for this SoC from the clock core commits and put them into this patch as one full commit.]
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/sama7g5.c | 108 ++++++++++++++++++------------------- 1 file changed, 54 insertions(+), 54 deletions(-)
drivers/clk/at91/sama7g5.c +54 -54
@@ -969,35 +969,34 @@ static const struct clk_pcr_layout sama7g5_pcr_layout = {static void __init sama7g5_pmc_setup (struct device_node *np) { -const char *main_xtal_name ="main_xtal" ; +u8 td_slck_index =0 , md_slck_index =1 , main_xtal_index =2 ; +const char *const main_xtal_name ="main_xtal" ; +const char *const td_slck_name ="td_slck" ; +const char *const md_slck_name ="md_slck" ; +struct clk_hw *hw, *main_rc_hw, *main_osc_hw; +struct clk_parent_data parent_data[10 ];struct pmc_data *sama7g5_pmc;void **alloc_mem =NULL ;int alloc_mem_size =0 ; +struct clk *main_xtal;struct regmap *regmap; -struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; -struct clk_hw *td_slck_hw, *md_slck_hw; -static struct clk_parent_data parent_data; -struct clk_hw *parent_hws[10 ];bool bypass;int i, j; - td_slck_hw =__clk_get_hw (of_clk_get_by_name (np,"td_slck" )); - md_slck_hw =__clk_get_hw (of_clk_get_by_name (np,"md_slck" )); - main_xtal_hw =__clk_get_hw (of_clk_get_by_name (np, main_xtal_name)); - -if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) + main_xtal =of_clk_get (np, main_xtal_index); +if (IS_ERR (main_xtal))return ; regmap =device_node_to_regmap (np);if (IS_ERR (regmap)) -return ; + goto put_main_xtal; sama7g5_pmc =pmc_data_allocate (PMC_MCK1 +1 ,nck (sama7g5_systemck),nck (sama7g5_periphck),nck (sama7g5_gck),8 );if (!sama7g5_pmc) -return ; + goto put_main_xtal; alloc_mem = kmalloc(sizeof(void *) * (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)),
@@ -1012,16 +1011,15 @@ static void __init sama7g5_pmc_setup(struct device_node *np) bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - parent_data.name = main_xtal_name; - parent_data.fw_name = main_xtal_name; main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , - &parent_data, bypass); + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass);if (IS_ERR (main_osc_hw)) goto err_free; - parent_hws[0 ] = main_rc_hw; - parent_hws[1 ] = main_osc_hw; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_hws,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free;
@@ -1029,7 +1027,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)for (i =0 ; i <PLL_ID_MAX ; i++) {for (j =0 ; j <PLL_COMPID_MAX ; j++) { -struct clk_hw *parent_hw; +unsigned long parent_rate =0 ;if (!sama7g5_plls[i][j].n)continue ;
@@ -1038,20 +1036,25 @@ static void __init sama7g5_pmc_setup(struct device_node *np)case PLL_TYPE_FRAC :switch (sama7g5_plls[i][j].p) {case SAMA7G5_PLL_PARENT_MAINCK : - parent_hw = sama7g5_pmc->chws[PMC_MAIN ]; + parent_data[0 ] =AT91_CLK_PD_NAME ("mainck" ,-1 ); + parent_rate =clk_hw_get_rate (sama7g5_pmc->chws[PMC_MAIN ]);break ;case SAMA7G5_PLL_PARENT_MAIN_XTAL : - parent_hw = main_xtal_hw; + parent_data[0 ] =AT91_CLK_PD_NAME (main_xtal_name, + main_xtal_index); + parent_rate =clk_get_rate (main_xtal);break ;default :/* Should not happen. */ - parent_hw =NULL ;break ; } +if (!parent_rate) +return ; + hw =sam9x60_clk_register_frac_pll (regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, -NULL , parent_hw, i, + parent_data, parent_rate, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f);
@@ -1081,7 +1084,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) } hw =at91_clk_register_master_div (regmap,"mck0" ,NULL , - sama7g5_plls[PLL_ID_CPU ][1 ].hw, + &AT91_CLK_PD_HW (sama7g5_plls[PLL_ID_CPU ][1 ].hw), &mck0_layout, &mck0_characteristics, &pmc_mck0_lock,CLK_GET_RATE_NOCACHE ,5 );if (IS_ERR (hw))
@@ -1089,12 +1092,11 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_mckx[PCK_PARENT_HW_MCK0 ].hw = sama7g5_pmc->chws[PMC_MCK ] = hw; - parent_hws[0 ] = md_slck_hw; - parent_hws[1 ] = td_slck_hw; - parent_hws[2 ] = sama7g5_pmc->chws[PMC_MAIN ]; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sama7g5_pmc->chws[PMC_MAIN ]);for (i =PCK_PARENT_HW_MCK1 ; i <ARRAY_SIZE (sama7g5_mckx); i++) {u8 num_parents =3 + sama7g5_mckx[i].ep_count; -struct clk_hw *tmp_parent_hws[8 ];u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
@@ -1109,13 +1111,11 @@ static void __init sama7g5_pmc_setup(struct device_node *np)u8 pll_id = sama7g5_mckx[i].ep[j].pll_id;u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid; - tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =AT91_CLK_PD_HW (sama7g5_plls[pll_id][pll_compid].hw); } -PMC_FILL_TABLE (&parent_hws[3 ], tmp_parent_hws, - sama7g5_mckx[i].ep_count); hw =at91_clk_sama7g5_register_master (regmap, sama7g5_mckx[i].n, - num_parents,NULL , parent_hws, mux_table, + num_parents,NULL , parent_data, mux_table, &pmc_mckX_lock, sama7g5_mckx[i].id, sama7g5_mckx[i].c, sama7g5_mckx[i].ep_chg_id);
@@ -1129,27 +1129,28 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_pmc->chws[sama7g5_mckx[i].eid] = hw; } - hw =at91_clk_sama7g5_register_utmi (regmap,"utmick" ,NULL , main_xtal_hw); + hw =at91_clk_sama7g5_register_utmi (regmap,"utmick" ,NULL , + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index));if (IS_ERR (hw)) goto err_free; sama7g5_pmc->chws[PMC_UTMI ] = hw; - parent_hws[0 ] = md_slck_hw; - parent_hws[1 ] = td_slck_hw; - parent_hws[2 ] = sama7g5_pmc->chws[PMC_MAIN ]; - parent_hws[3 ] = sama7g5_plls[PLL_ID_SYS ][PLL_COMPID_DIV0 ].hw; - parent_hws[4 ] = sama7g5_plls[PLL_ID_DDR ][PLL_COMPID_DIV0 ].hw; - parent_hws[5 ] = sama7g5_plls[PLL_ID_IMG ][PLL_COMPID_DIV0 ].hw; - parent_hws[6 ] = sama7g5_plls[PLL_ID_BAUD ][PLL_COMPID_DIV0 ].hw; - parent_hws[7 ] = sama7g5_plls[PLL_ID_AUDIO ][PLL_COMPID_DIV0 ].hw; - parent_hws[8 ] = sama7g5_plls[PLL_ID_ETH ][PLL_COMPID_DIV0 ].hw; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sama7g5_pmc->chws[PMC_MAIN ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama7g5_plls[PLL_ID_SYS ][PLL_COMPID_DIV0 ].hw); + parent_data[4 ] =AT91_CLK_PD_HW (sama7g5_plls[PLL_ID_DDR ][PLL_COMPID_DIV0 ].hw); + parent_data[5 ] =AT91_CLK_PD_HW (sama7g5_plls[PLL_ID_IMG ][PLL_COMPID_DIV0 ].hw); + parent_data[6 ] =AT91_CLK_PD_HW (sama7g5_plls[PLL_ID_BAUD ][PLL_COMPID_DIV0 ].hw); + parent_data[7 ] =AT91_CLK_PD_HW (sama7g5_plls[PLL_ID_AUDIO ][PLL_COMPID_DIV0 ].hw); + parent_data[8 ] =AT91_CLK_PD_HW (sama7g5_plls[PLL_ID_ETH ][PLL_COMPID_DIV0 ].hw);for (i =0 ; i <8 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); - hw =at91_clk_register_programmable (regmap, name,NULL , parent_hws, + hw =at91_clk_register_programmable (regmap, name,NULL , parent_data,9 , i, &programmable_layout, sama7g5_prog_mux_table);
@@ -1161,7 +1162,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)for (i =0 ; i <ARRAY_SIZE (sama7g5_systemck); i++) { hw =at91_clk_register_system (regmap, sama7g5_systemck[i].n, -NULL , sama7g5_pmc->pchws[i], +NULL , &AT91_CLK_PD_HW (sama7g5_pmc->pchws[i]), sama7g5_systemck[i].id,0 );if (IS_ERR (hw)) goto err_free;
@@ -1174,7 +1175,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) &sama7g5_pcr_layout, sama7g5_periphck[i].n,NULL , - sama7g5_mckx[sama7g5_periphck[i].p].hw, + &AT91_CLK_PD_HW (sama7g5_mckx[sama7g5_periphck[i].p].hw), sama7g5_periphck[i].id, &sama7g5_periphck[i].r, sama7g5_periphck[i].chgp ? 0 :
@@ -1185,12 +1186,11 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw; } - parent_hws[0 ] = md_slck_hw; - parent_hws[1 ] = td_slck_hw; - parent_hws[2 ] = sama7g5_pmc->chws[PMC_MAIN ]; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sama7g5_pmc->chws[PMC_MAIN ]);for (i =0 ; i <ARRAY_SIZE (sama7g5_gck); i++) {u8 num_parents =3 + sama7g5_gck[i].pp_count; -struct clk_hw *tmp_parent_hws[8 ];u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
@@ -1205,15 +1205,13 @@ static void __init sama7g5_pmc_setup(struct device_node *np)u8 pll_id = sama7g5_gck[i].pp[j].pll_id;u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid; - tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =AT91_CLK_PD_HW (sama7g5_plls[pll_id][pll_compid].hw); } -PMC_FILL_TABLE (&parent_hws[3 ], tmp_parent_hws, - sama7g5_gck[i].pp_count); hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, sama7g5_gck[i].n, NULL, - parent_hws, mux_table, + parent_data, mux_table, num_parents, sama7g5_gck[i].id, &sama7g5_gck[i].r,
@@ -1227,7 +1225,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)of_clk_add_hw_provider (np, of_clk_hw_pmc_get, sama7g5_pmc); -return ; + goto put_main_xtal; err_free:if (alloc_mem) {
@@ -1237,6 +1235,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np) }kfree (sama7g5_pmc); +put_main_xtal: +clk_put (main_xtal); }/* Some clks are used for a clocksource */
Signature · 1 line
2.43.0
PATCH v2 32/32 clk: at91: sama7d65: switch to clk_parent_data
In reply to [email protected]From: Ryan Wanner <[email protected]>
Switch SAMA7D65 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting.
Signed-off-by Ryan Wanner <[email protected]>
--- drivers/clk/at91/sama7d65.c | 113 +++++++++++++++++------------------- 1 file changed, 54 insertions(+), 59 deletions(-)
drivers/clk/at91/sama7d65.c +54 -59
@@ -1089,36 +1089,34 @@ static const struct clk_pcr_layout sama7d65_pcr_layout = {static void __init sama7d65_pmc_setup (struct device_node *np) { -const char *main_xtal_name ="main_xtal" ; +u8 td_slck_index =0 , md_slck_index =1 , main_xtal_index =2 ; +const char *const main_xtal_name ="main_xtal" ; +const char *const td_slck_name ="td_slck" ; +const char *const md_slck_name ="md_slck" ; +struct clk_hw *hw, *main_rc_hw, *main_osc_hw; +struct clk_parent_data parent_data[10 ];struct pmc_data *sama7d65_pmc; -const char *parent_names[11 ];void **alloc_mem =NULL ;int alloc_mem_size =0 ; +struct clk *main_xtal;struct regmap *regmap; -struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; -struct clk_hw *td_slck_hw, *md_slck_hw; -static struct clk_parent_data parent_data; -struct clk_hw *parent_hws[10 ];bool bypass;int i, j; - td_slck_hw =__clk_get_hw (of_clk_get_by_name (np,"td_slck" )); - md_slck_hw =__clk_get_hw (of_clk_get_by_name (np,"md_slck" )); - main_xtal_hw =__clk_get_hw (of_clk_get_by_name (np, main_xtal_name)); - -if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) + main_xtal =of_clk_get (np, main_xtal_index); +if (IS_ERR (main_xtal))return ; regmap =device_node_to_regmap (np);if (IS_ERR (regmap)) -return ; + goto put_main_xtal; sama7d65_pmc =pmc_data_allocate (PMC_INDEX_MAX ,nck (sama7d65_systemck),nck (sama7d65_periphck),nck (sama7d65_gck),8 );if (!sama7d65_pmc) -return ; + goto put_main_xtal; alloc_mem = kmalloc(sizeof(void *) * (ARRAY_SIZE(sama7d65_mckx) + ARRAY_SIZE(sama7d65_gck)),
@@ -1133,16 +1131,15 @@ static void __init sama7d65_pmc_setup(struct device_node *np) bypass =of_property_read_bool (np,"atmel,osc-bypass" ); - parent_data.name = main_xtal_name; - parent_data.fw_name = main_xtal_name; main_osc_hw =at91_clk_register_main_osc (regmap,"main_osc" ,NULL , - &parent_data, bypass); + &AT91_CLK_PD_NAME (main_xtal_name, main_xtal_index), + bypass);if (IS_ERR (main_osc_hw)) goto err_free; - parent_hws[0 ] = main_rc_hw; - parent_hws[1 ] = main_osc_hw; - hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_hws,2 ); + parent_data[0 ] =AT91_CLK_PD_HW (main_rc_hw); + parent_data[1 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =at91_clk_register_sam9x5_main (regmap,"mainck" ,NULL , parent_data,2 );if (IS_ERR (hw)) goto err_free;
@@ -1150,7 +1147,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)for (i =0 ; i <PLL_ID_MAX ; i++) {for (j =0 ; j <PLL_COMPID_MAX ; j++) { -struct clk_hw *parent_hw; +unsigned long parent_rate =0 ;if (!sama7d65_plls[i][j].n)continue ;
@@ -1159,20 +1156,22 @@ static void __init sama7d65_pmc_setup(struct device_node *np)case PLL_TYPE_FRAC :switch (sama7d65_plls[i][j].p) {case SAMA7D65_PLL_PARENT_MAINCK : - parent_hw = sama7d65_pmc->chws[PMC_MAIN ]; + parent_data[0 ] =AT91_CLK_PD_NAME ("mainck" ,-1 ); + parent_rate =clk_hw_get_rate (sama7d65_pmc->chws[PMC_MAIN ]);break ;case SAMA7D65_PLL_PARENT_MAIN_XTAL : - parent_hw = main_xtal_hw; + parent_data[0 ] =AT91_CLK_PD_NAME (main_xtal_name, + main_xtal_index); + parent_rate =clk_get_rate (main_xtal);break ;default :/* Should not happen. */ - parent_hw =NULL ;break ; } hw =sam9x60_clk_register_frac_pll (regmap, &pmc_pll_lock, sama7d65_plls[i][j].n, -NULL , parent_hw, i, + parent_data, parent_rate, i, sama7d65_plls[i][j].c, sama7d65_plls[i][j].l, sama7d65_plls[i][j].f);
@@ -1202,7 +1201,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) } hw =at91_clk_register_master_div (regmap,"mck0" ,NULL , - sama7d65_plls[PLL_ID_CPU ][1 ].hw, + &AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_CPU ][1 ].hw), &mck0_layout, &mck0_characteristics, &pmc_mck0_lock,CLK_GET_RATE_NOCACHE ,5 );if (IS_ERR (hw))
@@ -1211,12 +1210,11 @@ static void __init sama7d65_pmc_setup(struct device_node *np) sama7d65_pmc->chws[PMC_MCK ] = hw; sama7d65_mckx[PCK_PARENT_HW_MCK0 ].hw = hw; - parent_hws[0 ] = md_slck_hw; - parent_hws[1 ] = td_slck_hw; - parent_hws[2 ] = sama7d65_pmc->chws[PMC_MAIN ]; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sama7d65_pmc->chws[PMC_MAIN ]);for (i =PCK_PARENT_HW_MCK1 ; i <ARRAY_SIZE (sama7d65_mckx); i++) {u8 num_parents =3 + sama7d65_mckx[i].ep_count; -struct clk_hw *tmp_parent_hws[8 ];u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
@@ -1233,13 +1231,11 @@ static void __init sama7d65_pmc_setup(struct device_node *np)u8 pll_id = sama7d65_mckx[i].ep[j].pll_id;u8 pll_compid = sama7d65_mckx[i].ep[j].pll_compid; - tmp_parent_hws[j] = sama7d65_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =AT91_CLK_PD_HW (sama7d65_plls[pll_id][pll_compid].hw); } -PMC_FILL_TABLE (&parent_hws[3 ], tmp_parent_hws, - sama7d65_mckx[i].ep_count); hw = at91_clk_sama7g5_register_master(regmap, sama7d65_mckx[i].n, - num_parents, NULL, parent_hws, + num_parents, NULL, parent_data, mux_table, &pmc_mckX_lock, sama7d65_mckx[i].id, sama7d65_mckx[i].c,
@@ -1253,29 +1249,29 @@ static void __init sama7d65_pmc_setup(struct device_node *np) sama7d65_pmc->chws[sama7d65_mckx[i].eid] = hw; } - parent_names[0 ] ="syspll_divpmcck" ; - parent_names[1 ] ="usbpll_divpmcck" ; - parent_names[2 ] ="main_osc" ; - hw =sam9x60_clk_register_usb (regmap,"usbck" , parent_names,3 ); + parent_data[0 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_SYS ][PLL_COMPID_DIV0 ].hw); + parent_data[1 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_USB ][PLL_COMPID_DIV0 ].hw); + parent_data[2 ] =AT91_CLK_PD_HW (main_osc_hw); + hw =sam9x60_clk_register_usb (regmap,"usbck" ,NULL , parent_data,3 );if (IS_ERR (hw)) goto err_free; - parent_hws[0 ] = md_slck_hw; - parent_hws[1 ] = td_slck_hw; - parent_hws[2 ] = sama7d65_pmc->chws[PMC_MAIN ]; - parent_hws[3 ] = sama7d65_plls[PLL_ID_SYS ][PLL_COMPID_DIV0 ].hw; - parent_hws[4 ] = sama7d65_plls[PLL_ID_DDR ][PLL_COMPID_DIV0 ].hw; - parent_hws[5 ] = sama7d65_plls[PLL_ID_GPU ][PLL_COMPID_DIV0 ].hw; - parent_hws[6 ] = sama7d65_plls[PLL_ID_BAUD ][PLL_COMPID_DIV0 ].hw; - parent_hws[7 ] = sama7d65_plls[PLL_ID_AUDIO ][PLL_COMPID_DIV0 ].hw; - parent_hws[8 ] = sama7d65_plls[PLL_ID_ETH ][PLL_COMPID_DIV0 ].hw; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sama7d65_pmc->chws[PMC_MAIN ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_SYS ][PLL_COMPID_DIV0 ].hw); + parent_data[4 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_DDR ][PLL_COMPID_DIV0 ].hw); + parent_data[5 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_GPU ][PLL_COMPID_DIV0 ].hw); + parent_data[6 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_BAUD ][PLL_COMPID_DIV0 ].hw); + parent_data[7 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_AUDIO ][PLL_COMPID_DIV0 ].hw); + parent_data[8 ] =AT91_CLK_PD_HW (sama7d65_plls[PLL_ID_ETH ][PLL_COMPID_DIV0 ].hw);for (i =0 ; i <8 ; i++) {char name[6 ];snprintf (name,sizeof (name),"prog%d" , i); - hw =at91_clk_register_programmable (regmap, name,NULL , parent_hws, + hw =at91_clk_register_programmable (regmap, name,NULL , parent_data,9 , i, &programmable_layout, sama7d65_prog_mux_table);
@@ -1287,7 +1283,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)for (i =0 ; i <ARRAY_SIZE (sama7d65_systemck); i++) { hw =at91_clk_register_system (regmap, sama7d65_systemck[i].n, - sama7d65_systemck[i].p,NULL , +NULL , &AT91_CLK_PD_HW (sama7d65_pmc->pchws[i]), sama7d65_systemck[i].id,0 );if (IS_ERR (hw)) goto err_free;
@@ -1300,7 +1296,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) &sama7d65_pcr_layout, sama7d65_periphck[i].n,NULL , - sama7d65_mckx[sama7d65_periphck[i].p].hw, + &AT91_CLK_PD_HW (sama7d65_mckx[sama7d65_periphck[i].p].hw), sama7d65_periphck[i].id, &sama7d65_periphck[i].r, sama7d65_periphck[i].chgp ? 0 :
@@ -1311,13 +1307,12 @@ static void __init sama7d65_pmc_setup(struct device_node *np) sama7d65_pmc->phws[sama7d65_periphck[i].id] = hw; } - parent_hws[0 ] = md_slck_hw; - parent_hws[1 ] = td_slck_hw; - parent_hws[2 ] = sama7d65_pmc->chws[PMC_MAIN ]; - parent_hws[3 ] = sama7d65_pmc->chws[PMC_MCK1 ]; + parent_data[0 ] =AT91_CLK_PD_NAME (md_slck_name, md_slck_index); + parent_data[1 ] =AT91_CLK_PD_NAME (td_slck_name, td_slck_index); + parent_data[2 ] =AT91_CLK_PD_HW (sama7d65_pmc->chws[PMC_MAIN ]); + parent_data[3 ] =AT91_CLK_PD_HW (sama7d65_pmc->chws[PMC_MCK1 ]);for (i =0 ; i <ARRAY_SIZE (sama7d65_gck); i++) {u8 num_parents =4 + sama7d65_gck[i].pp_count; -struct clk_hw *tmp_parent_hws[8 ];u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
@@ -1334,15 +1329,13 @@ static void __init sama7d65_pmc_setup(struct device_node *np)u8 pll_id = sama7d65_gck[i].pp[j].pll_id;u8 pll_compid = sama7d65_gck[i].pp[j].pll_compid; - tmp_parent_hws[j] = sama7d65_plls[pll_id][pll_compid].hw; + parent_data[4 + j] =AT91_CLK_PD_HW (sama7d65_plls[pll_id][pll_compid].hw); } -PMC_FILL_TABLE (&parent_hws[4 ], tmp_parent_hws, - sama7d65_gck[i].pp_count); hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7d65_pcr_layout, sama7d65_gck[i].n, NULL, - parent_hws, mux_table, + parent_data, mux_table, num_parents, sama7d65_gck[i].id, &sama7d65_gck[i].r,
@@ -1356,7 +1349,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)of_clk_add_hw_provider (np, of_clk_hw_pmc_get, sama7d65_pmc);kfree (alloc_mem); -return ; + goto put_main_xtal; err_free:if (alloc_mem) {
@@ -1366,6 +1359,8 @@ static void __init sama7d65_pmc_setup(struct device_node *np) }kfree (sama7d65_pmc); +put_main_xtal: +clk_put (main_xtal); }/* Some clks are used for a clocksource */
Signature · 1 line
2.43.0