nvmem: s32g-ocotp: Add driver for S32G OCOTP
Subsystems (4)
v2 cover nvmem: s32g-ocotp: Add driver for S32G OCOTP
This driver provides a way to access the On Chip One-Time Programmable Controller (OCOTP) on the s32g chipset. There are three versions of this chip but they're compatible.
v2:
I have fixed everything that people pointed out about version 1.
Sorry, Rob and Krzysztof, for the problems with the device tree YAML file. I had an issue with my dtschema installation and it's fixed now.
I also screwed up the From headers in v1. I called git format-patch without passing the --from argument. I've fixed my scripts so that won't happen again. I also messed up the Signed-off by lines in patch 1 and 2. Sorry!
My other mistakes were from not being a familiar enough with the subsystem and those are addressed as well. Especially re-writing the driver using keepouts cut down a lot of lines of code. I've tested it and the results are the same before and after.
Ciprian Costea (2):
dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
nvmem: s32g-ocotp: Add driver for S32G OCOTP
Dan Carpenter (1):
arm64: dts: s32g: Add device tree information for the OCOTP driver
.../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 ++++++++ arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 ++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 ++ drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/s32g-ocotp-nvmem.c | 101 ++++++++++++++++++ 6 files changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c
Signature · 1 line
2.47.2
PATCH v2 1/3 dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
From: Ciprian Costea <[email protected]>
Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible.
---
v2: dt_binding_check DT_SCHEMA_FILES=nxp,s32g-ocotp-nvmem.yaml is clean
make CHECK_DTBS=y freescale/*.dtb is clean. Particularly the
freescale/s32g274a-evb.dtb file which Rob mentioned.
remove bogus include file
remove redundant "reg" description
remove #address-cells and #size-cells since they are already in nvmem.yaml
Fix email From header
.../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +45 -0
@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G OCOTP NVMEM driver + +maintainers: + - Ciprian Costea <[email protected]> + +description: | + The drivers provides an interface to access One Time + Programmable memory pages, such as TMU fuse values. + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-ocotp + - items: + - enum: + - nxp,s32r45-ocotp + - nxp,s32g3-ocotp + - const: nxp,s32g2-ocotp + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + };
Signature · 1 line
2.47.2
Frank Li
maintainerRe: [PATCH V2 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
Quoted 31 lines · Dan Carpenter
From: Ciprian Costea <[email protected]>
Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible.
Signed-off-by Ciprian Costea <[email protected]>Signed-off-by Dan Carpenter <[email protected]>---
v2:dt_binding_checkDT_SCHEMA_FILES=nxp,s32g-ocotp-nvmem.yaml is clean
make CHECK_DTBS=y freescale/*.dtb is clean. Particularly the
freescale/s32g274a-evb.dtb file which Rob mentioned.
remove bogus include file
remove redundant "reg" description
remove #address-cells and #size-cells since they are already innvmem.yaml
Fix email From header.../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yamlDocumentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +2
-0@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml line 12
Quoted 10 lines
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +10
-0+--- +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G OCOTP NVMEM driver + +maintainers: + - Ciprian Costea <[email protected]> + +description: |
Needn't |
https://yaml.org/spec/1.2.2/#scalars show "|" ">" "" 's difference.
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml line 17
Quoted 5 lines
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +5
-0+ The drivers provides an interface to access One Time + Programmable memory pages, such as TMU fuse values. + +allOf: + - $ref: nvmem.yaml#
Move just before examples in case need if-else later.
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml line 27
Quoted 10 lines
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +10
-0+ +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-ocotp + - items: + - enum: + - nxp,s32r45-ocotp + - nxp,s32g3-ocotp
Keep alphabet order for enum
Frank
Quoted 21 lines
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +18
-1+ - const: nxp,s32g2-ocotp + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; --2.47.2
Re: [PATCH V2 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
In reply to Dan CarpenterQuoted 59 lines · Dan Carpenter
From: Ciprian Costea <[email protected]>
Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible.
Signed-off-by Ciprian Costea <[email protected]>Signed-off-by Dan Carpenter <[email protected]>---
v2:dt_binding_checkDT_SCHEMA_FILES=nxp,s32g-ocotp-nvmem.yaml is clean
make CHECK_DTBS=y freescale/*.dtb is clean. Particularly the
freescale/s32g274a-evb.dtb file which Rob mentioned.
remove bogus include file
remove redundant "reg" description
remove #address-cells and #size-cells since they are already innvmem.yaml
Fix email From header.../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yamlDocumentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +30
-0@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G OCOTP NVMEM driver + +maintainers: + - Ciprian Costea <[email protected]> + +description: | + The drivers provides an interface to access One Time + Programmable memory pages, such as TMU fuse values. + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-ocotp + - items: + - enum: + - nxp,s32r45-ocotp + - nxp,s32g3-ocotp + - const: nxp,s32g2-ocotp + reg: + maxItems: 1
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml line 40
Quoted 10 lines
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +10
-0+ +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + ocotp: nvmem@400a4000 {
If you respin, drop the "ocotp" label, since the example doesn't use it.
PATCH v2 2/3 nvmem: s32g-ocotp: Add driver for S32G OCOTP
In reply to Dan CarpenterFrom: Ciprian Costea <[email protected]>
Provide access to the On Chip One-Time Programmable Controller (OCOTP) pages on the NXP S32G platform.
---
v2: Add S-o-b tags for Ghennadi and Larisa.
Use keepouts instead of the s32g_map[] table. This allows a bunch of code to be deleted.
Version 1 only let one word (S32G_OCOTP_WORD_SIZE or 4) to be read at a time, but now the driver allows larger reads. Set the .word_size in s32g_ocotp_nvmem_config to be 4 instead.
Krzysztof asked for some changes in the probe() function but that code was deleted instead.
drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/s32g-ocotp-nvmem.c | 101 +++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c
drivers/nvmem/Kconfig +10 -0
@@ -240,6 +240,16 @@ config NVMEM_NINTENDO_OTP This driver can also be built as a module. If so, the module will be called nvmem-nintendo-otp. +config NVMEM_S32G_OCOTP + tristate "S32G SoC OCOTP support" + depends on ARCH_S32 + help + This is a driver for the 'OCOTP' peripheral available on S32G + platforms. + + If you say Y here, you will get support for the One Time + Programmable memory pages. + config NVMEM_QCOM_QFPROM tristate "QCOM QFPROM Support" depends on ARCH_QCOM || COMPILE_TEST
drivers/nvmem/Makefile +2 -0
@@ -79,6 +79,8 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o nvmem_sunplus_ocotp-y := sunplus-ocotp.o obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o nvmem_sunxi_sid-y := sunxi_sid.o +obj-$(CONFIG_NVMEM_S32G_OCOTP) += nvmem-s32g-ocotp-nvmem.o +nvmem-s32g-ocotp-nvmem-y := s32g-ocotp-nvmem.o obj-$(CONFIG_NVMEM_U_BOOT_ENV) += nvmem_u-boot-env.o nvmem_u-boot-env-y := u-boot-env.o obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o
drivers/nvmem/s32g-ocotp-nvmem.c new file +101 -0
101 lines not on this page · raw message
Signature · 1 line
2.47.2
Frank Li
maintainerQuoted 38 lines · Dan Carpenter
From: Ciprian Costea <[email protected]>
Provide access to the On Chip One-Time Programmable Controller (OCOTP) pages on the NXP S32G platform.
Signed-off-by Ciprian Costea <[email protected]>Co-developed-by Ghennadi Procopciuc <[email protected]>Signed-off-by Ghennadi Procopciuc <[email protected]>Co-developed-by Larisa Grigore <[email protected]>Signed-off-by Larisa Grigore <[email protected]>Signed-off-by Dan Carpenter <[email protected]>---
v2: Add S-o-b tags for Ghennadi and Larisa.Use keepouts instead of the s32g_map[] table. This allows a bunch of code to be deleted.
Version 1 only let one word (
S32G_OCOTP_WORD_SIZEor 4) to be read at a time, but now the driver allows larger reads. Set the .word_size ins32g_ocotp_nvmem_configto be 4 instead.Krzysztof asked for some changes in the
probe()function but that code was deleted instead.drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/s32g-ocotp-nvmem.c | 101 +++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.cdrivers/nvmem/Kconfig +0
-0@@ -240,6 +240,16 @@ config NVMEM_NINTENDO_OTP This driver can also be built as a module. If so, the module will be called nvmem-nintendo-otp.
...
drivers/nvmem/Kconfig
Quoted 13 lines
drivers/nvmem/Kconfig +13
-0+ +static int s32g_ocotp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct s32g_ocotp_priv *s32g_data = context; + u32 *dst = val; + + while (bytes >= sizeof(u32)) { + *dst++ = ioread32(s32g_data->base + offset); + + bytes -= sizeof(u32); + offset += sizeof(u32); + }
readsw() ?
Quoted 38 lines
drivers/nvmem/Kconfig +38
-0+ + return 0; +} + +static struct nvmem_keepout s32g_keepouts[] = { + { .start = 0, .end = 520 }, + { .start = 540, .end = 564 }, + { .start = 596, .end = 664 }, + { .start = 668, .end = 676 }, + { .start = 684, .end = 732 }, + { .start = 744, .end = 864 }, + { .start = 908, .end = 924 }, + { .start = 928, .end = 936 }, + { .start = 948, .end = 964 }, + { .start = 968, .end = 976 }, + { .start = 984, .end = 1012 }, +}; + +static struct nvmem_config s32g_ocotp_nvmem_config = { + .name = "s32g-ocotp", + .add_legacy_fixed_of_cells = true, + .read_only = true, + .word_size = 4, + .reg_read = s32g_ocotp_read, + .keepout = s32g_keepouts, + .nkeepout = ARRAY_SIZE(s32g_keepouts), +}; + +static const struct of_device_id ocotp_of_match[] = { + { .compatible = "nxp,s32g2-ocotp" }, + { /* sentinel */ } +}; + +static int s32g_ocotp_probe(struct platform_device *pdev) +{ + struct s32g_ocotp_priv *s32g_data; + struct device *dev = &pdev->dev; + struct nvmem_device *nvmem;
drivers/nvmem/Kconfig
Quoted 10 lines
drivers/nvmem/Kconfig +10
-0+ struct resource *res; + + s32g_data = devm_kzalloc(dev, sizeof(*s32g_data), GFP_KERNEL); + if (!s32g_data) + return -ENOMEM; + + s32g_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(s32g_data->base)) { + dev_err(dev, "Cannot map OCOTP device.\n"); + return PTR_ERR(s32g_data->base);
return dev_err_probe(dev, PTR_ERR(s32g_data->base), ...)
Frank
Quoted 26 lines
drivers/nvmem/Kconfig +23
-1+ } + + s32g_data->dev = dev; + s32g_ocotp_nvmem_config.dev = dev; + s32g_ocotp_nvmem_config.priv = s32g_data; + s32g_ocotp_nvmem_config.size = resource_size(res); + + nvmem = devm_nvmem_register(dev, &s32g_ocotp_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static struct platform_driver s32g_ocotp_driver = { + .probe = s32g_ocotp_probe, + .driver = { + .name = "s32g-ocotp", + .of_match_table = ocotp_of_match, + }, +}; +module_platform_driver(s32g_ocotp_driver); +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("S32G OCOTP driver"); +MODULE_LICENSE("GPL"); --2.47.2
Quoted 6 lines · Frank Li
Quoted 6 lines
drivers/nvmem/s32g-ocotp-nvmem.c new file +6
-0+static int s32g_ocotp_read (void *context,unsigned int offset, +void *val,size_t bytes) +{ +struct s32g_ocotp_priv *s32g_data = context; +u32 *dst = val; +
Quoted 9 lines
drivers/nvmem/s32g-ocotp-nvmem.c line 30
Quoted 6 lines
drivers/nvmem/s32g-ocotp-nvmem.c new file +6
-0+while (bytes >=sizeof (u32)) { + *dst++ =ioread32 (s32g_data->base + offset); + + bytes -=sizeof (u32); + offset +=sizeof (u32); + }
readsw()?
Hi Frank,
I've learned a lot from your reviews. Thanks. :) It would be readsl() since it's a u32. But readsl() doesn't increment the offset, it just reads from the same memory address over and over.
I've made all the other changes.
regards,
dan carpenter
PATCH v2 3/3 arm64: dts: s32g: Add device tree information for the OCOTP driver
In reply to Dan CarpenterAdd the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip.
---
v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"
arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++ 2 files changed, 14 insertions(+)
arch/arm64/boot/dts/freescale/s32g2.dtsi +7 -0
@@ -701,5 +701,12 @@ gic: interrupt-controller@50800000 { interrupt-controller; #interrupt-cells = <3>; }; + + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; }; };
arch/arm64/boot/dts/freescale/s32g3.dtsi +7 -0
@@ -765,6 +765,13 @@ gic: interrupt-controller@50800000 { <0x50420000 0x2000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; }; timer {
Signature · 1 line
2.47.2
Frank Li
maintainerRe: [PATCH V2 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver
Quoted 16 lines · Dan Carpenter
Add the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip.
Signed-off-by Dan Carpenter <[email protected]>---
v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++ 2 files changed, 14 insertions(+)arch/arm64/boot/dts/freescale/s32g2.dtsi +0
-0
arch/arm64/boot/dts/freescale/s32g2.dtsi gic: interrupt-controller@50800000 { · line 710
Quoted 10 lines
arch/arm64/boot/dts/freescale/s32g2.dtsi +7
-0@@ -701,5 +701,12 @@ gic: interrupt-controller@50800000 { interrupt-controller; #interrupt-cells = <3>; }; + + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + };
Please keep order according to address, 0x400a4000 < 0x50800000
Frank Li
Quoted 23 lines
arch/arm64/boot/dts/freescale/s32g2.dtsi +0
-0}; };arch/arm64/boot/dts/freescale/s32g3.dtsi +7
-1@@ -765,6 +765,13 @@ gic: interrupt-controller@50800000 { <0x50420000 0x2000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; }; timer { --2.47.2