Add 4-bit SPI bus width on target devices
Subsystems (2)
v2 cover Add 4-bit SPI bus width on target devices
From: "Fong, Yan Kei" <[email protected]>
Add SPI bus width properties to correctly describe the hardware on the following devices:
- Stratix10
- Agilex
- Agilex5
- N5X
---
changes in v2:
- rewrite the commit message body to align with 80 characters.
- add additional reviewer
---
Fong, Yan Kei (4):
arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 ++ arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 ++ 4 files changed, 8 insertions(+)
Signature · 1 line
2.25.1
PATCH v2 1/4 arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
From: "Fong, Yan Kei" <[email protected]>
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the n5x device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely.
--- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +2 -0
@@ -93,6 +93,8 @@ flash@0 { cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions";
Signature · 1 line
2.25.1
PATCH v2 2/4 arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
In reply to [email protected]From: "Fong, Yan Kei" <[email protected]>
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the stratix10 device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely.
--- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +2 -0
@@ -190,6 +190,8 @@ flash@0 { cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions";
Signature · 1 line
2.25.1
PATCH v2 3/4 arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
In reply to [email protected]From: "Fong, Yan Kei" <[email protected]>
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely.
--- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +2 -0
@@ -116,6 +116,8 @@ flash@0 { cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions";
Signature · 1 line
2.25.1
PATCH v2 4/4 arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
In reply to [email protected]From: "Fong, Yan Kei" <[email protected]>
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex5 device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely.
--- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +2 -0
@@ -57,6 +57,8 @@ flash@0 { cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions";
Signature · 1 line
2.25.1
Dinh Nguyen
maintainerQuoted 10 lines · Yan Kei
Add SPI bus width properties to correctly describe the hardware on the following devices:
- Stratix10
- Agilex
- Agilex5
- N5XSigned-off-by Fong, Yan Kei <[email protected]>Reviewed-by Khairul Anuar Romli <[email protected]>Reviewed-by Matthew Gerlach <[email protected]>
Quoted 7 lines
---
changes in v3:
- remove the unalign email shown in the commit message body
changes in v2:
- rewrite the commit message body to align with 80 characters.
- add additional reviewer
You have a series of v2 and v3 patches in the same thread. Which ones should I look at?
Quoted 18 lines · Yan Kei
Quoted 18 lines
Quoted 17 lines
Add SPI bus width properties to correctly describe the hardware on the following devices:
- Stratix10
- Agilex
- Agilex5
- N5XSigned-off-by Fong, Yan Kei <[email protected]>Reviewed-by Khairul Anuar Romli <[email protected]>Reviewed-by Matthew Gerlach <[email protected]>---
changes in v3:
- remove the unalign email shown in the commit message body
changes in v2:
- rewrite the commit message body to align with 80 characters.
- add additional reviewer
---
Quoted 4 lines
Quoted 2 lines
You have a series of v2 and v3 patches in the same thread. Which ones should I look at?
Hi Dinh, you may look at v3 patches. Thank you.
Applied!
Thanks,
Dinh