Add PCIe support to Sophgo SG2042 SoC
Subsystems (6)
v3 cover Add PCIe support to Sophgo SG2042 SoC
From: Chen Wang <[email protected]>
Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.
This is a completely rewritten PCIe driver for SG2042. It inherits some previously submitted patch codes (not merged into the upstream mainline), but the biggest difference is that the support for compatibility with old 32-bit PCIe devices has been removed in this new version. This is because after discussing with community users, we felt that there was not much demand for support for old devices, so we made a new design based on the simplified design and practical needs. If someone really needs to play with old devices, we can provide them with some necessary hack patches in the downstream repository.
Since the new design is quite different from the old code, I will release it as a new patch series. The old patch series can be found in here [old-series].
Note, regarding [2/7] of this patchset, this fix is introduced because the pcie->ops pointer is not filled in SG2042 PCIe driver. This is not a must-have parameter, if we use it w/o checking will cause a null pointer access error during runtime.
Thanks,
Chen
---
Changes in v3:
This patchset is based on v6.17-rc1.
Fixed following issues for driver code based on feedbacks from Bjorn Helgaas, Mingcong Bai, thanks.
- Fixed the issue when building the driver as a module. Define own pm_ops inside driver, don't use the ops defined in other built-in drivers.
- Improve .remove() function to properly disable the host.
Changes in v2:
This patchset is based on v6.17-rc1. You can simply review or test the patches at the link [2].
Fixed following issues based on feedbacks from Rob Herring, Manivannan Sadhasivam, Bjorn Helgaas, ALOK TIWARI, thanks.
- Driver binding:
- Removed vendor-id/device-id from "required" property.
- Improve drivers code:
- Have separated pci_ops for the root bus and child buses.
- Make the driver tristate and as a module.
- Change the configuration name from PCIE_SG2042 to PCIE_SG2042_HOST.
- Removed "Fixes" tag from commit [2/7], since this is not for an existing bug fix.
- Other code cleanups and optimizations
- DT:
- Add PCIe support for SG2042 EVB boards.
Changes in v1:
The patch series is based on v6.17-rc1. You can simply review or test the patches at the link [1].
---
Chen Wang (7):
dt-bindings: pci: Add Sophgo SG2042 PCIe host
PCI: cadence: Check pcie-ops before using it
PCI: sg2042: Add Sophgo SG2042 PCIe driver
riscv: sophgo: dts: add PCIe controllers for SG2042
riscv: sophgo: dts: enable PCIe for PioneerBox
riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
.../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 ++++++++ arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++ arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 +++++++++++ drivers/pci/controller/cadence/Kconfig | 10 ++ drivers/pci/controller/cadence/Makefile | 1 + .../controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 +- drivers/pci/controller/cadence/pcie-cadence.h | 6 +- drivers/pci/controller/cadence/pcie-sg2042.c | 138 ++++++++++++++++++ 11 files changed, 343 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c
base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
Signature · 1 line
2.34.1
PATCH v3 1/7 dt-bindings: pci: Add Sophgo SG2042 PCIe host
From: Chen Wang <[email protected]>
Add binding for Sophgo SG2042 PCIe host controller.
--- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml new file +64 -0
@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) + +description: + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-pcie-host + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: cfg + + vendor-id: + const: 0x1f1c + + device-id: + const: 0x2042 + + msi-parent: true + +allOf: + - $ref: cdns-pcie-host.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + pcie@62000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x62000000 0x00800000>, + <0x48000000 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + bus-range = <0x00 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + };
Signature · 1 line
2.34.1
PATCH v3 2/7 PCI: cadence: Check pcie-ops before using it
In reply to Chen WangFrom: Chen Wang <[email protected]>
ops of struct cdns_pcie may be NULL, direct use
will result in a null pointer error.
Add checking of pcie->ops before using it for new
driver that may not supply pcie->ops.
--- drivers/pci/controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 ++-- drivers/pci/controller/cadence/pcie-cadence.h | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-)
drivers/pci/controller/cadence/pcie-cadence-host.c +1 -1
@@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)cdns_pcie_writel (pcie,CDNS_PCIE_AT_OB_REGION_PCI_ADDR1 (0 ), addr1);cdns_pcie_writel (pcie,CDNS_PCIE_AT_OB_REGION_DESC1 (0 ), desc1); -if (pcie->ops->cpu_addr_fixup) +if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup (pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
drivers/pci/controller/cadence/pcie-cadence.c +2 -2
@@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,cdns_pcie_writel (pcie,CDNS_PCIE_AT_OB_REGION_DESC1 (r), desc1);/* Set the CPU address */ -if (pcie->ops->cpu_addr_fixup) +if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup (pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
@@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, }/* Set the CPU address */ -if (pcie->ops->cpu_addr_fixup) +if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup (pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
drivers/pci/controller/cadence/pcie-cadence.h +3 -3
@@ -468,7 +468,7 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)static inline int cdns_pcie_start_link (struct cdns_pcie *pcie) { -if (pcie->ops->start_link) +if (pcie->ops && pcie->ops->start_link)return pcie->ops->start_link (pcie);return 0 ;
@@ -476,13 +476,13 @@ static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)static inline void cdns_pcie_stop_link (struct cdns_pcie *pcie) { -if (pcie->ops->stop_link) +if (pcie->ops && pcie->ops->stop_link) pcie->ops->stop_link (pcie); }static inline bool cdns_pcie_link_up (struct cdns_pcie *pcie) { -if (pcie->ops->link_up) +if (pcie->ops && pcie->ops->link_up)return pcie->ops->link_up (pcie);return true;
Signature · 1 line
2.34.1
PATCH v3 3/7 PCI: sg2042: Add Sophgo SG2042 PCIe driver
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add support for PCIe controller in SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in host mode only, supporting data rate (16 GT/s) and lanes (x16 or x8).
--- drivers/pci/controller/cadence/Kconfig | 10 ++ drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pcie-sg2042.c | 138 +++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c
drivers/pci/controller/cadence/Kconfig +10 -0
@@ -42,6 +42,15 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCIE_SG2042_HOST + tristate "Sophgo SG2042 PCIe controller (host mode)" + depends on OF && (ARCH_SOPHGO || COMPILE_TEST) + select PCIE_CADENCE_HOST + help + Say Y here if you want to support the Sophgo SG2042 PCIe platform + controller in host mode. Sophgo SG2042 PCIe controller uses Cadence + PCIe core. + config PCI_J721E tristate select PCIE_CADENCE_HOST if PCI_J721E_HOST != n
@@ -67,4 +76,5 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + endmenu
drivers/pci/controller/cadence/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o +obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o
drivers/pci/controller/cadence/pcie-sg2042.c new file +138 -0
138 lines not on this page · raw message
Signature · 1 line
2.34.1
PATCH v3 4/7 riscv: sophgo: dts: add PCIe controllers for SG2042
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled.
--- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+)
arch/riscv/boot/dts/sophgo/sg2042.dtsi +88 -0
@@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 { #clock-cells = <1>; }; + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
Signature · 1 line
2.34.1
Re: [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042
Quoted 20 lines · Chen Wang
From: Chen Wang <[email protected]>
Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled.
Signed-off-by Inochi Amaoto <[email protected]>Signed-off-by Han Gao <[email protected]>Signed-off-by Chen Wang <[email protected]>--- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+)arch/riscv/boot/dts/sophgo/sg2042.dtsi +0
-0@@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 { #clock-cells = <1>; };
arch/riscv/boot/dts/sophgo/sg2042.dtsi clkgen: clock-controller@7030012000 { · line 232
Quoted 10 lines
arch/riscv/boot/dts/sophgo/sg2042.dtsi +10
-0+ pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>,
PCI address of the I/O port starts from 0. So this should be:
<0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
Same comment for other nodes.
With this fixed,
- Mani
Quoted 84 lines
arch/riscv/boot/dts/sophgo/sg2042.dtsi +78
-0+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>;Signature · 1 line
2.34.1
Signature · 1 line
மணிவண்ணன் சதாசிவம்
Re: [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042
Quoted 35 lines · Manivannan Sadhasivam
Quoted 20 lines · Chen Wang
From: Chen Wang <[email protected]>
Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled.
Signed-off-by Inochi Amaoto <[email protected]>Signed-off-by Han Gao <[email protected]>Signed-off-by Chen Wang <[email protected]>--- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+)arch/riscv/boot/dts/sophgo/sg2042.dtsi +0
-0@@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 { #clock-cells = <1>; };arch/riscv/boot/dts/sophgo/sg2042.dtsi clkgen: clock-controller@7030012000 { · line 232
Quoted 10 lines
arch/riscv/boot/dts/sophgo/sg2042.dtsi +10
-0+ pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>,PCI address of the I/O port starts from 0. So this should be:
<0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
Quoted 7 lines
Same comment for other nodes.
With this fixed,
- Mani
Thanks, I will fix this in next version.
[......]
PATCH v3 5/7 riscv: sophgo: dts: enable PCIe for PioneerBox
In reply to Chen WangFrom: Chen Wang <[email protected]>
Enable PCIe controllers for PioneerBox, which uses SG2042 SoC.
--- arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +12 -0
@@ -128,6 +128,18 @@ uart0-rx-pins { }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + +&pcie_rc3 { + status = "okay"; +}; + &sd { pinctrl-0 = <&sd_cfg>; pinctrl-names = "default";
Signature · 1 line
2.34.1
PATCH v3 6/7 riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
In reply to Chen WangFrom: Chen Wang <[email protected]>
Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board, which uses SG2042 SoC.
--- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +12 -0
@@ -164,6 +164,18 @@ phy0: phy@0 { }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins {
Signature · 1 line
2.34.1
PATCH v3 7/7 riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
In reply to Chen WangFrom: Chen Wang <[email protected]>
Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board, which uses SG2042 SoC.
--- arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +12 -0
@@ -152,6 +152,18 @@ phy0: phy@0 { }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins {
Signature · 1 line
2.34.1
Hello, Bjorn,
Is it ok for you to pick this patchset, so we can see this in next 6.18.
You can pick [1/7]~[3/7], I can handle the left dts part.
Thanks,
Chen
Quoted 96 lines · Chen Wang
From: Chen Wang <[email protected]>
Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.
This is a completely rewritten PCIe driver for SG2042. It inherits some previously submitted patch codes (not merged into the upstream mainline), but the biggest difference is that the support for compatibility with old 32-bit PCIe devices has been removed in this new version. This is because after discussing with community users, we felt that there was not much demand for support for old devices, so we made a new design based on the simplified design and practical needs. If someone really needs to play with old devices, we can provide them with some necessary hack patches in the downstream repository.
Since the new design is quite different from the old code, I will release it as a new patch series. The old patch series can be found in here [old-series].
Note, regarding [2/7] of this patchset, this fix is introduced because the
pcie->opspointer is not filled in SG2042 PCIe driver. This is not a must-have parameter, if we use it w/o checking will cause a null pointer access error during runtime.Link https://lore.kernel.org/linux-riscv/[email protected]/ [old-series] open hereThanks,
Chen---
Changes in v3:
This patchset is based on v6.17-rc1.
Fixed following issues for driver code based on feedbacks from Bjorn Helgaas, Mingcong Bai, thanks.
- Fixed the issue when building the driver as a module. Define own
pm_opsinside driver, don't use the ops defined in other built-in drivers.
- Improve .remove() function to properly disable the host.Changes in v2:
This patchset is based on v6.17-rc1. You can simply review or test the patches at the link [2].
Fixed following issues based on feedbacks from Rob Herring, Manivannan Sadhasivam, Bjorn Helgaas, ALOK TIWARI, thanks.
- Driver binding:
- Removed vendor-id/device-id from "required" property.
- Improve drivers code:
- Have separatedpci_opsfor the root bus and child buses.
- Make the driver tristate and as a module.
- Change the configuration name fromPCIE_SG2042toPCIE_SG2042_HOST.
- Removed "Fixes" tag from commit [2/7], since this is not for an existing bug fix.
- Other code cleanups and optimizations
- DT:
- Add PCIe support for SG2042 EVB boards.Changes in v1:
The patch series is based on v6.17-rc1. You can simply review or test the patches at the link [1].
---
Chen Wang (7):
dt-bindings: pci: Add Sophgo SG2042 PCIe host
PCI: cadence: Check pcie-ops before using it
PCI: sg2042: Add Sophgo SG2042 PCIe driver
riscv: sophgo: dts: add PCIe controllers for SG2042
riscv: sophgo: dts: enable PCIe for PioneerBox
riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0.../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 ++++++++ arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++ arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 +++++++++++ drivers/pci/controller/cadence/Kconfig | 10 ++ drivers/pci/controller/cadence/Makefile | 1 + .../controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 +- drivers/pci/controller/cadence/pcie-cadence.h | 6 +- drivers/pci/controller/cadence/pcie-sg2042.c | 138 ++++++++++++++++++ 11 files changed, 343 insertions(+), 6 deletions(-)create mode 100644
Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yamlcreate mode 100644drivers/pci/controller/cadence/pcie-sg2042.cbase-commit:
8f5ae30d69d7543eee0d70083daf4de8fe15d585
Re: (subset) [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC
In reply to Chen WangQuoted 14 lines · Chen Wang
From: Chen Wang <[email protected]>
Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.
This is a completely rewritten PCIe driver for SG2042. It inherits some previously submitted patch codes (not merged into the upstream mainline), but the biggest difference is that the support for compatibility with old 32-bit PCIe devices has been removed in this new version. This is because after discussing with community users, we felt that there was not much demand for support for old devices, so we made a new design based on the simplified design and practical needs. If someone really needs to play with old devices, we can provide them with some necessary hack patches in the downstream repository.
Quoted 1 line
[...]
Applied, thanks!
[1/7] dt-bindings: pci: Add Sophgo SG2042 PCIe host
commit: 4e4a4f58bed19e1a3a5a7c3a18ce3b927b76fcd3
[2/7] PCI: cadence: Check pcie-ops before using it
commit: 49a6c160ad4812476f8ae1a8f4ed6d15adfa6c09
[3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver
commit: 1c72774df028429836eec3394212f2921bb830fcBest regards,
Signature · 1 line
Manivannan Sadhasivam <[email protected]>