i3c: dw: Add Altera Agilex5 runtime PM disable quirk

From: Adrian Ng Ho Yin <[email protected]>

This patchset adds support for an Altera SoCFPGA-specific quirk in the Synopsys DesignWare I3C master driver.

While running the I3C compliance test suite on the Altera Agilex5 SoCFPGA, the I3C bus was observed to hang when a slave device issued an IBI after the Dynamic Address Assignment (DAA) process completed.

This issue occurs because the controller enters a suspended state after DAA due to runtime PM being enabled. When suspended, the controller stops driving the SCL line. As a result, an IBI transfer cannot complete, leaving the SDA line stuck low and the bus in a hung state.

To address this issue, a new compatible string, "altr,agilex5-dw-i3c-master", is introduced to identify the SoC variant. When this compatible string is matched, a new quirk (DW_I3C_DISABLE_RUNTIME_PM_QUIRK) is applied to keep the controller enabled by incrementing the runtime PM reference counter during probe. This ensures the controller remains active to reliably handle IBI transactions without requiring runtime PM checks throughout the driver.

---
changelog:
v3->v4:
*Add reviewed by tag for dt binding.
*Aligned compatible string in dtsi with previous line.
*Update commit message for better clarity.
*Updated implementation to increment the PM reference counter during probe instead of conditionally bypassing runtime PM APIs. This simplifies the logic and ensures consistent behavior when the disable-runtime-PM quirk is applied.
v2->v3:
*Dropped RFC tag.
*Update compatible string to "altr,agilex5-dw-i3c-master" to match actual SoC. *Update commit message to describe changes correctly.
v1->v2:
*Add new compatible string in dw i3c dt binding to validate against newly added compatible string.
*Added new compatible string for altr socfpga platform.
*Remove Kconfig that disables runtime PM added in v1.
*Update implementation to disable runtime PM via compatible string match so that the implementation can be tied to a specific compatible string so that it does impact the existing behavior for other users.

See previous patch series at:
https://lore.kernel.org/all/22286d459959f2a153ac59d7da46794c0f495c77.1760579799.git.adrianhoyin.ng@altera.com/
---

Adrian Ng Ho Yin (3):
dt-bindings: i3c: snps: Add Altera SoCFPGA compatible
arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers
i3c: dw: Add runtime PM disable quirk for Altera Agilex5

 .../devicetree/bindings/i3c/snps,dw-i3c-master.yaml  |  6 +++++-
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi       |  6 ++++--
 drivers/i3c/master/dw-i3c-master.c                   | 12 ++++++++++++
 3 files changed, 21 insertions(+), 3 deletions(-)

2.49.GIT

From: Adrian Ng Ho Yin <[email protected]>

Add the "altr,agilex5-dw-i3c-master" compatible string to the Synopsys DesignWare I3C master binding. This allow Agilex5 to use the generic DW I3C master controller while applying any required platform-specific quirks.

---
 .../devicetree/bindings/i3c/snps,dw-i3c-master.yaml         | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

index 5f6467375811..e803457d3f55 100644
@@ -14,7 +14,11 @@ allOf:
 
 properties:
   compatible:
-    const: snps,dw-i3c-master-1.00a
+    oneOf:
+      - const: snps,dw-i3c-master-1.00a
+      - items:
+          - const: altr,agilex5-dw-i3c-master
+          - const: snps,dw-i3c-master-1.00a
 
   reg:
     maxItems: 1

2.49.GIT

From: Adrian Ng Ho Yin <[email protected]>

Add the "altr,agilex5-dw-i3c-master" compatible string to the I3C controller nodes on the Agilex5 SoCFPGA platform.

---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

index 04e99cd7e74b..5c8ad5e9b248 100644
@@ -203,7 +203,8 @@ i2c4: i2c@10c02c00 {
 		};
 
 		i3c0: i3c@10da0000 {
-			compatible = "snps,dw-i3c-master-1.00a";
+			compatible = "altr,agilex5-dw-i3c-master",
+				     "snps,dw-i3c-master-1.00a";
 			reg = <0x10da0000 0x1000>;
 			#address-cells = <3>;
 			#size-cells = <0>;

@@ -213,7 +214,8 @@ i3c0: i3c@10da0000 {
 		};
 
 		i3c1: i3c@10da1000 {
-			compatible = "snps,dw-i3c-master-1.00a";
+			compatible = "altr,agilex5-dw-i3c-master",
+				     "snps,dw-i3c-master-1.00a";
 			reg = <0x10da1000 0x1000>;
 			#address-cells = <3>;
 			#size-cells = <0>;

2.49.GIT

From: Adrian Ng Ho Yin <[email protected]>

When running compliance tests on the Altera Agilex5 SoCFPGA platform, it was observed that the I3C bus could enter a hung state when a slave device issues an IBI after the DAA process completes. This occurs because the DesignWare I3C master controller enters runtime suspend once the DAA sequence finishes, causing it to stop driving the SCL line. As a result, the IBI transfer cannot complete, leaving the SDA line stuck low and the bus in a hung state.

To address this, introduce a new compatible string, "altr,agilex5-dw-i3c-master", that applies a quirk to disable runtime PM for this platform. The quirk keeps the controller enabled by calling pm_runtime_get_noresume() during probe and balancing it with pm_runtime_put_noidle() during remove.

This ensures that the controller remains active and avoids bus hangs triggered by IBIs while maintaining normal behavior for other platforms.

---
 drivers/i3c/master/dw-i3c-master.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

index 9ceedf09c3b6..5913822648ca 100644
@@ -228,6 +228,7 @@
 
 /* List of quirks */
 #define AMD_I3C_OD_PP_TIMING		BIT(1)
+#define DW_I3C_DISABLE_RUNTIME_PM_QUIRK	BIT(2)
 
 struct dw_i3c_cmd {
 	u32 cmd_lo;

@@ -1592,6 +1593,10 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
 
 	master->quirks = (unsigned long)device_get_match_data(&pdev->dev);
 
+	/* Keep controller enabled by preventing runtime suspend */
+	if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
+		pm_runtime_get_noresume(&pdev->dev);
+
 	INIT_WORK(&master->hj_work, dw_i3c_hj_work);
 	ret = i3c_master_register(&master->base, &pdev->dev,
 				  &dw_mipi_i3c_ops, false);

@@ -1617,6 +1622,10 @@ void dw_i3c_common_remove(struct dw_i3c_master *master)
 	cancel_work_sync(&master->hj_work);
 	i3c_master_unregister(&master->base);
 
+	/* Balance pm_runtime_get_noresume() from probe() */
+	if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
+		pm_runtime_put_noidle(master->dev);
+
 	pm_runtime_disable(master->dev);
 	pm_runtime_set_suspended(master->dev);
 	pm_runtime_dont_use_autosuspend(master->dev);

@@ -1761,6 +1770,9 @@ static void dw_i3c_shutdown(struct platform_device *pdev)
 
 static const struct of_device_id dw_i3c_master_of_match[] = {
 	{ .compatible = "snps,dw-i3c-master-1.00a", },
+	{ .compatible = "altr,agilex5-dw-i3c-master",
+	  .data = (void *)DW_I3C_DISABLE_RUNTIME_PM_QUIRK,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);

2.49.GIT

suggest commit message

i3c: dw: Disable runtime PM on Agilex5 to avoid bus hang on IBI

When running compliance tests on the Altera Agilex5 SoCFPGA platform, the I3C bus can hang when a slave issues an IBI after the DAA process completes. The DesignWare I3C master enters runtime suspend once DAA finishes and stops driving SCL, preventing the IBI transfer from completing and leaving SDA stuck low.

Add a new compatible string, "altr,agilex5-dw-i3c-master" and apply a quirk that keep runtime PM always active on this platform by calling pm_runtime_get_noresume() during probe.

Prevent bus hangs triggered by IBIs on Agilex5 while maintaining keep the same behavior on other platforms.

struct dw_i3c_drvdata {
	u32 flags;
}