Add Agilex5 AXI DMA support

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask.

Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver.

Add dma-ranges to the binding schema to allow specifying DMA address mapping between the controller and its parent bus.

Signed-off-by Khairul Anuar Romli <[email protected]>

---
Changes in v3:
- Simple dma-ranges property with true and without description
Changes in v2:
- Add dma-ranges

---
 .../bindings/dma/snps,dw-axi-dmac.yaml           | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +9 -5

index a393a33c8908..1f4dcf3092c3 100644
@@ -17,11 +17,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - snps,axi-dma-1.01a
-      - intel,kmb-axi-dma
-      - starfive,jh7110-axi-dma
-      - starfive,jh8100-axi-dma
+    oneOf:
+      - enum:
+          - snps,axi-dma-1.01a
+          - intel,kmb-axi-dma
+          - starfive,jh7110-axi-dma
+          - starfive,jh8100-axi-dma
+      - items:
+          - const: altr,agilex5-axi-dma
+          - const: snps,axi-dma-1.01a
 
   reg:
     minItems: 1

Quoted 51 lines · Khairul Anuar Romli

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask.

Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver.

Add dma-ranges to the binding schema to allow specifying DMA address mapping between the controller and its parent bus.

Signed-off-by Khairul Anuar Romli <[email protected]>

---
Changes in v3:
- Simple dma-ranges property with true and without description
Changes in v2:
- Add dma-ranges

---
  .../bindings/dma/snps,dw-axi-dmac.yaml           | 16 +++++++++++-----
  1 file changed, 11 insertions(+), 5 deletions(-)

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +9 -5

index a393a33c8908..1f4dcf3092c3 100644
@@ -17,11 +17,15 @@ allOf:
 
  properties:
    compatible:
-    enum:
-      - snps,axi-dma-1.01a
-      - intel,kmb-axi-dma
-      - starfive,jh7110-axi-dma
-      - starfive,jh8100-axi-dma
+    oneOf:
+      - enum:
+          - snps,axi-dma-1.01a
+          - intel,kmb-axi-dma
+          - starfive,jh7110-axi-dma
+          - starfive,jh8100-axi-dma
+      - items:
+          - const: altr,agilex5-axi-dma
+          - const: snps,axi-dma-1.01a
 
    reg:
      minItems: 1

@@ -104,6 +108,8 @@ properties:
      minimum: 1
      maximum: 256
 

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml properties: · line 112

Quoted 2 lines

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +2 -0

+  dma-ranges: true
+

You no longer need this because it is in the bus node.

Rob

Add device tree compatible string support for the Altera Agilex5 AXI DMA controller.

Introduces logic to parse the "dma-ranges" property and calculate the actual number of addressable bits (bus width) for the DMA engine. This calculated value is then used to set the coherent mask via 'dma_set_mask_and_coherent()', allowing the driver to correctly handle devices with bus widths less than 64 bits. The addressable bits default to 64 if 'dma-ranges' is not specified or cannot be parsed.

Introduce 'addressable_bits' to 'struct axi_dma_chip' to store this value.

Signed-off-by Khairul Anuar Romli <[email protected]>

---
Changes in v3:
- Refactor the code to align with dma controller device node move to 1 level down.
Changes in v2:
- Add driver implementation to set the DMA BIT MAST to 40 based on dma-ranges defined in DT.
- Add glue for driver and DT.

---
 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 69 ++++++++++++++++++-
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
 2 files changed, 69 insertions(+), 1 deletion(-)

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +33 -1

index b23536645ff7..96b0a0842ff5 100644
@@ -271,7 +271,9 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip)
 		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
 		axi_chan_disable(&chip->dw->chan[i]);
 	}
-	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+
+	dev_dbg(chip->dev, "Adressable bus width: %u\n", chip->addressable_bits);
+	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(chip->addressable_bits));
 	if (ret)
 		dev_warn(chip->dev, "Unable to set coherent mask\n");
 }

@@ -1461,13 +1463,24 @@ static int axi_req_irqs(struct platform_device *pdev, struct axi_dma_chip *chip)
 	return 0;
 }
 
+/* Forward declaration (no size required) */
+static const struct of_device_id dw_dma_of_id_table[];
+
 static int dw_probe(struct platform_device *pdev)
 {
 	struct axi_dma_chip *chip;
 	struct dw_axi_dma *dw;
 	struct dw_axi_dma_hcfg *hdata;
 	struct reset_control *resets;
+	struct device_node *parent;
+	const struct of_device_id *match;
 	unsigned int flags;
+	unsigned int addressable_bits = 64;
+	unsigned int len_bytes;
+	unsigned int num_cells;
+	const __be32 *prop;
+	u64 bus_width;
+	u32 *cells;
 	u32 i;
 	int ret;
 

@@ -1483,9 +1496,61 @@ static int dw_probe(struct platform_device *pdev)
 	if (!hdata)
 		return -ENOMEM;
 
+	match = of_match_node(dw_dma_of_id_table, pdev->dev.of_node);
+	if (!match) {
+		dev_err(&pdev->dev, "Unsupported AXI DMA device\n");
+		return -ENODEV;
+	}
+
+	parent = of_get_parent(pdev->dev.of_node);
+	if (parent) {
+		prop = of_get_property(parent, "dma-ranges", &len_bytes);
+		if (prop) {
+			num_cells = len_bytes / sizeof(__be32);
+			cells = kcalloc(num_cells, sizeof(*cells), GFP_KERNEL);
+			if (!cells)
+				return -ENOMEM;
+
+			ret = of_property_read_u32(parent, "#address-cells", &i);
+			if (ret) {
+				dev_err(&pdev->dev, "missing #address-cells property\n");
+				return ret;

Quoted 94 lines · Khairul Anuar Romli

Add device tree compatible string support for the Altera Agilex5 AXI DMA controller.

Introduces logic to parse the "dma-ranges" property and calculate the actual number of addressable bits (bus width) for the DMA engine. This calculated value is then used to set the coherent mask via 'dma_set_mask_and_coherent()', allowing the driver to correctly handle devices with bus widths less than 64 bits. The addressable bits default to 64 if 'dma-ranges' is not specified or cannot be parsed.

Introduce 'addressable_bits' to 'struct axi_dma_chip' to store this value.

Signed-off-by Khairul Anuar Romli <[email protected]>

---
Changes in v3:
- Refactor the code to align with dma controller device node move to 1 level down.
Changes in v2:
- Add driver implementation to set the DMA BIT MAST to 40 based on dma-ranges defined in DT.
- Add glue for driver and DT.

---
 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 69 ++++++++++++++++++-
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
 2 files changed, 69 insertions(+), 1 deletion(-)

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +38 -1

index b23536645ff7..96b0a0842ff5 100644
@@ -271,7 +271,9 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip)
              axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
              axi_chan_disable(&chip->dw->chan[i]);
      }
-     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+
+     dev_dbg(chip->dev, "Adressable bus width: %u\n", chip->addressable_bits);
+     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(chip->addressable_bits));
      if (ret)
              dev_warn(chip->dev, "Unable to set coherent mask\n");
 }

@@ -1461,13 +1463,24 @@ static int axi_req_irqs(struct platform_device *pdev, struct axi_dma_chip *chip)
      return 0;
 }
 
+/* Forward declaration (no size required) */
+static const struct of_device_id dw_dma_of_id_table[];
+
 static int dw_probe(struct platform_device *pdev)
 {
      struct axi_dma_chip *chip;
      struct dw_axi_dma *dw;
      struct dw_axi_dma_hcfg *hdata;
      struct reset_control *resets;
+     struct device_node *parent;
+     const struct of_device_id *match;
      unsigned int flags;
+     unsigned int addressable_bits = 64;
+     unsigned int len_bytes;
+     unsigned int num_cells;
+     const __be32 *prop;
+     u64 bus_width;
+     u32 *cells;
      u32 i;
      int ret;
 

@@ -1483,9 +1496,61 @@ static int dw_probe(struct platform_device *pdev)
      if (!hdata)
              return -ENOMEM;
 
+     match = of_match_node(dw_dma_of_id_table, pdev->dev.of_node);
+     if (!match) {
+             dev_err(&pdev->dev, "Unsupported AXI DMA device\n");
+             return -ENODEV;
+     }
+
+     parent = of_get_parent(pdev->dev.of_node);
+     if (parent) {
+             prop = of_get_property(parent, "dma-ranges", &len_bytes);
+             if (prop) {
+                     num_cells = len_bytes / sizeof(__be32);
+                     cells = kcalloc(num_cells, sizeof(*cells), GFP_KERNEL);
+                     if (!cells)
+                             return -ENOMEM;
+
+                     ret = of_property_read_u32(parent, "#address-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #address-cells property\n");
+                             return ret;
+                     }
+
+                     ret = of_property_read_u32(parent, "#size-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #size-cells property\n");

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c static int dw_probe(struct platform_device *pdev) · line 1527

Quoted 5 lines

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +5 -0

+                             return ret;
+                     }
+
+                     if (!of_property_read_u32_array(parent, "dma-ranges",
+                                                     cells, num_cells)) {

We have common code to parse dma-ranges. Use it and don't implement your own.

Quoted 96 lines · Rob Herring

Quoted 94 lines · Khairul Anuar Romli

Add device tree compatible string support for the Altera Agilex5 AXI DMA controller.

Introduces logic to parse the "dma-ranges" property and calculate the actual number of addressable bits (bus width) for the DMA engine. This calculated value is then used to set the coherent mask via 'dma_set_mask_and_coherent()', allowing the driver to correctly handle devices with bus widths less than 64 bits. The addressable bits default to 64 if 'dma-ranges' is not specified or cannot be parsed.

Introduce 'addressable_bits' to 'struct axi_dma_chip' to store this value.

Signed-off-by Khairul Anuar Romli <[email protected]>

---
Changes in v3:
- Refactor the code to align with dma controller device node move to 1 level down.
Changes in v2:
- Add driver implementation to set the DMA BIT MAST to 40 based on dma-ranges defined in DT.
- Add glue for driver and DT.

---
  .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 69 ++++++++++++++++++-
  drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
  2 files changed, 69 insertions(+), 1 deletion(-)

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +38 -1

index b23536645ff7..96b0a0842ff5 100644
@@ -271,7 +271,9 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip)
               axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
               axi_chan_disable(&chip->dw->chan[i]);
       }
-     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+
+     dev_dbg(chip->dev, "Adressable bus width: %u\n", chip->addressable_bits);
+     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(chip->addressable_bits));
       if (ret)
               dev_warn(chip->dev, "Unable to set coherent mask\n");
  }

@@ -1461,13 +1463,24 @@ static int axi_req_irqs(struct platform_device *pdev, struct axi_dma_chip *chip)
       return 0;
  }
 
+/* Forward declaration (no size required) */
+static const struct of_device_id dw_dma_of_id_table[];
+
  static int dw_probe(struct platform_device *pdev)
  {
       struct axi_dma_chip *chip;
       struct dw_axi_dma *dw;
       struct dw_axi_dma_hcfg *hdata;
       struct reset_control *resets;
+     struct device_node *parent;
+     const struct of_device_id *match;
       unsigned int flags;
+     unsigned int addressable_bits = 64;
+     unsigned int len_bytes;
+     unsigned int num_cells;
+     const __be32 *prop;
+     u64 bus_width;
+     u32 *cells;
       u32 i;
       int ret;
 

@@ -1483,9 +1496,61 @@ static int dw_probe(struct platform_device *pdev)
       if (!hdata)
               return -ENOMEM;
 
+     match = of_match_node(dw_dma_of_id_table, pdev->dev.of_node);
+     if (!match) {
+             dev_err(&pdev->dev, "Unsupported AXI DMA device\n");
+             return -ENODEV;
+     }
+
+     parent = of_get_parent(pdev->dev.of_node);
+     if (parent) {
+             prop = of_get_property(parent, "dma-ranges", &len_bytes);
+             if (prop) {
+                     num_cells = len_bytes / sizeof(__be32);
+                     cells = kcalloc(num_cells, sizeof(*cells), GFP_KERNEL);
+                     if (!cells)
+                             return -ENOMEM;
+
+                     ret = of_property_read_u32(parent, "#address-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #address-cells property\n");
+                             return ret;
+                     }
+
+                     ret = of_property_read_u32(parent, "#size-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #size-cells property\n");

Quoted 8 lines

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c static int dw_probe(struct platform_device *pdev) · line 1527

Quoted 5 lines

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +5 -0

+                             return ret;
+                     }
+
+                     if (!of_property_read_u32_array(parent, "dma-ranges",
+                                                     cells, num_cells)) {

We have common code to parse dma-ranges. Use it and don't implement your own.

Actually, the driver and DT core should take care of all this for you and there's nothing to do in the driver. A driver only needs to set the mask for the IP itself and only when >32 bits. The core takes care of any additional restrictions in the bus.

Rob

Quoted 111 lines · Rob Herring

Quoted 96 lines · Rob Herring

Quoted 94 lines · Khairul Anuar Romli

Add device tree compatible string support for the Altera Agilex5 AXI DMA controller.

Introduces logic to parse the "dma-ranges" property and calculate the actual number of addressable bits (bus width) for the DMA engine. This calculated value is then used to set the coherent mask via 'dma_set_mask_and_coherent()', allowing the driver to correctly handle devices with bus widths less than 64 bits. The addressable bits default to 64 if 'dma-ranges' is not specified or cannot be parsed.

Introduce 'addressable_bits' to 'struct axi_dma_chip' to store this value.

Signed-off-by Khairul Anuar Romli <[email protected]>

---
Changes in v3:
- Refactor the code to align with dma controller device node move to 1 level down.
Changes in v2:
- Add driver implementation to set the DMA BIT MAST to 40 based on dma-ranges defined in DT.
- Add glue for driver and DT.

---
  .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 69 ++++++++++++++++++-
  drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
  2 files changed, 69 insertions(+), 1 deletion(-)

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +38 -1

index b23536645ff7..96b0a0842ff5 100644
@@ -271,7 +271,9 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip)
               axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
               axi_chan_disable(&chip->dw->chan[i]);
       }
-     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+
+     dev_dbg(chip->dev, "Adressable bus width: %u\n", chip->addressable_bits);
+     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(chip->addressable_bits));
       if (ret)
               dev_warn(chip->dev, "Unable to set coherent mask\n");
  }

@@ -1461,13 +1463,24 @@ static int axi_req_irqs(struct platform_device *pdev, struct axi_dma_chip *chip)
       return 0;
  }
 
+/* Forward declaration (no size required) */
+static const struct of_device_id dw_dma_of_id_table[];
+
  static int dw_probe(struct platform_device *pdev)
  {
       struct axi_dma_chip *chip;
       struct dw_axi_dma *dw;
       struct dw_axi_dma_hcfg *hdata;
       struct reset_control *resets;
+     struct device_node *parent;
+     const struct of_device_id *match;
       unsigned int flags;
+     unsigned int addressable_bits = 64;
+     unsigned int len_bytes;
+     unsigned int num_cells;
+     const __be32 *prop;
+     u64 bus_width;
+     u32 *cells;
       u32 i;
       int ret;
 

@@ -1483,9 +1496,61 @@ static int dw_probe(struct platform_device *pdev)
       if (!hdata)
               return -ENOMEM;
 
+     match = of_match_node(dw_dma_of_id_table, pdev->dev.of_node);
+     if (!match) {
+             dev_err(&pdev->dev, "Unsupported AXI DMA device\n");
+             return -ENODEV;
+     }
+
+     parent = of_get_parent(pdev->dev.of_node);
+     if (parent) {
+             prop = of_get_property(parent, "dma-ranges", &len_bytes);
+             if (prop) {
+                     num_cells = len_bytes / sizeof(__be32);
+                     cells = kcalloc(num_cells, sizeof(*cells), GFP_KERNEL);
+                     if (!cells)
+                             return -ENOMEM;
+
+                     ret = of_property_read_u32(parent, "#address-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #address-cells property\n");
+                             return ret;
+                     }
+
+                     ret = of_property_read_u32(parent, "#size-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #size-cells property\n");

Quoted 8 lines

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c static int dw_probe(struct platform_device *pdev) · line 1527

Quoted 5 lines

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +5 -0

+                             return ret;
+                     }
+
+                     if (!of_property_read_u32_array(parent, "dma-ranges",
+                                                     cells, num_cells)) {

We have common code to parse dma-ranges. Use it and don't implement your own.

Actually, the driver and DT core should take care of all this for you and there's nothing to do in the driver. A driver only needs to set the mask for the IP itself and only when >32 bits. The core takes care of any additional restrictions in the bus.

Quoted 1 line

Rob

The current implementation explicitly set the mask to 64.

- ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));

Will the core re-set the mask based on the dma-ranges on DT?

Quoted 117 lines · Khairul Anuar

Quoted 106 lines · Rob Herring

Quoted 96 lines · Rob Herring

Quoted 94 lines · Khairul Anuar Romli

Add device tree compatible string support for the Altera Agilex5 AXI DMA controller.

Introduces logic to parse the "dma-ranges" property and calculate the actual number of addressable bits (bus width) for the DMA engine. This calculated value is then used to set the coherent mask via 'dma_set_mask_and_coherent()', allowing the driver to correctly handle devices with bus widths less than 64 bits. The addressable bits default to 64 if 'dma-ranges' is not specified or cannot be parsed.

Introduce 'addressable_bits' to 'struct axi_dma_chip' to store this value.

Signed-off-by Khairul Anuar Romli <[email protected]>

---
Changes in v3:
- Refactor the code to align with dma controller device node move to 1 level down.
Changes in v2:
- Add driver implementation to set the DMA BIT MAST to 40 based on dma-ranges defined in DT.
- Add glue for driver and DT.

---
   .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 69 ++++++++++++++++++-
   drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  1 +
   2 files changed, 69 insertions(+), 1 deletion(-)

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +38 -1

index b23536645ff7..96b0a0842ff5 100644
@@ -271,7 +271,9 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip)
                axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
                axi_chan_disable(&chip->dw->chan[i]);
        }
-     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
+
+     dev_dbg(chip->dev, "Adressable bus width: %u\n", chip->addressable_bits);
+     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(chip->addressable_bits));
        if (ret)
                dev_warn(chip->dev, "Unable to set coherent mask\n");
   }

@@ -1461,13 +1463,24 @@ static int axi_req_irqs(struct platform_device *pdev, struct axi_dma_chip *chip)
        return 0;
   }
 
+/* Forward declaration (no size required) */
+static const struct of_device_id dw_dma_of_id_table[];
+
   static int dw_probe(struct platform_device *pdev)
   {
        struct axi_dma_chip *chip;
        struct dw_axi_dma *dw;
        struct dw_axi_dma_hcfg *hdata;
        struct reset_control *resets;
+     struct device_node *parent;
+     const struct of_device_id *match;
        unsigned int flags;
+     unsigned int addressable_bits = 64;
+     unsigned int len_bytes;
+     unsigned int num_cells;
+     const __be32 *prop;
+     u64 bus_width;
+     u32 *cells;
        u32 i;
        int ret;
 

@@ -1483,9 +1496,61 @@ static int dw_probe(struct platform_device *pdev)
        if (!hdata)
                return -ENOMEM;
 
+     match = of_match_node(dw_dma_of_id_table, pdev->dev.of_node);
+     if (!match) {
+             dev_err(&pdev->dev, "Unsupported AXI DMA device\n");
+             return -ENODEV;
+     }
+
+     parent = of_get_parent(pdev->dev.of_node);
+     if (parent) {
+             prop = of_get_property(parent, "dma-ranges", &len_bytes);
+             if (prop) {
+                     num_cells = len_bytes / sizeof(__be32);
+                     cells = kcalloc(num_cells, sizeof(*cells), GFP_KERNEL);
+                     if (!cells)
+                             return -ENOMEM;
+
+                     ret = of_property_read_u32(parent, "#address-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #address-cells property\n");
+                             return ret;
+                     }
+
+                     ret = of_property_read_u32(parent, "#size-cells", &i);
+                     if (ret) {
+                             dev_err(&pdev->dev, "missing #size-cells property\n");

Quoted 8 lines

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c static int dw_probe(struct platform_device *pdev) · line 1527

Quoted 5 lines

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +5 -0

+                             return ret;
+                     }
+
+                     if (!of_property_read_u32_array(parent, "dma-ranges",
+                                                     cells, num_cells)) {

We have common code to parse dma-ranges. Use it and don't implement your own.

Quoted 6 lines

Actually, the driver and DT core should take care of all this for you and there's nothing to do in the driver. A driver only needs to set the mask for the IP itself and only when >32 bits. The core takes care of any additional restrictions in the bus.

Rob

The current implementation explicitly set the mask to 64.

Quoted 3 lines

- ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));

Will the core re-set the mask based on the dma-ranges on DT?

I don't think it changes the mask, but there's also bus ranges which get factored in. See struct device.bus_dma_limit and dma_range_map.

Rob