Add Meta Rainiera6 BMC support
Subsystems (2)
cover Add Meta Rainiera6 BMC support
Add initial device tree support for the Meta Rainiera6 platform.
This series adds:
- Meta Rainiera6 compatible entry
- Rainiera6 BMC DTS
The DTS has been validated with:
- make dtbs
- make dt_binding_check
- make CHECK_DTBS=y
Neil Cheng (2):
dt-bindings: arm: aspeed: Add Meta Rainiera6 board
ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC
.../bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-rainiera6.dts | 1012 +++++++++++++++++ 3 files changed, 1014 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts
Signature · 1 line
2.25.1
PATCH 1/2 dt-bindings: arm: aspeed: Add Meta Rainiera6 board
Document the new compatibles used on Meta Rainiera6.
Signed-off-by Neil Cheng <[email protected]>
--- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +1 -0
@@ -95,6 +95,7 @@ properties: - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc + - facebook,rainiera6-bmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc - facebook,yosemite5-bmc
Signature · 1 line
2.25.1
Re: [PATCH 1/2] dt-bindings: arm: aspeed: Add Meta Rainiera6 board
Acked-by Conor Dooley <[email protected]>
pw-bot: not-applicable
PATCH 2/2 ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC
In reply to Neil ChengAdd device tree for the Meta (Facebook) Rainiera6 compute node, based on AST2600 BMC.
Signed-off-by Neil Cheng <[email protected]>
--- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-rainiera6.dts | 1012 +++++++++++++++++ 2 files changed, 1013 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts
arch/arm/boot/dts/aspeed/Makefile +1 -0
@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-harma.dtb \ aspeed-bmc-facebook-minerva.dtb \ aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-rainiera6.dtb \ aspeed-bmc-facebook-santabarbara.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts new file +1012 -0
1,012 lines not on this page · raw message
Signature · 1 line
2.25.1
RE: [PATCH 2/2] ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC
Hi Neil Cheng,
Quoted 130 lines
-----Original Message-----
From: Neil Cheng <[email protected]>
Sent: 18 May 2026 09:13
Subject: [PATCH 2/2] ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC[You don't often get email from [email protected]. Learn why this is important at
https://aka.ms/LearnAboutSenderIdentification ]Add device tree for the Meta (Facebook) Rainiera6 compute node, based on AST2600 BMC.
Signed-off-by Neil Cheng <[email protected]>--- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-rainiera6.dts | 1012 +++++++++++++++++ 2 files changed, 1013 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dtsarch/arm/boot/dts/aspeed/Makefile +1
-0@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-harma.dtb \ aspeed-bmc-facebook-minerva.dtb \ aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-rainiera6.dtb \ aspeed-bmc-facebook-santabarbara.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-
rainiera6.dtsb/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dtsnew file mode 100644
index 000000000000..2c8c983db677arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts new file +94
-0@@ -0,0 +1,1012 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2026 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> #include +<dt-bindings/i2c/i2c.h> + +/ { + model = "Facebook Rainier BMC"; + compatible = "facebook,rainiera6-bmc", "aspeed,ast2600"; + + aliases { + i2c16 = &i2c5mux0ch0; + i2c17 = &i2c5mux0ch1; + i2c18 = &i2c5mux1ch0; + i2c19 = &i2c5mux1ch1; + i2c20 = &i2c6mux0ch0; + i2c21 = &i2c6mux0ch1; + i2c22 = &i2c6mux0ch2; + i2c23 = &i2c6mux0ch3; + i2c24 = &i2c8mux0ch0; + i2c25 = &i2c8mux0ch1; + i2c26 = &i2c8mux0ch2; + i2c27 = &i2c8mux0ch3; + i2c28 = &i2c26mux0ch0; + i2c29 = &i2c26mux0ch1; + i2c30 = &i2c26mux0ch2; + i2c31 = &i2c26mux0ch3; + serial0 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "fp_id_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "power_fault_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + p1v8_adc_vref: regulator-p1v8-aux { + compatible = "regulator-fixed"; + regulator-name = "p1v8_adc_vref"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + status = "okay"; + + tpm@0 {
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts line 104
Quoted 10 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts new file +10
-0+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&adc0 { + vref-supply = <&p1v8_adc_vref>; + status = "okay";
Maybe status after pinctrl entries to consistent with wdt1 and spi2 below??
Cheers,
Biju
Quoted 910 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts new file +907
-1+ pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default +&pinctrl_adc7_default>; }; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc10_default>; }; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; #include +"openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BATTERY_DETECT","","BMC_I2C1_FPGA_ALERT_L","BMC_READY_R", + "IOEXP_INT_3V3_L_R1","FM_ID_LED","","", + /*C0-C7*/ "BMC_GPIOC0","","","","PMBUS_REQ_N","PSU_FW_UPDATE_REQ_N","", + "BMC_I2C_SSIF_ALERT_L", + /*D0-D7*/ "","","","","BMC_GPIOD4","","","", + /*E0-E7*/ "BMC_GPIOE0","BMC_GPIOE1","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "FM_BMC_MUX1_SEL_R","","","","","","FM_DEBUG_PORT_PRSNT_R1_N", + "FM_BMC_DBP_PRESENT_R_N", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","FLASH_WP_STATUS_R1","BMC_JTAG_MUX_SEL","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "PCIE_EP_RST_EN","BMC_FRU_WP","SCM_HPM_STBY_RST_N", + "SCM_HPM_STBY_R_EN","STBY_POWER_PG_3V3_R","TH500_SHDN_OK_L","","", + /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1","LED_POSTCODE_2", + "LED_POSTCODE_3","LED_POSTCODE_4","LED_POSTCODE_5", + "LED_POSTCODE_6","LED_POSTCODE_7", + /*O0-O7*/ "RUN_POWER_PG","PWR_BRAKE_L","CHASSIS_AC_LOSS_L", + "BSM_PRSNT_R_N","PSU_SMB_ALERT_L","FM_TPM_PRSNT_0_N", + "PSU_FW_UPDATING_N","DEBUG_CARD_BYPASS", + /*P0-P7*/ "PWR_BTN_BMC_R1_N","IPEX_CABLE_PRSNT_L","ID_RST_BTN_BMC_R_N", + "RST_BMC_RSTBTN_OUT_R_N","BMC_PWR_LED","RUN_POWER_EN", + "SHDN_FORCE_L","BMC_HEARTBEAT_N", + /*Q0-Q7*/ "IRQ_PCH_TPM_SPI_LV3_N","USB_OC0_REAR_R_N","UART_MUX_SEL", + "I2C_MUX_RESET_L","RSVD_NV_PLT_DETECT","SPI_TPM_INT_L", + "CPU_JTAG_MUX_SELECT","THERM_BB_OVERT_L", + /*R0-R7*/ "THERM_BB_WARN_L","SPI_BMC_FPGA_INT_L","CPU_BOOT_DONE", + "PMBUS_GNT_L","CHASSIS_PWR_BRK_L","PCIE_WAKE_L","PDB_THERM_OVERT_L", + "SHDN_REQ_L", + /*S0-S7*/ "","","SYS_BMC_PWRBTN_R_N","FM_TPM_PRSNT_1_N", + "FM_BMC_DEBUG_SW_N","UID_LED_N","SYS_FAULT_LED_N", + "RUN_POWER_FAULT_L", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "L2_RST_REQ_OUT_L","L0L1_RST_REQ_OUT_L","BMC_ID_BEEP_SEL_R1", + "BMC_I2C0_FPGA_ALERT_L","SMB_BMC_TMP_ALERT","PWR_LED_N", + "SYS_RST_OUT_L","IRQ_TPM_SPI_N", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","FM_DBP_CPU_PREQ_GF_N_R1","","","","","","", + /*Y0-Y7*/ "","RST_BMC_SELF_HW_R1","FM_FLASH_LATCH_N_R1","", + "BMC_GPIOY4_R","BMC_GPIOY5_R","","", + /*Z0-Z7*/ "","","","","","","BMC_GPIOZ6_R","BMC_GPIOZ7_R"; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","FM_BOARD_BMC_REV_ID0","FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2","", + /*18C0-18C7*/ "","","SPI_BMC_BIOS_ROM_IRQ0_R_N","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "FM_BMC_PROT_LS_EN","AC_PWR_BMC_BTN_R_N","",""; +}; + +/* Rainiera6 SoC SSIF */ +&i2c1 { + status = "okay"; + + ssif_bmc: ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + status = "okay"; + }; +}; + +/* MCIO 2A I2C */ +&i2c2 { + status = "okay"; +}; + +&i2c4 { + multi-master; + mctp-controller; + clock-frequency = <400000>; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + /* OCP NIC TEMP */ + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + + /* OCP NIC FRU EEPROM */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c5 { + status = "okay"; + + gpio-expander@22 { + compatible = "nxp,pca9535"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "JTAG_BMC_IOEXP_MUX_OE", "JTAG_BMC_MCIO_MUX_S1", + "JTAG_BMC_MCIO_MUX_S0", "JTAG_IOEXP_BMC_MUX_SEL", + "FM_USB_MUX_1_OE_N", "FM_USB_MUX_2_OE_N", + "PROGRAMN_CPLD", "", + "", "", + "", "", + "", "", + "", ""; + }; + + /* I2C MUX for MCIO 1A */ + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + /* I2C MUX for MCIO 0A */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + /* I2C MUX for PWRPIC #13 ~ #16 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #13 */ + i2c6mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #14 */ + i2c6mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #16 */ + i2c6mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #15 */ + i2c6mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c7 { + multi-master; + status = "okay"; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c8 { + status = "okay"; + + power-monitor@14 { + compatible = "infineon,xdp710"; + reg = <0x14>; + }; + + adc@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + /* PDB IOEXP0 */ + pdb_io_expander0: gpio-expander@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + interrupt-parent = <&sgpiom0>; + interrupts = <92 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "FM_P52V_AUX_FLT_N","FM_P12V_AUX_ALERT_N", + "FM_SLOT1_HSC_FAULT","FM_SLOT2_HSC_FAULT", + "FM_SLOT3_HSC_FAULT","FM_SLOT4_HSC_FAULT", + "FM_SLOT5_HSC_FAULT","FM_SLOT6_HSC_FAULT", + "PRSNT_FAN0","PRSNT_FAN1", + "PRSNT_FAN2","PRSNT_FAN3", + "","", + "","INT_SLOT"; + }; + + /* PDB IOEXP1 */ + gpio-expander@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + interrupt-parent = <&pdb_io_expander0>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SLOT1_CM_UPDATE","SLOT2_CM_UPDATE", + "SLOT3_CM_UPDATE","SLOT4_CM_UPDATE", + "SLOT5_CM_UPDATE","SLOT6_CM_UPDATE", + "","", + "","", + "","", + "","", + "",""; + }; + + power-sensor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + /* PADDLE BD IOEXP */ + gpio-expander@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "HSC_OC_GPIO0", "HSC_OC_GPIO1", + "HSC_OC_GPIO2", "HSC_OC_GPIO3"; + }; + + power-sensor@42 { + compatible = "ti,ina238"; + reg = <0x42>; + shunt-resistor = <1000>; + }; + + power-monitor@43 { + compatible = "lltc,ltc4287"; + reg = <0x43>; + shunt-resistor-micro-ohms = <100>; + }; + + power-sensor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-sensor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + power-monitor@46 { + compatible = "mps,mp5998"; + reg = <0x46>; + }; + + power-monitor@47 { + compatible = "ti,tps25990"; + reg = <0x47>; + ti,rimon-micro-ohms = <430000000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + /* PDB FRU */ + eeprom@56 { + compatible = "atmel,24c128"; + reg = <0x56>; + }; + + /* Paddle BD FRU */ + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + }; + + power-monitor@58 { + compatible = "renesas,isl28022"; + reg = <0x58>; + shunt-resistor-micro-ohms = <10000>; + }; + + power-monitor@59 { + compatible = "renesas,isl28022"; + reg = <0x59>; + shunt-resistor-micro-ohms = <10000>; + }; + + power-monitor@5a { + compatible = "renesas,isl28022"; + reg = <0x5a>; + shunt-resistor-micro-ohms = <10000>; + }; + + power-monitor@5b { + compatible = "renesas,isl28022"; + reg = <0x5b>; + shunt-resistor-micro-ohms = <10000>; + }; + + psu@5c { + compatible = "renesas,raa228006"; + reg = <0x5c>; + }; + + fan-controller@5e{ + compatible = "maxim,max31790"; + reg = <0x5e>; + }; + + /* I2C MUX for PWRPIC #1, #2, #11, #12 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #1 */ + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #2 */ + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #12 (Connector to CXL BD) */ + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + i2c26mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c26mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c26mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + /* CXL FRU */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + i2c26mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* PWRPIC #11 */ + i2c8mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c9 { + status = "okay"; + + temperature-sensor@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + + /* SCM FRU */ + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + /* BSM FRU */ + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +/* MCIO 0A I2C */ +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + /* I2C11_IOEXP_3 */ + gpio-expander@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "IRQ_INA230_FAN0_ALERT_N_CPLD", "IRQ_INA230_FAN1_ALERT_N_CPLD", + "IRQ_INA230_FAN2_ALERT_N_CPLD", "IRQ_INA230_FAN3_ALERT_N_CPLD", + "IRQ_INA230_P12V_DIMM_0_ALERT_N", "IRQ_INA230_P12V_DIMM_1_ALERT_N", + "IRQ_P3V3_E1S_0_FLT_N", "P12V_E1S_0_FAULT_R_N", + "IRQ_P3V3_E1S_1_FLT_N", "P12V_E1S_1_FAULT_R_N", + "IRQ_P3V3_NIC_FLT_N", "P12V_NIC_FAULT_R_N", + "SMB_SENSOR_ALERT_N", "FW_CPLD_RST_RTC_RST_R1", + "RTC_CLR", "RTC_U11_ALRT_N"; + }; + + /* I2C11_IOEXP_2 */ + gpio-expander@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "FAN_0_PRESENT_CPLD", "FAN_1_PRESENT_CPLD", + "FAN_2_PRESENT_CPLD", "FAN_3_PRESENT_CPLD", + "FAN_FAIL_L_CPLD", "FULL_SPEED_N_R_CPLD", + "P12V_FAN0_PWRGD_CPLD", "P12V_FAN1_PWRGD_CPLD", + "P12V_FAN2_PWRGD_CPLD", "P12V_FAN3_PWRGD_CPLD", + "FM_P12V_FAN0_FLTB_N_CPLD", "FM_P12V_FAN1_FLTB_N_CPLD", + "FM_P12V_FAN2_FLTB_N_CPLD", "FM_P12V_FAN3_FLTB_N_CPLD", + "P12V_FAN_EN_R_CPLD", ""; + }; + + /* I2C11_IOEXP_1 */ + gpio-expander@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "PWRGD_P12V_SCM", "PWRGD_P5V_STBY", + "PWRGD_P3V3_STBY", "PWRGD_P1V8_STBY", + "PWRGD_P1V2_STBY", "PWRGD_P1V1_STBY", + "PWRGD_P1V0_STBY", "", + "", "", + "", "", + "", "", + "", ""; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + + power-sensor@42 { + compatible = "ti,ina230"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + + power-sensor@43 { + compatible = "ti,ina230"; + reg = <0x43>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + adc@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + adc@4a { + compatible = "ti,ads7830"; + reg = <0x4a>; + }; + + adc@4b { + compatible = "ti,ads7830"; + reg = <0x4b>; + }; + rtc@6f { + compatible = "nuvoton,nct3018y"; + reg = <0x6f>; + status = "okay"; + }; +}; + +/* MCIO 4A I2C */ +&i2c12 { + multi-master; + mctp-controller; + clock-frequency = <400000>; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; +}; + +&i2c13 { + status = "okay"; + + fan-controller@20 { + compatible = "maxim,max31790"; + reg = <0x20>; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + temperature-sensor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "national,lm75b"; + reg = <0x49>; + }; + + /* MB FRU */ + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; +}; + +/* PROT reserve */ +&i2c14 { + status = "okay"; +}; + +/* MCIO 3A I2C */ +&i2c15 { + status = "okay"; +}; + +&mac2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; + status = "okay"; +}; + +&pinctrl { + pinctrl_ncsi3_default: ncsi3_default { + function = "RMII3"; + groups = "NCSI3"; + }; +}; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*"input pin","output pin"*/ + "SOC_ERROR_N_CPLD","RST_SOC_SRST_N_CPLD", + "SOC_ELASTOPCLK_N","SOC_BMC_READY_CPLD", + "SOC_LINKSTOP_N","wIBB_BMC_SRST_OUT", + "SOC_POST_COMPLETE_CPLD","I3C_MUX_SEL_DIMM_C0_024", + "SOC_RESETREQ","I3C_MUX_SEL_DIMM_C0_135", + "SOC_SYS_PWRDN_CPLD","I3C_MUX_SEL_DIMM_C1_024", + "SOC_PORQ","I3C_MUX_SEL_DIMM_C1_135", + "SOC_HOT_N_CPLD","BOOT_PWRDIS_CPLD", + // IOB0-IOB7 bit8-15 + "PWRGD_V1P8_CPU","HDD0_PERST_N_CPLD", + "PWRGD_V1P26_CPLD","HDD1_PERST_N_CPLD", + "PWRGD_V1P2","MCIO_1A_PWRDIS_R", + "","", + "FM_CONFIG_ID","P3V_BAT_SCALED_EN", + "wALL_POWER_OK","PERST_CEM0_N_CPLD", + "wANDGATE_ALL_POWER_GD","PERST_CEM1_N_CPLD", + "wAC_CYCLE_12V","PERST_PLD_TUSB7340_N", + // IOC0-IOC7 bit16-23 + "wAC_CYCLE_54V","FM_USB_MUX_SEL_CPLD", + "FM_PLD_CLKS_DEV_EN","SMB_BOOT_RST_N_CPLD", + "PWRGD_P1V2_STBY","SMB_MCIO_0A_RST_R_N", + "wIBB_BMC_SRST","RST_SMB_NIC_R_N", + "PWRGD_P12V_E1S_0","FM_PPS_NIC_IN_BUF_OE_N_R", + "PWRGD_P12V_E1S_1","FM_BUF_PPS_NIC_IN_EN_CPLD", + "","FM_NIC_PPS_IN_OE_CPLD", + "PWRGD_P12V_NIC","FM_PPS_NIC_IN_S0_CPLD", + // IOD0-IOD7 bit24-31 + "wALL_POWER_OK_1","FM_NIC_PPS_IN_S1", + "wALL_POWER_OK_2","FM_PPS_NIC_OUT_CPU_OE_N", + "PWRGD_EAST_DIMM_CPLD","", + "PWRGD_WEST_DIMM_CPLD","FM_BUF_PPS_NIC_OUT_EN_CPLD", + "PWRGD_NIC_CPLD","", + "","PMBUS_MUX_SEL_C0", + "PHOENIX_PWRBTN_N_CPLD","PMBUS_MUX_SEL_C1", + "IRQ_INA230_E1S_0_ALERT_N","", + // IOE0-IOE7 bit32-39 + "IRQ_INA230_E1S_1_ALERT_N","PWR_ON_RST_TUSB7340_CPLD", + "","RST_PCIE_BOOT_PERST_N_CPLD", + "FM_NIC_WAKE_N_CPLD","RST_PCIE_CPLD_NIC_N_CPLD", + "FM_TPM_CONN_PRSNT_N","RST_PCIE_MCIO_0A_PERST_N_CPLD", + "HDD0_PRSNT_N_CPLD","RST_PCIE_MCIO_0B_PERST_N_CPLD", + "IRQ_INA230_P12V_NIC_ALERT_N","RST_PCIE_MCIO_1A_PERST_N_CPLD", + "IRQ_INA230_P12V_SCM_ALERT_N","RST_PCIE_MCIO_1A_SA_PERST_N_CPL", + "IRQ_PMBUS_ALERT_PWR11_R_N","RST_PCIE_MCIO_1B_PERST_N_CPLD", + // IOF0-IOF7 bit40-47 + "CHASSIS_LEAK_2A_R_N","RST_PCIE_MCIO_2A_PERST_N_CPLD", + "CHASSIS_LEAK_3A_R_N","RST_PCIE_MCIO_2B_PERST_N_CPLD", + "CHASSIS_LEAK_4A_R_N","RST_PCIE_MCIO_3A_PERST_N_CPLD", + "OC_ALERT_PADDLE_R_N","RST_PCIE_MCIO_3B_PERST_N_CPLD", + "OC_ALERT_PWR2_R_N","RST_PCIE_MCIO_4A_PERST_N_CPLD", + "OC_ALERT_PWR11_R_N","RST_PCIE_MCIO_4B_PERST_N_CPLD", + "FM_IOE_ALT_N","RST_PERST1_N_CPLD", + "LEAK_DETECT_1_PWR14_R_N","RST_PERST2_N_CPLD", + // IOG0-IOG7 bit48-55 + "LEAK_DETECT_2_PWR14_R_N","RST_PERST3_N_CPLD", + "LEAK_DETECT_1_PWR15_R_N","RST_SMB_MUX_MCIO_0A_R_N", + "LEAK_DETECT_2_PWR15_R_N","RST_SMB_MUX_MCIO_1A_R_N", + "MCIO_0A_SMB_ALERT_N","RST_SOC_EXTWARMRESET_CPLD", + "MCIO_1A_SMB_ALERT_N","RST_SOC_PORESET_N_BMC", + "MCIO_2A_SMB_ALERT_N","RST_USB_HUB_R_N", + "MCIO_2B_SMB_ALERT_N","SMB_MM7_MUX_RESET_N", + "MCIO_3A_SMB_ALERT_N","SMB_MUX_RESET_N_CPLD", + // IOH0-IOH7 bit56-63 + "MCIO_3B_SMB_ALERT_N","SOC_I2C_0_ALERT_CPLD", + "MCIO_4A_SMB_ALERT_N","SOC_LINKSTOP_OUT_N", + "MCIO_4B_SMB_ALERT_N","SPI_TPM_RST_R_N", + "MCIO_1A_THERMTRIP_N","", + "MCIO_2A_THERMTRIP_N","", + "MCIO_3A_THERMTRIP_N","", + "MCIO_4A_THERMTRIP_N_CPLD","", + "UV_ALERT_PADDLE_R_N","wFM_USB_MUX_OE_N", + // IOI0-IOI7 bit64-71 + "UV_ALERT_PWR2_R_N","wFM_USB_MUX_SEL", + "UV_ALERT_PWR11_R_N","", + "SOC_PMBUS_0_ALERT_R_CPLD","FM_BIOS_DEBUG_MODE_N", + "HDD1_PRSNT_N_CPLD","", + "","", + "SOC_DRAM_0_HOT_N_CPLD","", + "SOC_DRAM_1_HOT_N_CPLD","RST_PLTRST_PLD_B_N", + "SOC_DRAM_2_HOT_N_CPLD","FM_TPM_MUX6_SEL", + // IOJ0-IOJ7 bit72-79 + "SOC_DRAM_3_HOT_N_CPLD","CPLD_MUX6_EN_N", + "IRQ_P3V3_NIC_FLT_MOS_N_CPLD","", + "VRHOT_V0P75_PCIE_VDDQ_N","", + "P12V_SCM_FAULT_R_N","", + "SOC_I2C_1_ALERT_CPLD","", + "","", + "SOC_PLATHOT_N_CPLD","", + "SOC_THRMTRIP_N_CPLD","", + // IOK0-IOK7 bit80-87 + "VRHOT_VCPUC1_VCPUMC1_N","", + "VRHOT_VSYSC0_VSOCC0_N","", + "VRHOT_VSYSC1_VSOCC1_N","", + "VRHOT_VCPUC0_VCPUMC0_N","", + "","", + "INT_IOEXP_N","", + "RSVD_IOEXP_0A_SB1_R","", + "RSVD_IOEXP_0A_SB2_R","", + // IOL0-IOL7 bit88-95 + "IRQ_PMBUS_PWR2_ALERT_R_N","", + "FM_BORD_REV_ID0","", + "FM_BORD_REV_ID1","", + "FM_BORD_REV_ID2","", + "FM_VR_TYPE_0","", + "FM_VR_TYPE_1","", + "","", + "MCIO_0B_SMB_ALERT_N","", + // IOM0-IOM7 bit96-103 + "MCIO_1B_SMB_ALERT_N","", + "PRSNT_BOOT_N","", + "PRSNT_MCIO_1A_N","", + "wPRSNT_NIC_N","", + "","", + "SOC_TEST_MODE0","", + "PWRGD_V0P75_PCIE","", + "PWRGD_VDDQ","", + // ION0-ION7 bit104-111 + "PWRGD_VCPUC0","", + "PWRGD_VCPUMC0","", + "PWRGD_VCPUMC1","", + "PWRGD_VCPUC1","", + "PWRGD_VSYSC0","", + "PWRGD_VSOCC0","", + "PWRGD_VSYSC1","", + "PWRGD_VSOCC1","", + // IOO0-IOO7 bit112-119 + "SOC_PMBUS_1_ALERT_R_CPLD","", + "SOC_GPIO_15","", + "C0_POSTCODE_0_CPLD","", + "C0_POSTCODE_1_CPLD","", + "C0_POSTCODE_2_CPLD","", + "C0_POSTCODE_3_CPLD","", + "C0_POSTCODE_4_CPLD","", + "C1_POSTCODE_0_CPLD","", + // IOP0-IOP7 bit 120-127 + "C1_POSTCODE_1_CPLD","", + "C1_POSTCODE_2_CPLD","", + "C1_POSTCODE_3_CPLD","", + "C1_POSTCODE_4_CPLD","", + "","", + "SOC_GPIO_17","", + "SOC_GPIO_18","", + "SOC_GPIO_37",""; +}; + +/* BIOS Flash */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + status = "okay"; + + flash@0 { + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <12000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + status = "okay"; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +/* SOL */ +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +/* BMC Console */ +&uart5 { + status = "okay"; +}; + +&wdt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + status = "okay"; +}; --2.25.1
v2 cover Add Meta Rainiera6 BMC support
In reply to Neil ChengAdd initial device tree support for the Meta Rainiera6 platform.
Changes in v2:
- reorder adc0/adc1 properties
- add Acked-by from Conor Dooley
This series adds:
- Meta Rainiera6 compatible entry
- Rainiera6 BMC DTS
The DTS has been validated with:
- make dtbs
- make dt_binding_check
- make CHECK_DTBS=y
Neil Cheng (2):
dt-bindings: arm: aspeed: Add Meta Rainiera6 board
ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC
.../bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-rainiera6.dts | 1012 +++++++++++++++++ 3 files changed, 1014 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts
Signature · 1 line
2.25.1
PATCH v2 1/2 dt-bindings: arm: aspeed: Add Meta Rainiera6 board
Document the new compatibles used on Meta Rainiera6.
Acked-by Conor Dooley <[email protected]>
Signed-off-by Neil Cheng <[email protected]>
--- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +1 -0
@@ -95,6 +95,7 @@ properties: - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc + - facebook,rainiera6-bmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc - facebook,yosemite5-bmc
Signature · 1 line
2.25.1
PATCH v2 2/2 ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC
In reply to Neil ChengAdd device tree for the Meta (Facebook) Rainiera6 compute node, based on AST2600 BMC.
Signed-off-by Neil Cheng <[email protected]>
--- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-rainiera6.dts | 1012 +++++++++++++++++ 2 files changed, 1013 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts
arch/arm/boot/dts/aspeed/Makefile +1 -0
@@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-harma.dtb \ aspeed-bmc-facebook-minerva.dtb \ aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-rainiera6.dtb \ aspeed-bmc-facebook-santabarbara.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts new file +1012 -0
1,012 lines not on this page · raw message
Signature · 1 line
2.25.1
Andrew Jeffery
maintainerHi Neil,
Quoted 10 lines · Neil Cheng
Add initial device tree support for the Meta Rainiera6 platform.
Changes in v2:
- reorder adc0/adc1 properties
- add Acked-by from Conor DooleyThis series adds:
- Meta Rainiera6 compatible entry
- Rainiera6 BMC DTS
In the future can you please avoid threading v2 (and later) under your prior submissions?
Thanks,
Andrew
Quoted 20 lines · Neil Cheng
Add initial device tree support for the Meta Rainiera6 platform.
Changes in v2:
- reorder adc0/adc1 properties
- add Acked-by from Conor DooleyThis series adds:
- Meta Rainiera6 compatible entry
- Rainiera6 BMC DTSThe DTS has been validated with:
- make dtbs
- makedt_binding_check
- make CHECK_DTBS=yNeil Cheng (2):
dt-bindings: arm: aspeed: Add Meta Rainiera6 board
ARM: dts: aspeed: rainiera6: Add Meta Rainiera6 BMC
Quoted 5 lines
.../bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-rainiera6.dts | 1012 +++++++++++++++++
3 files changed, 1014 insertions(+)create mode 100644
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-rainiera6.dts
Applied to aspeed/arm/dt in the BMC tree.
Thanks,
Andrew