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arm64: dts: am62p5-var-som-symphony: align DTS with hardware revision

PATCH Superseded Stefano Radaelli 2 participants 8 messages Jun 28

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Device tree bindings Arm/Texas Instruments K3 architecture

v1 of 2 Superseded Latest is v2 →

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Stefano Radaelli

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#0 lore raw

cover arm64: dts: am62p5-var-som-symphony: align DTS with hardware revision

This series updates the device tree description for the Variscite VAR-SOM-AM62P and Symphony carrier board to better reflect the current board configuration.

It aligns the Ethernet PHY description, updates the audio codec configuration, and adds the touchscreen and TPM devices together with their required board-level resources.

Stefano Radaelli (4):
arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration
arm64: dts: ti: var-som-am62p: update audio codec configuration
arm64: dts: am62p5-var-som-symphony: add touchscreen support
arm64: dts: am62p5-var-som-symphony: add TPM support

 .../dts/ti/k3-am62p5-var-som-symphony.dts     | 43 +++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 38 ++++++++++++++--
 2 files changed, 77 insertions(+), 4 deletions(-)

base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43

Signature · 1 line
2.47.3
author
#1 lore raw

PATCH 1/4 arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

Fix the Ethernet device tree description on the VAR-SOM-AM62P.

Enable the CPSW Ethernet controller and correct the Ethernet PHY description by modelling the PHY power supply and adding the required board-specific PHY properties.

Signed-off-by Stefano Radaelli <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +14 -3
index fc5a3942cde0..be19cbaffc4b 100644
@@ -113,6 +113,15 @@ reg_3v3_phy: regulator-3v3-phy {
 		regulator-always-on;
 	};
 
+	reg_eth_phy_vdd: regulator-eth-vdd {
+		compatible = "regulator-fixed";
+		regulator-name = "reg_eth_phy_vdd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&main_gpio0 46 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	sound {
 		compatible = "simple-audio-card";
 		simple-audio-card,bitclock-master = <&codec_dai>;

@@ -149,6 +158,7 @@ &audio_refclk1 {
 &cpsw3g {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_rgmii1>;
+	status = "okay";
 };
 
 &cpsw3g_mdio {

@@ -159,9 +169,10 @@ &cpsw3g_mdio {
 	cpsw3g_phy0: ethernet-phy@4 {
 		compatible = "ethernet-phy-id0283.bc30";
 		reg = <4>;
-		reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <10000>;
-		reset-deassert-us = <100000>;
+		bootph-all;
+		enet-phy-lane-no-swap;
+		vdd-supply = <&reg_eth_phy_vdd>;
+		ti,min-output-impedance;
 	};
 };
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AI review
#2 lore raw

Re: [PATCH v1 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] Replacing PHY `reset-gpios` with an unhandled `vdd-supply` regulator without `regulator-always-on`…

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Replacing PHY reset-gpios with an unhandled vdd-supply regulator without regulator-always-on will cause the kernel to erroneously reset the PHY, breaking Ethernet connectivity.
- [Medium] TI-specific PHY properties are erroneously applied to an Analog Devices PHY.
--

commit 3f60b20a54eb8dc897529e8f7d0ac14da1c7808f
Author: Stefano Radaelli <[email protected]>

arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

Enable the CPSW Ethernet controller and correct the Ethernet PHY description by modelling the PHY power supply and adding the required board-specific PHY properties.

Quoted 7 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +0 -0
index fc5a3942cde00..be19cbaffc4b0 100644
@@ -113,6 +113,15 @@ reg_3v3_phy: regulator-3v3-phy {
 		regulator-always-on;
 	};

arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi reg_3v3_phy: regulator-3v3-phy { · line 124

Quoted 10 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +9 -0
 
+	reg_eth_phy_vdd: regulator-eth-vdd {
+		compatible = "regulator-fixed";
+		regulator-name = "reg_eth_phy_vdd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&main_gpio0 46 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+

[Severity: High]
Does this code cause the PHY to be erroneously reset during late init, breaking Ethernet connectivity?

Since the kernel PHY drivers do not handle the vdd-supply property, this regulator will have no consumers. Without regulator-always-on, it will be disabled by regulator_init_complete() during late init.

Disabling this regulator drives the active-high GPIO (main_gpio0 46) low, which will assert the PHY's physical active-low reset pin.

Additionally, the required 100ms hardware initialization delay is lost since this new regulator lacks a corresponding startup-delay-us property.

[ ... ]

arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi &cpsw3g_mdio { · line 177

Quoted 13 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +4 -3
@@ -159,9 +169,10 @@ &cpsw3g_mdio {
 	cpsw3g_phy0: ethernet-phy@4 {
 		compatible = "ethernet-phy-id0283.bc30";
 		reg = <4>;
-		reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <10000>;
-		reset-deassert-us = <100000>;
+		bootph-all;
+		enet-phy-lane-no-swap;
+		vdd-supply = <&reg_eth_phy_vdd>;
+		ti,min-output-impedance;
 	};
 };

[Severity: Medium]
Are these TI-specific properties (ti,min-output-impedance and enet-phy-lane-no-swap) correct for an Analog Devices ADIN1300 PHY (ethernet-phy-id0283.bc30)?

If the hardware is actually an ADIN1300, these TI properties are ignored by the adin.c driver. If it is a TI PHY, the kernel will bind the wrong driver due to the incorrect compatible string.

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
author
#3 lore raw

PATCH 2/4 arm64: dts: ti: var-som-am62p: update audio codec configuration

In reply to Stefano Radaelli

Update the WM8904 audio codec configuration on the VAR-SOM-AM62P.

Set the audio reference clock rate to 12 MHz and add the codec DRC, GPIO and DMIC configuration required by the board.

Signed-off-by Stefano Radaelli <[email protected]>
---
 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 21 ++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +20 -1
index be19cbaffc4b..9440891339b3 100644
@@ -152,7 +152,7 @@ simple-audio-card,cpu {
 };
 
 &audio_refclk1 {
-	assigned-clock-rates = <100000000>;
+	assigned-clock-rates = <12000000>;
 };
 
 &cpsw3g {

@@ -204,6 +204,25 @@ wm8904: audio-codec@1a {
 		DBVDD-supply = <&reg_3v3>;
 		DCVDD-supply = <&reg_1v8>;
 		MICVDD-supply = <&reg_1v8>;
+		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+				    "soft", "music";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
+		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
+		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+		/* DMIC is connected to IN1L */
+		wlf,in1l-as-dmicdat1;
 	};
 };
Signature · 1 line
2.47.3
AI review
#4 lore raw

Re: [PATCH v1 2/4] arm64: dts: ti: var-som-am62p: update audio codec configuration

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Incomplete device tree audio routing configuration for the new DMIC on IN1L. --

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete device tree audio routing configuration for the new DMIC on IN1L. --

commit 7dd222d83843c4dcd6d8e965ee097f2c019186e6
Author: Stefano Radaelli <[email protected]>

arm64: dts: ti: var-som-am62p: update audio codec configuration

Update the WM8904 audio codec configuration on the VAR-SOM-AM62P. Set the audio reference clock rate to 12 MHz and add the codec DRC, GPIO and DMIC configuration required by the board.

Quoted 4 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +0 -0
index be19cbaffc4b0..9440891339b3a 100644

[ ... ]

Quoted 13 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +9 -0
@@ -204,6 +204,25 @@ wm8904: audio-codec@1a {
 		DBVDD-supply = <&reg_3v3>;
 		DCVDD-supply = <&reg_1v8>;
 		MICVDD-supply = <&reg_1v8>;
+		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+				    "soft", "music";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
+		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
+		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1

arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi wm8904: audio-codec@1a { · line 225

Quoted 10 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +10 -0
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+		/* DMIC is connected to IN1L */
+		wlf,in1l-as-dmicdat1;

[Severity: Medium]
Does this new DMIC configuration conflict with the existing simple-audio-card routing?

Earlier in the file, the ALSA DAPM audio routing maps IN1L to an external analog microphone jack:

	sound {
		...
		simple-audio-card,routing =
			...
			"IN1L", "Microphone Jack",
			"IN1R", "Microphone Jack";

Since IN1L is now configured as a digital microphone (DMIC), should the routing be updated so ALSA DAPM doesn't incorrectly couple the DMIC's power sequencing and userspace representation with a physical analog jack widget?

Quoted 2 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +0 -0
 	};
 };
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
author
#5 lore raw

PATCH 3/4 arm64: dts: am62p5-var-som-symphony: add touchscreen support

In reply to Stefano Radaelli

Add support for the capacitive touchscreen on the Symphony carrier board.

Describe the FT5x06 touchscreen controller, configure its interrupt and wakeup pins, and mark it as a wakeup source.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/ti/k3-am62p5-var-som-symphony.dts     | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +21 -0
index 5ba4ed56755b..5c41647ff43f 100644
@@ -293,6 +293,21 @@ &main_i2c1 {
 	clock-frequency = <400000>;
 	status = "okay";
 
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch_pins>;
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};
+
 	rtc@68 {
 		compatible = "dallas,ds1337";
 		reg = <0x68>;

@@ -307,6 +322,12 @@ &main_mcan0 {
 };
 
 &main_pmx0 {
+	pinctrl_captouch_pins: main-captouch-default-pins {
+		pinctrl-single,pins = <
+			AM62PX_IOPAD(0x01b8, PIN_INPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */
+		>;
+	};
+
 	pinctrl_extcon: main-extcon-pins {
 		pinctrl-single,pins = <
 			AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */
Signature · 1 line
2.47.3
AI review
#6 lore raw

Re: [PATCH v1 3/4] arm64: dts: am62p5-var-som-symphony: add touchscreen support

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The commit message claims to configure both the interrupt and wakeup pins, but the device tree…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message claims to configure both the interrupt and wakeup pins, but the device tree node and pinctrl only configure the interrupt pin, lacking a wakeup pin configuration. --

commit 6d6b56a3161a61ca2f1a68dce1765826d0594c86
Author: Stefano Radaelli <[email protected]>

arm64: dts: am62p5-var-som-symphony: add touchscreen support

This commit adds support for the capacitive touchscreen on the Symphony carrier board. It describes the FT5x06 touchscreen controller, configures its pins, and marks it as a wakeup source.

Quoted 4 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +0 -0
index 5ba4ed56755b4..5c41647ff43fa 100644

[ ... ]

Quoted 8 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +4 -0
@@ -293,6 +293,21 @@ &main_i2c1 {
 	clock-frequency = <400000>;
 	status = "okay";
 
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;

arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts &main_i2c1 { · line 309

Quoted 10 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +10 -0
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch_pins>;
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};

[Severity: Medium]
The commit message claims to configure both the interrupt and wakeup pins, but ft5x06_ts only configures the interrupt pin in its pinctrl.

Does this node also need a wake-gpios property to match the commit message and properly wake the device from hibernation?

[ ... ]

Quoted 10 lines
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +6 -0
@@ -307,6 +322,12 @@ &main_mcan0 {
 };
 
 &main_pmx0 {
+	pinctrl_captouch_pins: main-captouch-default-pins {
+		pinctrl-single,pins = <
+			AM62PX_IOPAD(0x01b8, PIN_INPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */
+		>;
+	};
+
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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
author
#7 lore raw

PATCH 4/4 arm64: dts: am62p5-var-som-symphony: add TPM support

In reply to Stefano Radaelli

Add the ST33KTPM2XI2C TPM device on the Symphony carrier board.

The TPM reset signal is driven through a PCAL6408 GPIO expander, so add the corresponding GPIO expander node. Configure the RGB_SEL board signal through a GPIO hog to keep the board in the expected configuration.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/ti/k3-am62p5-var-som-symphony.dts     | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +22 -0
index 5c41647ff43f..8fe8ec903d3d 100644
@@ -293,6 +293,28 @@ &main_i2c1 {
 	clock-frequency = <400000>;
 	status = "okay";
 
+	pcal6408: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		/* RGB_SEL */
+		lvds-brg-enable-hog {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "lvds_brg_en";
+		};
+	};
+
+	st33ktpm2xi2c: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		label = "tpm";
+		reg = <0x2e>;
+		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
+	};
+
 	/* Capacitive touch controller */
 	ft5x06_ts: touchscreen@38 {
 		compatible = "edt,edt-ft5206";
Signature · 1 line
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