Introduce MMIO-based CMT access for Enhanced RDT

Make topo_lookup_cpuid() accessible outside of topology.c and add its declaration to asm/apic.h. This is needed by Enhanced RDT (ERDT) to resolve x2APIC IDs from ACPI tables to logical CPU numbers.

No functional change expected.

Tested-by Hongyu Ning <[email protected]>

Signed-off-by Chen Yu <[email protected]>

Hi Chenyu,

Since this targets a different subsystem, could you please re-order the series to have this as first patch to make it obvious that it does not depend on anything in this series.

Quoted 3 lines

Make topo_lookup_cpuid() accessible outside of topology.c and add its declaration to asm/apic.h. This is needed by Enhanced RDT (ERDT) to resolve x2APIC IDs from ACPI tables to logical CPU numbers.

The first sentence of this changelog describes verbatim what can clearly be seen from the patch self without any context or problem description about why this change is needed.
tip changelogs always need to start with *why* the patch is needed before describing the change self. For more details about changelog requirements, please see "Changelog" in Documentation/process/maintainer-tip.rst

Quoted 5 lines

No functional change expected.

Tested-by Hongyu Ning <[email protected]>

Signed-off-by Chen Yu <[email protected]>

Also please follow "Ordering of commit tags" found in Documentation/process/maintainer-tip.rst for all patches in this series.

From: Anil S Keshavamurthy <[email protected]>

Parse the ERDT (Enhanced RDT) ACPI table so enhanced RDT features can consume firmware-provided domain information.

The ERDT may contain these sub-tables:

- Resource Management Domain Description Structure (RMDD)
- CPU Agent Collection Description Structure (CACD)
- Cache Monitoring Registers for CPU Agents Description Structure

    (CMRC)

There is one ERDT per platform. Each RMDD describes one resource

management domain (RMD), also known as an L3 domain, and carries MMIO base information for later monitoring support.

Add basic ERDT table parsing and retain the relevant sub-table information for later processing.

Handle RMDD specially. For each RMDD, parse the associated CACD, map its x2APIC IDs to logical CPUs, and save the resulting CPU mask. This mask associates each ERDT domain with the CPUs that belong to it and is used later when attaching ERDT data to resctrl monitoring domains.

Suggested-by Tony Luck <[email protected]>

Suggested-by Reinette Chatre <[email protected]>

Tested-by Hongyu Ning <[email protected]>

Signed-off-by Anil S Keshavamurthy <[email protected]>

Signed-off-by Chen Yu <[email protected]>

---

arch/x86/kernel/cpu/resctrl/erdt.c new file +3 -0

new file mode 100644
index 000000000000..6405df9be817
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Enhanced Resource Director Technology (ERDT)

arch/x86/kernel/cpu/resctrl/erdt.c new file +7 -0

+
+#define ERDT_VALID_VERSION		1
+#define RMDD_FLAG_CPU_L3_DOMAIN		BIT(0)
+
+/* Bitmask of valid sub-tables found in the first RMDD, used to ensure all RMDDs match. */
+static u32 valid_subtbl_mask;
+

arch/x86/kernel/cpu/resctrl/erdt.c new file +7 -0

+	return addr;
+}
+
+static void erdt_iounmap_domain(struct erdt_domain_info *domain)
+{
+	for (int i = 0; i < ERDT_MMIO_NUM_TYPES; i++) {
+		if (domain->base[i]) {

arch/x86/kernel/cpu/resctrl/erdt.c new file +51 -0

+	kfree(d);
+}
+
+/*
+ * Save CACD information for this RMDD:
+ * convert the X2APIC to CPU and save them in a mask.
+ */
+static __init int cacd_init(struct acpi_subtbl_hdr_16 *subtbl,
+			    struct erdt_domain_info *domain_info)
+{
+	struct acpi_erdt_cacd *cacd = (struct acpi_erdt_cacd *)subtbl;
+	int num_ids, cpu;
+
+	if (cacd->header.length < struct_size(cacd, X2APICIDS, 1)) {
+		pr_warn(FW_BUG "Invalid x2apicid CACD table\n");
+		return -EIO;
+	}
+
+	num_ids = (cacd->header.length - sizeof(*cacd)) / sizeof(cacd->X2APICIDS[0]);
+
+	for (int i = 0; i < num_ids; i++) {
+		cpu = topo_lookup_cpuid(cacd->X2APICIDS[i]);
+		if (cpu < 0) {
+			pr_warn(FW_BUG "Unknown x2apicid 0x%x\n", cacd->X2APICIDS[i]);
+			return -EIO;
+		}
+
+		cpumask_set_cpu(cpu, domain_info->cpu_mask);
+	}
+
+	return 0;
+}
+
+static inline struct acpi_subtbl_hdr_16 *rmdd_subtbl(struct acpi_erdt_rmdd *rmdd)
+{
+	return (void *)rmdd + sizeof(*rmdd);
+}
+
+static inline struct acpi_subtbl_hdr_16 *next_subtbl(struct acpi_subtbl_hdr_16 *subtbl)
+{
+	return (void *)subtbl + subtbl->length;
+}
+
+static inline bool subtbl_valid(void *end, struct acpi_subtbl_hdr_16 *subtbl)
+{
+	/* Ensure the header is within bounds before dereferencing it. */
+	if ((void *)subtbl + sizeof(*subtbl) > end)
+		return false;
+
+	/* A sub-table must be at least as large as its header. */
+	if (subtbl->length < sizeof(*subtbl))

arch/x86/kernel/cpu/resctrl/erdt.c new file +5 -0

+		return false;
+	}
+
+	rmdd = (struct acpi_erdt_rmdd *)rmdd_hdr;
+

arch/x86/kernel/cpu/resctrl/erdt.c new file +10 -0

+			if (cacd_init(subtbl, domain_info))
+				goto cleanup;
+
+			subtbl_mask |= BIT(ACPI_ERDT_TYPE_CACD);
+			break;
+		default:
+			break;
+		}
+	}
+

arch/x86/kernel/cpu/resctrl/erdt.c new file +6 -0

+
+	list_add(&domain_info->list, &domain_info_list);
+
+	return true;
+
+cleanup:

arch/x86/kernel/cpu/resctrl/erdt.c new file +6 -0

+		d = container_of(pos, struct erdt_domain_info, list);
+		list_del(pos);
+		cleanup_one_domain(d);
+	}
+	__erdt_enabled = false;
+	valid_subtbl_mask = 0;

arch/x86/kernel/cpu/resctrl/erdt.c new file +35 -0

+		return -EINVAL;
+	}
+
+	if (erdt->header.length < sizeof(*erdt)) {
+		pr_warn(FW_BUG "ERDT: Invalid table length %u bytes\n", erdt->header.length);
+		return -EINVAL;
+	}
+
+	subtbl = (void *)erdt + sizeof(struct acpi_table_erdt);
+	table_end = (void *)erdt + erdt->header.length;
+
+	while (subtbl_valid(table_end, subtbl)) {
+		if (subtbl->type == ACPI_ERDT_TYPE_RMDD &&
+		    !parse_rmdd_entry(subtbl))
+			goto cleanup;
+
+		subtbl = next_subtbl(subtbl);
+	}
+
+	if (list_empty(&domain_info_list))
+		goto cleanup;
+
+	__erdt_enabled = true;
+
+	return 0;
+
+cleanup:
+	erdt_exit();
+	return -EINVAL;
+}
+
+int __init erdt_init(void)
+{
+	return acpi_table_parse(ACPI_SIG_ERDT, enumerate_erdt_table);
+}

arch/x86/kernel/cpu/resctrl/internal.h +3 -0

index e3cfa0c10e92..299d7222f693 100644
@@ -21,6 +21,26 @@
 
 #define RMID_VAL_UNAVAIL		BIT_ULL(62)
 
+/*
+ * Index into erdt_domain_info::base[] for each MMIO region.
+ * @ERDT_MMIO_RMDD_CREG: RMDD control register base address

arch/x86/kernel/cpu/resctrl/internal.h +2 -0

+};
+
 /*
  * With the above fields in use 62 bits remain in MSR_IA32_QM_CTR for
  * data to be returned. The counter width is discovered from the hardware

Hi Chenyu,

Quoted 7 lines · Chen Yu

From: Anil S Keshavamurthy <[email protected]>

Parse the ERDT (Enhanced RDT) ACPI table so enhanced RDT features can consume firmware-provided domain information.

The ERDT may contain these sub-tables:

Quoted 4 lines

- Resource Management Domain Description Structure (RMDD)
- CPU Agent Collection Description Structure (CACD)
- Cache Monitoring Registers for CPU Agents Description Structure

     (CMRC)

How should "The ERDT may contain these sub-tables" be interpreted here? This sounds like some high level partial description of ERDT that is not specific to this patch.

Quoted 2 lines

There is one ERDT per platform. Each RMDD describes one resource

"one ERDT" -> "one ERDT table"?

Quoted 13 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +7 -0

new file mode 100644
index 000000000000..6405df9be817
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Enhanced Resource Director Technology (ERDT)
+ *
+ * Copyright (C) 2026 Intel Corporation
+ *
+ */

arch/x86/kernel/cpu/resctrl/erdt.c line 13

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +6 -0

+
+#define pr_fmt(fmt)     "resctrl: " fmt
+
+#include <linux/acpi.h>
+#include <linux/cleanup.h>
+#include <linux/cpu.h>

Which parts of cpu.h are used?

arch/x86/kernel/cpu/resctrl/erdt.c line 18

Quoted 5 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +5 -0

+#include <linux/err.h>
+#include <linux/overflow.h>
+#include <linux/resctrl.h>
+#include <linux/sizes.h>
+#include <linux/xarray.h>

xarray is no longer needed?

arch/x86/kernel/cpu/resctrl/erdt.c line 26

Quoted 8 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +8 -0

+
+#include <asm/apic.h>
+
+#include "internal.h"
+
+static LIST_HEAD(domain_info_list);
+
+static bool __erdt_enabled;

Is double underscore needed?

Could you please add a comment above the variable to describe what it means when "erdt is enabled"?

Quoted 11 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +11 -0

+
+#define ERDT_VALID_VERSION		1
+#define RMDD_FLAG_CPU_L3_DOMAIN		BIT(0)
+
+/* Bitmask of valid sub-tables found in the first RMDD, used to ensure all RMDDs match. */
+static u32 valid_subtbl_mask;
+
+int erdt_get_max_rmid(int cpu)
+{
+	struct erdt_domain_info *d;
+	struct list_head *pos;

arch/x86/kernel/cpu/resctrl/erdt.c line 43

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +6 -0

+
+	if (!__erdt_enabled)
+		return 0;
+
+	list_for_each(pos, &domain_info_list) {
+		d = container_of(pos, struct erdt_domain_info, list);

(list_for_each_entry()?)

arch/x86/kernel/cpu/resctrl/erdt.c line 50

Quoted 7 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +7 -0

+
+		if (cpumask_test_cpu(cpu, d->cpu_mask))
+			return d->max_rmid;
+	}
+
+	return -1;
+}

Using a CPU as parameter to determine the maximum RMID supported by ERDT is unexpected. Looking ahead at how this function is used I find only one usage:

	rdt_get_l3_mon_config() {
		...
		/*
		 * Currently assume all CPU domains share the same maximum RMID
		 * value from the RMDD table, use CPU0 domain's value.
		 */
		int erdt_max_rmid = erdt_get_max_rmid(0);

From this usage I do not see any reason why to do any CPU matching ... erdt_get_max_rmid()
could just return the max_rmid of any domain ... but that does not look right either since the comment states an assumption that is never enforced in the code.

Could this be made more robust by replacing the "per-erdt-domain max_rmid" with one global "ERDT max RMID" to which all RMDD's max RMID is compared to *ensure* they are all the same. If there is no such guarantee then I expect this will be the minimum among all RMDD? All seems to point to there only being one global value that is determined during ERDT enumeration and then this helper can just return that value directly?

arch/x86/kernel/cpu/resctrl/erdt.c line 57

Quoted 7 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +7 -0

+
+static void __iomem *erdt_ioremap(phys_addr_t base, u32 num_pages, const char *desc)
+{
+	void __iomem *addr;
+	size_t size;
+
+	if (check_mul_overflow((size_t)num_pages, (size_t)SZ_4K, &size))

I do not think check_mul_overflow() requires size_t type, does it?

arch/x86/kernel/cpu/resctrl/erdt.c line 64

Quoted 7 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +7 -0

+		return NULL;
+
+	addr = ioremap(base, size);
+	if (!addr) {
+		pr_err("ERDT: Failed to map %s at phys addr %pa (size: %u pages)\n",
+		       desc, &base, num_pages);
+	}

(unnecessary braces)

Quoted 11 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +11 -0

+	return addr;
+}
+
+static void erdt_iounmap_domain(struct erdt_domain_info *domain)
+{
+	for (int i = 0; i < ERDT_MMIO_NUM_TYPES; i++) {
+		if (domain->base[i]) {
+			iounmap(domain->base[i]);
+			domain->base[i] = NULL;
+		}
+	}

arch/x86/kernel/cpu/resctrl/erdt.c line 81

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +6 -0

+}
+
+static void cleanup_one_domain(struct erdt_domain_info *d)
+{
+	erdt_iounmap_domain(d);
+	free_cpumask_var(d->cpu_mask);

free_cpumask_var() does not look right ... it is for stack usage, no? (more later)

arch/x86/kernel/cpu/resctrl/erdt.c line 142

Quoted 1 line

arch/x86/kernel/cpu/resctrl/erdt.c new file +1 -0

+static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr)

nit: what is motivation for the "entry" term? this is only occurance of the word "entry" in this patch while RMDD is more frequently referred to as "table" or "sub-table".

arch/x86/kernel/cpu/resctrl/erdt.c line 150

Quoted 8 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +8 -0

+{
+	struct erdt_domain_info *domain_info;
+	struct acpi_subtbl_hdr_16 *subtbl;
+	struct acpi_erdt_rmdd *rmdd;
+	u32 subtbl_mask = 0;
+
+	if (rmdd_hdr->length < sizeof(*rmdd)) {
+		pr_warn(FW_BUG "Invalid RMDD length %u\n", rmdd_hdr->length);

Please include unit, similar to equivalent ERDT message.

Quoted 10 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +10 -0

+		return false;
+	}
+
+	rmdd = (struct acpi_erdt_rmdd *)rmdd_hdr;
+
+	/* Quietly ignore non-CPU-based L3 domains */
+	if (!(rmdd->flags & RMDD_FLAG_CPU_L3_DOMAIN))
+		return true;
+
+	domain_info = kzalloc_obj(*domain_info, GFP_KERNEL);

arch/x86/kernel/cpu/resctrl/erdt.c line 165

Quoted 5 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +5 -0

+	if (!domain_info)
+		return false;
+
+	if (!zalloc_cpumask_var(&domain_info->cpu_mask, GFP_KERNEL))
+		goto cleanup;

Similar to free_cpumask_var() this does not look right since the cpu_mask is not on stack here ... (more later)

arch/x86/kernel/cpu/resctrl/erdt.c line 176

Quoted 11 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +11 -0

+
+	domain_info->base[ERDT_MMIO_RMDD_CREG] =
+		erdt_ioremap(rmdd->creg_base, rmdd->creg_size, "RMDD ctrl base");
+	if (!domain_info->base[ERDT_MMIO_RMDD_CREG])
+		goto cleanup;
+
+	for (subtbl = rmdd_subtbl(rmdd);
+	     subtbl_valid((void *)rmdd + rmdd->header.length, subtbl);
+	     subtbl = next_subtbl(subtbl)) {
+		switch (subtbl->type) {
+		case ACPI_ERDT_TYPE_CACD:

It is quite subtle that there could be multiple CACD tables. Could this be highlighted with a small comment? Something like:

			/* An RMDD table has one or more CACD sub-table(s) */

Quoted 14 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +14 -0

+			if (cacd_init(subtbl, domain_info))
+				goto cleanup;
+
+			subtbl_mask |= BIT(ACPI_ERDT_TYPE_CACD);
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (!subtbl_mask)
+		goto cleanup;
+
+	/*

arch/x86/kernel/cpu/resctrl/erdt.c line 196

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +6 -0

+	 * Require all RMDDs to support same set of sub-tables
+	 */
+	if (!valid_subtbl_mask) {
+		valid_subtbl_mask = subtbl_mask;
+	} else if (subtbl_mask != valid_subtbl_mask) {
+		pr_warn(FW_BUG "RMDD sub-table set does not match the first RMDD\n");

Would it be useful to print the domain ID to help diagnistics?

arch/x86/kernel/cpu/resctrl/erdt.c line 200

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +4 -0

+		goto cleanup;
+	}
+
+	if (!rmdd->max_rmid || rmdd->max_rmid > INT_MAX) {

rmdd->max_rmid is a u32 so INT_MAX test is not clear to me here

arch/x86/kernel/cpu/resctrl/erdt.c line 201

Quoted 1 line

arch/x86/kernel/cpu/resctrl/erdt.c new file +1 -0

+		pr_warn(FW_BUG "Unreasonable RMDD max_rmid %u\n", rmdd->max_rmid);

Is there a limit in the spec?

arch/x86/kernel/cpu/resctrl/erdt.c line 204

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +3 -0

+		goto cleanup;
+	}
+	domain_info->max_rmid = rmdd->max_rmid;

As mentioned before, instead of a per-domain RMID, could there be a global ERDT RMID that is initialized by first ERDT domain and updated/compared with every following ERDT domain?

arch/x86/kernel/cpu/resctrl/erdt.c line 220

Quoted 7 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +7 -0

+
+void erdt_exit(void)
+{
+	struct erdt_domain_info *d;
+	struct list_head *pos, *n;
+
+	list_for_each_safe(pos, n, &domain_info_list) {

list_for_each_entry_safe()?

Quoted 10 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +10 -0

+		d = container_of(pos, struct erdt_domain_info, list);
+		list_del(pos);
+		cleanup_one_domain(d);
+	}
+	__erdt_enabled = false;
+	valid_subtbl_mask = 0;
+}
+
+static __init int enumerate_erdt_table(struct acpi_table_header *table_hdr)
+{

arch/x86/kernel/cpu/resctrl/erdt.c line 236

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +6 -0

+	struct acpi_table_erdt *erdt = (struct acpi_table_erdt *)table_hdr;
+	struct acpi_subtbl_hdr_16 *subtbl;
+	void *table_end;
+
+	if (erdt->header.revision != ERDT_VALID_VERSION) {
+		pr_info("Unsupported ERDT table revision %d\n", erdt->header.revision);

Would it be helpful to print what the ERDT table revision is to help diagnostics?

Please add documentation here that describes each member of struct erdt_domain_info.

arch/x86/kernel/cpu/resctrl/erdt.c line 170

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +3 -0

+struct erdt_domain_info {
+	void __iomem		*base[ERDT_MMIO_NUM_TYPES];
+	cpumask_var_t		cpu_mask;

Should this be struct cpumask instead? Compare with struct rdt_domain_hdr. When evaluating cpumask_var_t, please read the detailed comments above its definition in include/linux/cpumask_types.h - specifically note the start:
*cpumask_var_t: struct cpumask for stack usage*

arch/x86/kernel/cpu/resctrl/erdt.c line 172

Quoted 2 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +2 -0

+	int			max_rmid;
+	struct list_head	list;

Could you please rename this to be "node" or "entry" to make it obvious that this is an entry of a list? This is not consistent in resctrl but really helps when reading the code.

Hi Chenyu,

Quoted 10 lines · Reinette Chatre

Hi Chenyu,

Quoted 7 lines · Chen Yu

From: Anil S Keshavamurthy <[email protected]>

Parse the ERDT (Enhanced RDT) ACPI table so enhanced RDT features can consume firmware-provided domain information.

The ERDT may contain these sub-tables:

Quoted 9 lines

Quoted 4 lines

   - Resource Management Domain Description Structure (RMDD)
   - CPU Agent Collection Description Structure (CACD)
   - Cache Monitoring Registers for CPU Agents Description Structure (CMRC)

How should "The ERDT may contain these sub-tables" be interpreted here? This sounds like some high level partial description of ERDT that is not specific to this patch.

I planned to add some background context on ERDT. Let me remove unrelated content and change the sentence to:
Parse the RMDD subtables within the ERDT ACPI table and their nested CACD entries to construct per-domain CPU masks.

Quoted 10 lines

arch/x86/kernel/cpu/resctrl/erdt.c line 26

Quoted 8 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +8 -0

+
+#include <asm/apic.h>
+
+#include "internal.h"
+
+static LIST_HEAD(domain_info_list);
+
+static bool __erdt_enabled;

Is double underscore needed?

The double underscore was used to prevent name collisions with the existing erdt_enabled(). Let me switch it to a single underscore instead.

Quoted 4 lines

Could you please add a comment above the variable to describe what it means when "erdt is enabled"?

OK, let me add this:

/*
 * Set when the ERDT ACPI table has been successfully parsed and at least
 * one valid RMDD domain with a CACD cpumask exists. Cleared on teardown.

Quoted 10 lines

Quoted 10 lines

+        d = container_of(pos, struct erdt_domain_info, list); +        list_del(pos);
+        cleanup_one_domain(d);
+    }
+    __erdt_enabled = false;
+    valid_subtbl_mask = 0;

arch/x86/kernel/cpu/resctrl/erdt.c new file +4 -0

+}
+
+static __init int enumerate_erdt_table(struct acpi_table_header *table_hdr)
+{

Quoted 9 lines

Quoted 6 lines

+    struct acpi_table_erdt *erdt = (struct acpi_table_erdt *)table_hdr; +    struct acpi_subtbl_hdr_16 *subtbl;
+    void *table_end;
+
+    if (erdt->header.revision != ERDT_VALID_VERSION) {
+        pr_info("Unsupported ERDT table revision %d\n", erdt->header.revision);

Would it be helpful to print what the ERDT table revision is to help diagnostics?

Yes, it will print the revision, do you mean print the expected revision?

pr_info("Unsupported ERDT table revision %d (expected %d)\n", erdt->header.revision, ERDT_VALID_VERSION);

Hi Chenyu,

Quoted 12 lines

Quoted 11 lines

Quoted 6 lines

The ERDT may contain these sub-tables:

   - Resource Management Domain Description Structure (RMDD)
   - CPU Agent Collection Description Structure (CACD)
   - Cache Monitoring Registers for CPU Agents Description Structure (CMRC)

How should "The ERDT may contain these sub-tables" be interpreted here? This sounds like some high level partial description of ERDT that is not specific to this patch.

Quoted 4 lines

I planned to add some background context on ERDT. Let me remove unrelated content and change the sentence to:
Parse the RMDD subtables within the ERDT ACPI table and their nested CACD entries to construct per-domain CPU masks.

Thank you. Making this patch specific will also help to identify unrelated changes, for example the introduction of ERDT_MMIO_CMRC_BASE that would be more appropriate for the patch that uses it.

Quoted 11 lines

Quoted 10 lines

arch/x86/kernel/cpu/resctrl/erdt.c line 26

Quoted 8 lines

arch/x86/kernel/cpu/resctrl/erdt.c new file +8 -0

+
+#include <asm/apic.h>
+
+#include "internal.h"
+
+static LIST_HEAD(domain_info_list);
+
+static bool __erdt_enabled;

Is double underscore needed?

Quoted 2 lines

The double underscore was used to prevent name collisions with the existing erdt_enabled(). Let me switch it to a single underscore instead.

You say "existing" but I am not able to find erdt_enabled() in this series. Is it something that will be needed later?

Quoted 7 lines

Quoted 4 lines

Could you please add a comment above the variable to describe what it means when "erdt is enabled"?

OK, let me add this:

Quoted 3 lines

/*
 * Set when the ERDT ACPI table has been successfully parsed and at least
 * one valid RMDD domain with a CACD cpumask exists. Cleared on teardown.

To make this easier to understand, please aim to have comments that do not describe code verbatim but instead what it means. Consider, for example, something like:
"True when the ERDT ACPI table describes at least one domain with at least one CPU."

Quoted 22 lines

Quoted 10 lines

Quoted 10 lines

+        d = container_of(pos, struct erdt_domain_info, list); +        list_del(pos);
+        cleanup_one_domain(d);
+    }
+    __erdt_enabled = false;
+    valid_subtbl_mask = 0;

arch/x86/kernel/cpu/resctrl/erdt.c new file +4 -0

+}
+
+static __init int enumerate_erdt_table(struct acpi_table_header *table_hdr)
+{

Quoted 9 lines

Quoted 6 lines

+    struct acpi_table_erdt *erdt = (struct acpi_table_erdt *)table_hdr; +    struct acpi_subtbl_hdr_16 *subtbl;
+    void *table_end;
+
+    if (erdt->header.revision != ERDT_VALID_VERSION) {
+        pr_info("Unsupported ERDT table revision %d\n", erdt->header.revision);

Would it be helpful to print what the ERDT table revision is to help diagnostics?

Yes, it will print the revision, do you mean print the expected revision?

Quoted 2 lines

pr_info("Unsupported ERDT table revision %d (expected %d)\n",
        erdt->header.revision, ERDT_VALID_VERSION);

oh, apologies, I misread what you had originally. Even so, your new proposal looks good to me.
As a sidenote, please use most accurate conversion when printing, for example %u for unsigned instead of %d.

After the rdt_hw_l3_mon_domain has been created during CPU online, attach the pre-parsed ACPI ERDT table information to the rdt_hw_l3_mon_domain to facilitate monitor data read via the ERDT and its sub-tables information.

During attachment, a sanity check is triggered to verify whether the

CPU mask reported by silicon (CPUID leaf 4) matches the information exposed by firmware (CACD table). If inconsistent, this CPU will be cleared from the legitimate domain mask.

Suggested-by Reinette Chatre <[email protected]>

Tested-by Hongyu Ning <[email protected]>

Signed-off-by Chen Yu <[email protected]>

---
v4->v5:
new patch.

---
 arch/x86/kernel/cpu/resctrl/core.c     | 17 +++++++++
 arch/x86/kernel/cpu/resctrl/erdt.c     | 49 ++++++++++++++++++++++++++
 arch/x86/kernel/cpu/resctrl/internal.h |  4 +++
 3 files changed, 70 insertions(+)

arch/x86/kernel/cpu/resctrl/core.c +0 -0

index 23925bcd71d7..2e95586ebe45 100644
@@ -549,6 +549,19 @@ static void l3_mon_domain_setup(int cpu, int id, struct rdt_resource *r, struct
 	d->ci_id = ci->id;

arch/x86/kernel/cpu/resctrl/core.c +1 -0

+		}
 		break;
 	case RDT_RESOURCE_PERF_PKG:
 		if (!hdr)

arch/x86/kernel/cpu/resctrl/erdt.c +4 -0

index 6405df9be817..6c1df7e43eab 100644
@@ -212,6 +212,55 @@ static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr)
 	return false;
 }
 
+/*
+ * Associate ERDT table information with this domain.
+ */
+int erdt_l3_mon_domain_setup(int cpu, struct rdt_domain_hdr *hdr)

arch/x86/kernel/cpu/resctrl/erdt.c +19 -0

+				pr_warn(FW_BUG "Mismatch detected, CPU%d in L3 domain(%*pbl) and CACD domain(%*pbl)\n",
+					cpu, cpumask_pr_args(&hdr->cpu_mask), cpumask_pr_args(d->cpu_mask));
+
+				return -EIO;
+			}
+
+			hw_dom = resctrl_to_arch_mon_dom(container_of(hdr, struct rdt_l3_mon_domain, hdr));
+			/* No mismatch, assign the ERDT information to hw_dom */
+			if (!hw_dom->d_info)
+				hw_dom->d_info = d;
+
+			return 0;
+		}
+	}
+
+	pr_warn(FW_BUG "Cannot find CACD domain for CPU%d\n", cpu);
+	return -ENOENT;
+}
+
 void erdt_exit(void)
 {
 	struct erdt_domain_info *d;

arch/x86/kernel/cpu/resctrl/internal.h +0 -0

index 299d7222f693..7d9100b7648f 100644

arch/x86/kernel/cpu/resctrl/internal.h +0 -0

  *
  * Members of this structure are accessed via helpers that provide abstraction.
  */
 struct rdt_hw_l3_mon_domain {

Hi Chenyu,

Quoted 4 lines · Chen Yu

After the rdt_hw_l3_mon_domain has been created during CPU online, attach the pre-parsed ACPI ERDT table information to the rdt_hw_l3_mon_domain to facilitate monitor data read via the ERDT and its sub-tables information.

Please follow tip guidance for changelog by starting with context before jumping to what the patch does.

Quoted 2 lines

During attachment, a sanity check is triggered to verify whether the

Please write in imperative tone.

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/core.c +0 -0

@@ -549,6 +549,19 @@ static void l3_mon_domain_setup(int cpu, int id, struct rdt_resource *r, struct
  	d->ci_id = ci->id;
  	cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
 

arch/x86/kernel/cpu/resctrl/core.c static void l3_mon_domain_setup(int cpu, int id, struct rdt_resource *r, struct · line 559

Quoted 8 lines

arch/x86/kernel/cpu/resctrl/core.c +8 -0

+	/*
+	 * Verify whether the CPU domain information matches the ACPI data.
+	 * Skip adding the newly created domain to the list if there is a mismatch.
+	 * ACPI information should be assigned to the domain prior to its insertion
+	 * into the list, in case others might iterate the list in parallel.
+	 */
+	if (erdt_l3_mon_domain_setup(cpu, &d->hdr)) {
+		pr_warn("CPU%d has inconsistent domain information, do not add this new domain\n", cpu);

erdt_l3_mon_domain_setup() already contains a pr_warn() when there is an error, is this pr_warn() needed?

arch/x86/kernel/cpu/resctrl/core.c static void l3_mon_domain_setup(int cpu, int id, struct rdt_resource *r, struct · line 563

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/core.c +4 -0

+		cpumask_clear_cpu(cpu, &d->hdr.cpu_mask);
+		l3_mon_domain_free(hw_dom);
+		return;
+	}

Since the rdt_hw_l3_mon_domain was just allocated and the current CPU is the *only* CPU assigned to it, erdt_l3_mon_domain_setup() should never fail? I do not think any CPU checking is necessary here - when the flow reaches l3_mon_domain_setup() it can just assign the ERDT domain directly, no?

arch/x86/kernel/cpu/resctrl/core.c static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) · line 609

Quoted 12 lines

arch/x86/kernel/cpu/resctrl/core.c +4 -0

+
  	arch_mon_domain_online(r, d);
 
  	if (l3_mon_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) {

@@ -591,6 +604,10 @@ static void domain_add_cpu_mon(int cpu, struct rdt_resource *r)
  			resctrl_arch_mbm_cntr_assign_set_one(r);
  		if (!hdr)
  			l3_mon_domain_setup(cpu, id, r, add_pos);
+		else if (erdt_l3_mon_domain_setup(cpu, hdr)) {
+			pr_warn("CPU%d has inconsistent domain information, remove it from the domain\n", cpu);
+			cpumask_clear_cpu(cpu, &hdr->cpu_mask);

I do not think it is necessary to add the CPU to hdr->cpu_mask for the ERDT test to be performed (more below). It thus looks to me as though this ERDT domain assignment should be split - the error check is only needed if there is a header and if that finds a problem it can just bail early (before adding CPU to hdr->cpu_mask). Something like:

		hdr = resctrl_find_domain(&r->mon_domains, id, &add_pos);
		if (hdr) {
			if (/* This CPU's ERDT domain a NOT subset of hdr->cpu_mask */)
				bail;
			cpumask_set_cpu(cpu, &hdr->cpu_mask);
		}

		switch (r->rid) {
		case RDT_RESOURCE_L3:
			...
			if (!hdr)
				/* l3_mon_domain_setup() initializes hw_dom->d_info without CPU checking */
				l3_mon_domain_setup(cpu, id, r, add_pos);
			
			...
		}

Quoted 12 lines

arch/x86/kernel/cpu/resctrl/core.c +1 -0

+		}
  		break;
  	case RDT_RESOURCE_PERF_PKG:
  		if (!hdr)

arch/x86/kernel/cpu/resctrl/erdt.c +0 -0

index 6405df9be817..6c1df7e43eab 100644
@@ -212,6 +212,55 @@ static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr)
  	return false;
  }
 

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/erdt.c +4 -0

+/*
+ * Associate ERDT table information with this domain.
+ */
+int erdt_l3_mon_domain_setup(int cpu, struct rdt_domain_hdr *hdr)

arch/x86/kernel/cpu/resctrl/erdt.c static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr) · line 228

Quoted 10 lines

arch/x86/kernel/cpu/resctrl/erdt.c +10 -0

+{
+	struct rdt_hw_l3_mon_domain *hw_dom;
+	struct erdt_domain_info *d;
+	struct list_head *pos;
+
+	if (!__erdt_enabled)
+		return 0;
+
+	/*
+	 * Find the erdt_domain_info that contains this CPU,

Please use entire line length available.

arch/x86/kernel/cpu/resctrl/erdt.c static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr) · line 231

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/erdt.c +3 -0

+	 * compare erdt_domain_info's cpumask with the cpumask
+	 * exposed by hw_dom (derived from CPUID leaf 4).
+	 * If yes, assign the erdt_domain_info in the hw_dom,

What does "If yes" refer to?

arch/x86/kernel/cpu/resctrl/erdt.c static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr) · line 234

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/erdt.c +3 -0

+	 * otherwise this CPU should be isolated from resctrl.
+	 * For example, the hw_dom reports CPU{0,1} are in
+	 * l3 domain0, CPU{2,3} belongs to domain1. Meanwhile

Please use consistent terms (l3 -> L3, cpumask -> cpu_mask, etc.)

arch/x86/kernel/cpu/resctrl/erdt.c static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr) · line 238

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/erdt.c +4 -0

+	 * erdt_domain_info reports that CPU{0,2} are in domain0,
+	 * CPU{1,3} are in domain1. So when it comes to CPU1,
+	 * a mismatch is detected, we should remove CPU1 from
+	 * resctrl.

CPU1 and CPU2?

arch/x86/kernel/cpu/resctrl/erdt.c static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr) · line 241

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/erdt.c +3 -0

+	 */
+	list_for_each(pos, &domain_info_list) {
+		d = container_of(pos, struct erdt_domain_info, list);

list_for_each_entry()

arch/x86/kernel/cpu/resctrl/erdt.c static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr) · line 244

Quoted 3 lines

arch/x86/kernel/cpu/resctrl/erdt.c +3 -0

+
+		if (cpumask_test_cpu(cpu, d->cpu_mask)) {
+			if (!cpumask_subset(&hdr->cpu_mask, d->cpu_mask)) {

Consider the above two tests, the first, cpumask_test_cpu() already checks that CPU in parameter belongs to d->cpu_mask, it is thus not required for the same CPU to be a member of hdr->cpu_mask in the cpumask_subset() that follows? The callers currently add the CPU to hdr->cpu_mask before calling erdt_l3_mon_domain_setup() and then remove the CPU on failure ... that thus looks unnecessary? Caller can just add the CPU to hdr->cpu_mask on success?

arch/x86/kernel/cpu/resctrl/internal.h struct rdt_hw_ctrl_domain { · line 95

Quoted 7 lines

arch/x86/kernel/cpu/resctrl/internal.h +1 -0

@@ -92,14 +92,18 @@ struct rdt_hw_ctrl_domain {
   * @arch_mbm_states:	Per-event pointer to the MBM event's saved state.
   *			An MBM event's state is an array of struct arch_mbm_state
   *			indexed by RMID on x86.
+ * @d_info:		ERDT table information of this domain(read-only)

read-only in comments can be made explicit with a const below?

Quoted 1 line · Reinette Chatre

On 7/1/26 6:45 AM, Chen Yu wrote:

Quoted 6 lines

Quoted 3 lines

+     * otherwise this CPU should be isolated from resctrl. +     * For example, the hw_dom reports CPU{0,1} are in +     * l3 domain0, CPU{2,3} belongs to domain1. Meanwhile

Please use consistent terms (l3 -> L3, cpumask -> cpu_mask, etc.)

OK, will do.

Quoted 5 lines

Quoted 4 lines

+     * erdt_domain_info reports that CPU{0,2} are in domain0, +     * CPU{1,3} are in domain1. So when it comes to CPU1, +     * a mismatch is detected, we should remove CPU1 from +     * resctrl.

Quoted 2 lines

CPU1 and CPU2?

I think it should be CPU1 and CPU3 that will be removed from resctrl - because the first CPU of the hw_dom->cpumask will not find a mismatch per your description previously.

Hi Chenyu,

Quoted 8 lines

Quoted 7 lines

Quoted 4 lines

+     * erdt_domain_info reports that CPU{0,2} are in domain0, +     * CPU{1,3} are in domain1. So when it comes to CPU1, +     * a mismatch is detected, we should remove CPU1 from +     * resctrl.

CPU1 and CPU2?

Quoted 3 lines

I think it should be CPU1 and CPU3 that will be removed from resctrl - because the first CPU of the hw_dom->cpumask will not find a mismatch per your description previously.

I expected that only the CPUs CPUID and ACPI disagree on will be removed? In the example CPUID and ACPI agree on which domain CPU0 and CPU3 belongs to while they disagree on which domain CPU1 and CPU2 belongs to.

The CMRC (Cache Monitoring Registers for CPU Agents Description) sub-table of ERDT describes the MMIO registers used to read cache monitoring counters (e.g. LLC occupancy) for an RMD.

Parse each CMRC sub-table, ioremap its register window, and save the CMRC pointer in the corresponding ERDT domain entry so that later monitoring code can read the counters via MMIO.

Suggested-by Tony Luck <[email protected]>

Reviewed-by Thomas Gleixner <[email protected]>

Tested-by Hongyu Ning <[email protected]>

Signed-off-by Chen Yu <[email protected]>

---
v4->v5:
No change.

---
 arch/x86/kernel/cpu/resctrl/erdt.c     | 44 ++++++++++++++++++++++++++
 arch/x86/kernel/cpu/resctrl/internal.h |  1 +
 2 files changed, 45 insertions(+)

arch/x86/kernel/cpu/resctrl/erdt.c +2 -0

index 6c1df7e43eab..a5754d64fcc1 100644
@@ -26,6 +26,7 @@ static LIST_HEAD(domain_info_list);
 static bool __erdt_enabled;
 
 #define ERDT_VALID_VERSION		1
+#define CMRC_SUPPORTED_INDEX_FN		1
 #define RMDD_FLAG_CPU_L3_DOMAIN		BIT(0)
 
 /* Bitmask of valid sub-tables found in the first RMDD, used to ensure all RMDDs match. */

@@ -79,6 +80,7 @@ static void cleanup_one_domain(struct erdt_domain_info *d)
 {
 	erdt_iounmap_domain(d);
 	free_cpumask_var(d->cpu_mask);
+	kfree(d->cmrc);
 	kfree(d);
 }
 

arch/x86/kernel/cpu/resctrl/erdt.c +29 -0

+		pr_warn(FW_BUG "Truncated CMRC subtable\n");
+		return -EIO;
+	}
+
+	if (cmrc->index_fn != CMRC_SUPPORTED_INDEX_FN) {
+		pr_info("Unsupported CMRC index function %d\n", cmrc->index_fn);
+		return -EIO;
+	}
+
+	if (!cmrc->clump_size) {
+		pr_warn(FW_BUG "CMRC clump_size is zero\n");
+		return -EIO;
+	}
+
+	domain_info->base[ERDT_MMIO_CMRC_BASE] =
+		erdt_ioremap(cmrc->cmt_reg_base, cmrc->cmt_reg_size, "CMRC base");
+	if (!domain_info->base[ERDT_MMIO_CMRC_BASE])
+		return -EIO;
+
+	domain_info->cmrc = kmemdup(cmrc, subtbl->length, GFP_KERNEL);
+	if (!domain_info->cmrc) {
+		iounmap(domain_info->base[ERDT_MMIO_CMRC_BASE]);
+		domain_info->base[ERDT_MMIO_CMRC_BASE] = NULL;
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
 static inline struct acpi_subtbl_hdr_16 *rmdd_subtbl(struct acpi_erdt_rmdd *rmdd)
 {
 	return (void *)rmdd + sizeof(*rmdd);

arch/x86/kernel/cpu/resctrl/erdt.c +4 -0

+			if (!(subtbl_mask & BIT(ACPI_ERDT_TYPE_CMRC)) &&
+			    !cmrc_init(subtbl, domain_info))
+				subtbl_mask |= BIT(ACPI_ERDT_TYPE_CMRC);
+
 			break;
 		default:
 			break;

arch/x86/kernel/cpu/resctrl/internal.h +0 -0

index 7d9100b7648f..3dab05c38003 100644

Hi Chenyu,

Quoted 3 lines · Chen Yu

The CMRC (Cache Monitoring Registers for CPU Agents Description) sub-table of ERDT describes the MMIO registers used to read cache monitoring counters (e.g. LLC occupancy) for an RMD.

Please use the entire line length available (please check all changelogs). Some context for this request:
https://lore.kernel.org/lkml/20250916105447.GCaMlB976WLxHHeNMD@fat_crate.local/

Quoted 4 lines

Parse each CMRC sub-table, ioremap its register window, and save the CMRC pointer in the corresponding ERDT domain entry so that later monitoring code can read the counters via MMIO.

Is the "save the CMRC pointer ..." referring to how resctrl makes a copy of the CMRC table? If so, that is very different from "saving a pointer".

arch/x86/kernel/cpu/resctrl/erdt.c static __init int cacd_init(struct acpi_subtbl_hdr_16 *subtbl, · line 122

Quoted 6 lines

arch/x86/kernel/cpu/resctrl/erdt.c +6 -0

+static __init int cmrc_init(struct acpi_subtbl_hdr_16 *subtbl,
+			    struct erdt_domain_info *domain_info)
+{
+	struct acpi_erdt_cmrc *cmrc = (struct acpi_erdt_cmrc *)subtbl;
+
+	if (subtbl->length < sizeof(*cmrc)) {

I think it will be helpful if the ERDT parsing code uses consistent patterns. Here, for example, now that a pointer of accurate type is available via cmrc, can cmrc be referenced instead to be consistent with cacd_init()?

Quoted 7 lines

arch/x86/kernel/cpu/resctrl/erdt.c +1 -0

+
  static inline struct acpi_subtbl_hdr_16 *rmdd_subtbl(struct acpi_erdt_rmdd *rmdd)
  {
  	return (void *)rmdd + sizeof(*rmdd);

@@ -178,6 +215,13 @@ static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr)
  				goto cleanup;
 

arch/x86/kernel/cpu/resctrl/erdt.c static __init bool parse_rmdd_entry(struct acpi_subtbl_hdr_16 *rmdd_hdr) · line 220

Quoted 4 lines

arch/x86/kernel/cpu/resctrl/erdt.c +3 -0

  			subtbl_mask |= BIT(ACPI_ERDT_TYPE_CACD);
+			break;
+		case ACPI_ERDT_TYPE_CMRC:
+			/* TBD: Only 1 CMRR per domain is allowed? */

Who are you asking this question to?

Monitoring counter values are currently obtained via MSR and many identifiers involved in processing these values contain "msr" as part of their names, for example "prev_msr" and "msr_val".

The ERDT ACPI table describes MMIO registers for monitoring data access. Rename "msr"-based identifiers to be interface-agnostic to support their upcoming use for MMIO-read values.

No functional change.

Reviewed-by Thomas Gleixner <[email protected]>

Tested-by Hongyu Ning <[email protected]>

Signed-off-by Chen Yu <[email protected]>

---

From: Tony Luck <[email protected]>

Currently, mon_evt::any_cpu is false for all events associated with RDT_RESOURCE_L3. The MMIO-based CMT will set any_cpu to true in a follow-up patch. This change will trigger a warning when calling

smp_processor_id() inside __l3_mon_event_count(), because __l3_mon_event_count() may be invoked from arbitrary CPUs in task context. Since the calling context is preemptible here, smp_processor_id() will emit a debug warning.

To prepare for MMIO-based CMT reads, skip the current CPU lookup when an event's any_cpu flag is set. Events with this flag do not require execution on a specific CPU.

Introduce erdt_cpu_has() to verify if a specific RDT feature is backed by an ERDT table. erdt_cpu_has() is derived from rdt_cpu_has(), which not only considers firmware (ERDT table and its sub-tables) support for an event, but also considers userspace input like "rdt=!cmt". erdt_cpu_has() expects the same input parameters as

rdt_cpu_has().

Introduce erdt_mon_read(), a helper that retrieves monitoring data for a given RMID and event ID from an ERDT domain. erdt_mon_read() leverages erdt_cpu_has() to check whether the system supports the corresponding ACPI tables, such as ERDT and CMRC (Cache Monitoring Registers for CPU Agents Description). It invokes the low-level MMIO read callbacks (introduced later) if supported.

Tested-by Hongyu Ning <[email protected]>

Signed-off-by Chen Yu <[email protected]>

---

arch/x86/include/asm/resctrl.h +2 -0

index 575f8408a9e7..0fd4bf85f628 100644
@@ -49,6 +49,8 @@ DECLARE_STATIC_KEY_FALSE(rdt_enable_key);
 DECLARE_STATIC_KEY_FALSE(rdt_alloc_enable_key);
 DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key);
 
+bool erdt_cpu_has(int flag);
+
 static inline bool resctrl_arch_alloc_capable(void)
 {
 	return rdt_alloc_capable;

arch/x86/include/asm/resctrl.h +0 -0

 	/* h/w works in units of "boot_cpu_data.x86_cache_occ_scale" */
 	val /= scale;
 	return val * scale;

arch/x86/kernel/cpu/resctrl/core.c +0 -0

index 2e95586ebe45..5932cf813cb4 100644

arch/x86/kernel/cpu/resctrl/core.c +21 -1

+
+	if (!ret)
+		return ret;
+
+	for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
+		if (flag == o->flag) {
+			if (o->force_off)
+				ret = false;
+			if (o->force_on)
+				ret = true;
+			break;
+		}
+	}
+
+	return ret;
+}
+
 bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt)
 {
 	if (!rdt_cpu_has(X86_FEATURE_BMEC))

@@ -982,7 +1005,10 @@ static __init bool get_rdt_mon_resources(void)
 	struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
 	bool ret = false;
 
-	if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) {
+	if (erdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) {
+		resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, true, 0, NULL);
+		ret = true;
+	} else if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) {
 		resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false, 0, NULL);
 		ret = true;
 	}

arch/x86/kernel/cpu/resctrl/erdt.c +3 -0

+	return -EIO;
+}
+
 static void __iomem *erdt_ioremap(phys_addr_t base, u32 num_pages, const char *desc)
 {
 	void __iomem *addr;

arch/x86/kernel/cpu/resctrl/internal.h +3 -0

index 6eb0fdea6b63..ecb44f82581e 100644
@@ -278,8 +278,11 @@ static inline void intel_aet_mon_domain_setup(int cpu, int id, struct rdt_resour
 static inline bool intel_handle_aet_option(bool force_off, char *tok) { return false; }
 #endif
 
+bool erdt_support_features(int flag);
+bool erdt_cpu_has(int flag);
 int erdt_get_max_rmid(int cpu);
 int erdt_init(void);
 void erdt_exit(void);
+int erdt_mon_read(struct rdt_domain_hdr *hdr, int ev_id, int rmid, u64 *val);
 
 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */

arch/x86/kernel/cpu/resctrl/monitor.c +9 -0

index f4f4c9015ceb..e6d7037f000b 100644
@@ -279,6 +279,10 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr,
 
 	switch (r->rid) {
 	case RDT_RESOURCE_L3:
+		if (eventid == QOS_L3_OCCUP_EVENT_ID &&
+		    erdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC))
+			return erdt_mon_read(hdr, eventid, rmid, val);
+
 		return arch_l3_read_event(hdr, rmid, eventid, val, r);
 	case RDT_RESOURCE_PERF_PKG:
 		return intel_aet_read_event(hdr->id, rmid, arch_priv, val);

@@ -423,6 +427,11 @@ int __init rdt_get_l3_mon_config(struct rdt_resource *r)
 {
 	unsigned int mbm_offset = boot_cpu_data.x86_cache_mbm_width_offset;
 	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
+	/*
+	 * Currently assume all CPU domains share the same maximum RMID
+	 * value from the RMDD table, use CPU0 domain's value.
+	 */
+	int erdt_max_rmid = erdt_get_max_rmid(0);
 	unsigned int threshold;
 	u32 eax, ebx, ecx, edx;
 

arch/x86/kernel/cpu/resctrl/monitor.c +3 -0

+	} else {
+		r->mon_capable = true;
+	}
 
 	return 0;
 }

fs/resctrl/monitor.c +0 -0

index 6a7c86a72c51..2cf03e4cf72a 100644

fs/resctrl/monitor.c +0 -0

 bool resctrl_is_mon_event_enabled(enum resctrl_event_id eventid)
 {
 	return eventid >= QOS_FIRST_EVENT && eventid < QOS_NUM_EVENTS &&

include/linux/resctrl.h +0 -0

index 73ff522448a0..dfde025432ab 100644

Implement the erdt_mon_read().

Use the CMRC (Cache Monitoring Registers for CPU Agents Description) ACPI sub-table to read LLC occupancy counters for each RMID via MMIO when ERDT is enabled. This CMRC information is stored in the rdt_hw_l3_mon_domain, which could be accessed directly.

Suggested-by Reinette Chatre <[email protected]>

Signed-off-by Chen Yu <[email protected]>

---
v4->v5:
Split into a smaller patch; no functional code changes in the low level implementation, but read from the CMRC information stored per domain .

---
 arch/x86/kernel/cpu/resctrl/erdt.c | 63 ++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

arch/x86/kernel/cpu/resctrl/erdt.c +27 -0

index 1114ad4e3b42..f897c7e247bb 100644
@@ -36,6 +36,9 @@ static u32 valid_subtbl_mask;
 
 bool erdt_support_features(int flag)
 {
+	if (flag == X86_FEATURE_CQM_OCCUP_LLC)
+		return valid_subtbl_mask & BIT(ACPI_ERDT_TYPE_CMRC);
+
 	return false;
 }
 

@@ -57,8 +60,68 @@ int erdt_get_max_rmid(int cpu)
 	return -1;
 }
 
+static void __iomem *cmrc_index_function_1(struct erdt_domain_info *d,
+					   struct acpi_erdt_cmrc *cmrc, int rmid)
+{
+	u16 clump_size, stride_size;
+	void __iomem *vaddr;
+
+	clump_size = cmrc->clump_size;
+	stride_size = cmrc->clump_stride;
+
+	/*
+	 * MMIO_ADDRESS_for_RMID# = CMRC Base +
+	 *   (RMID / ClumpSize) * Stride +
+	 *   (RMID % ClumpSize) * 8
+	 */
+	vaddr = d->base[ERDT_MMIO_CMRC_BASE] +
+		(rmid / clump_size) * stride_size +
+		(rmid % clump_size) * 8;
+
+	return vaddr;
+}
+
+static int erdt_read_l3_occupancy(struct erdt_domain_info *d, int rmid, u64 *val)
+{
+	struct acpi_erdt_cmrc *cmrc;

arch/x86/kernel/cpu/resctrl/erdt.c +5 -0

+	/* Overflow of cmt_reg_size * SZ_4K already validated in erdt_ioremap(). */
+	if (offset + sizeof(u64) > (u32)cmrc->cmt_reg_size * SZ_4K)
+		return -EINVAL;
+
+	vaddr = cmrc_index_function_1(d, cmrc, rmid);