arm64: dts: freescale: imx8mn-var-som: Align SOM and Symphony DTSs

PATCH Superseded Stefano Radaelli 2 participants 22 messages Jul 3

Subsystems (2)

Device tree bindings Arm i.MX and Layerscape

lore

Share & tools

lore

Stefano Radaelli

author

2026-07-03 08:46 UTC #0 lore raw

cover arm64: dts: freescale: imx8mn-var-som: Align SOM and Symphony DTSs

This series aligns the i.MX8MN VAR-SOM and VAR-SOM Symphony device trees with the latest hardware revisions.

As the i.MX8MN device tree hierarchy closely mirrors the i.MX8MM one, this series applies the same alignment already accepted for the i.MX8MM platform, ensuring a consistent hardware description across both families.

The update consolidates the device tree descriptions to better reflect the actual hardware partitioning between the SOM and the carrier board. Nodes describing peripherals physically present on the SOM are kept in the SOM dtsi, while carrier-specific components are described in the corresponding carrier dts.

The changes were tested on the latest VAR-SOM and Symphony hardware revision.

Stefano Radaelli (15):
arm64: dts: freescale: imx8mn-var-som: Move UART4 description to
Symphony
arm64: dts: freescale: imx8mn-var-som: move SD card support to
Symphony
arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tables
arm64: dts: freescale: imx8mn-var-som: Update FEC support with
MaxLinear PHY
arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio
codec
arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller
arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy
dts
arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node
arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface
arm64: dts: imx8mn-var-som-symphony: Add TPM2 support
arm64: dts: imx8mn-var-som-symphony: Enable I2C4
arm64: dts: imx8mn-var-som-symphony: add wakeup sources
arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low
arm64: dts: imx8mn-var-som-symphony: enable PWM1
arm64: dts: imx8mn-var-som-symphony: Disable internal RTC

 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../imx8mn-var-som-symphony-legacy.dts        |  19 +
 .../dts/freescale/imx8mn-var-som-symphony.dts | 162 +++++++-
 .../imx8mn-var-som-wifi-brcm-legacy.dtsi      |  12 +
 .../imx8mn-var-som-wifi-bt-iw61x.dtsi         |  45 +++
 .../boot/dts/freescale/imx8mn-var-som.dtsi    | 364 ++++++++++--------
 6 files changed, 446 insertions(+), 157 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi

base-commit: d0c222c2e2ce577d801bdf129dc6c078f29e22df

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #1 lore raw

PATCH 1/15 arm64: dts: freescale: imx8mn-var-som: Move UART4 description to Symphony

From: Stefano Radaelli <[email protected]>

The VAR-SOM-MX8MN module does not provide an onboard debug console. UART4 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART.

Move the UART4 node from the SOM device tree to the imx8mn-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../dts/freescale/imx8mn-var-som-symphony.dts  | 18 ++++++++++++++++++
 .../boot/dts/freescale/imx8mn-var-som.dtsi     | 18 ------------------
 2 files changed, 18 insertions(+), 18 deletions(-)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +18 -0

index 3434b189fa58..b07e71d3adee 100644
@@ -15,6 +15,10 @@ / {
 	model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
 	compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
 
+	chosen {
+		stdout-path = &uart4;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";

@@ -171,6 +175,13 @@ &uart3 {
 	status = "okay";
 };
 
+/* Console */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
 &usbotg1 {
 	dr_mode = "otg";
 	hnp-disable;

@@ -234,4 +245,11 @@ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
 			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
 		>;
 	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
+			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
+		>;
+	};
 };

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 ~~-18~~

index 38ef9e4fdf07..32f101ef2850 100644
@@ -11,10 +11,6 @@ / {
 	model = "Variscite VAR-SOM-MX8MN module";
 	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
 
-	chosen {
-		stdout-path = &uart4;
-	};
-
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0x0 0x40000000 0 0x40000000>;

@@ -274,13 +270,6 @@ &uart2 {
 	status = "okay";
 };
 
-/* Console */
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "okay";
-};
-
 &usbotg1 {
 	dr_mode = "otg";
 	usb-role-switch;

@@ -432,13 +421,6 @@ MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
 		>;
 	};
 
-	pinctrl_uart4: uart4grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
-			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
-		>;
-	};
-
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #2 lore raw

PATCH 2/15 arm64: dts: freescale: imx8mn-var-som: move SD card support to Symphony

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

The VAR-SOM-MX8MN module does not provide an onboard SD card slot. USDHC2 is routed to the SD card slot on the Symphony carrier board.

Move the USDHC2 node and pinctrl configuration from the SOM device tree to imx8mn-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../dts/freescale/imx8mn-var-som-symphony.dts | 57 +++++++++++++++++++
 .../boot/dts/freescale/imx8mn-var-som.dtsi    | 56 ------------------
 2 files changed, 57 insertions(+), 56 deletions(-)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +57 -0

index b07e71d3adee..7308613a48b2 100644
@@ -28,6 +28,7 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
+		off-on-delay-us = <20000>;
 	};
 
 	gpio-keys {

@@ -200,6 +201,20 @@ usb1_drd_sw: endpoint {
 	};
 };
 
+/* SD */
+&usdhc2 {
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl_captouch: captouchgrp {
 		fsl,pins = <

@@ -252,4 +267,46 @@ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
 			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
 		>;
 	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
 };

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 ~~-56~~

68 lines not on this page · raw message

Signature · 1 line

2.47.3

[email protected]

AI review

2026-07-03 08:54 UTC #3 lore raw

Re: [PATCH v1 02/15] arm64: dts: freescale: imx8mn-var-som: move SD card support to Symphony

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] Moving the `&usdhc2` base configuration out of `imx8mn-var-som.dtsi` completely disables SD card…

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Moving the &usdhc2 base configuration out of imx8mn-var-som.dtsi completely disables SD card support on the imx8mn-rve-gateway.dts carrier board.
- [Medium] The patch silently introduces a functional change to the regulator power sequencing by adding off-on-delay-us = <20000>; to the SD card VMMC regulator. --

commit 2f4cda5f00417bf4a0771aca7e26c1a6e92521a3
Author: Stefano Radaelli <[email protected]>

arm64: dts: freescale: imx8mn-var-som: move SD card support to Symphony

The commit moves the USDHC2 node and pinctrl configuration from the SOM device tree to the Symphony carrier board device tree. It intends to keep the SOM dtsi limited only to hardware present on the module itself.

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts reg_usdhc2_vmmc: regulator-usdhc2-vmmc { · line 32

Quoted 10 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +1 -0

index b07e71d3adeee..7308613a48b2b 100644
@@ -28,6 +28,7 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
+		off-on-delay-us = <20000>;
 	};

[Severity: Medium]
Is it intentional to add off-on-delay-us here without mentioning it in the commit message? This introduces a functional change to the regulator power sequencing that seems unrelated to simply moving the nodes between files.

[ ... ]

Quoted 12 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -4

index 32f101ef28500..e1d2e2a72e1f5 100644
@@ -295,20 +295,6 @@ brcmf: wifi@1 {
 	};
 };
 
-/* SD */
-&usdhc2 {
-	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
-	assigned-clock-rates = <200000000>;

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi brcmf: wifi@1 { · line 311

Quoted 10 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 ~~-10~~

-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
-	bus-width = <4>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	status = "okay";
-};
-

[Severity: High]
Does moving this base configuration out of the SOM dtsi break SD card support on other carrier boards like the RVE gateway?

The imx8mn-rve-gateway.dts relies on the SOM dtsi setting status = "okay" and configuring base hardware requirements for &usdhc2. Because the SoC devicetree imx8mn.dtsi sets status = "disabled" for usdhc2 by default, moving this enabling and setup exclusively to the Symphony board leaves the RVE gateway with a disabled SD card interface lacking clock assignments and pinmux configurations.

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2

Stefano Radaelli

author

2026-07-03 08:46 UTC #4 lore raw

PATCH 3/15 arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tables

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Reformat the fsl,pins tables in the i.MX8MN VAR-SOM device tree to use consistent column alignment across all pinctrl groups.

Align the entries to match the formatting already used in the pinctrl_fec1 group, which contains the longest pin definitions, for improved readability and consistency.

No functional changes intended.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../boot/dts/freescale/imx8mn-var-som.dtsi    | 126 +++++++++---------
 1 file changed, 63 insertions(+), 63 deletions(-)

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +63 ~~-63~~

index e1d2e2a72e1f..71a2f0866822 100644
@@ -368,129 +368,129 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
+			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
+			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
 		>;
 	};
 
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
-			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
+			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
+			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
 		>;
 	};
 
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
+			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8		0x141
 		>;
 	};
 
 	pinctrl_reg_eth_phy: regethphygrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
+			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9		0x41
 		>;
 	};
 
 	pinctrl_restouch: restouchgrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
+			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x1c0
 		>;
 	};
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
-			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
-			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
-			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
+			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x140
+			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x140
+			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x140
+			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x140
 		>;
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x190
+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
 		>;
 	};
 
 	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x194
+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4
+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4
+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4
+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4
+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4
 		>;
 	};
 
 	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
+			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x196
+			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6
+			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6
+			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6
+			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6
+			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6
 		>;
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
 		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
 		>;
 	};
 
 	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
 		>;
 	};
 
 	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
 		>;
 	};
 
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
 		>;
 	};
 };

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #5 lore raw

PATCH 4/15 arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY.

Add the PHY VDDIO supply regulator, adjust reset timings and add a pinctrl sleep state for low-power operation.

The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring.

Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony).
Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../dts/freescale/imx8mn-var-som-symphony.dts | 20 ++++++++++++++++++-
 .../boot/dts/freescale/imx8mn-var-som.dtsi    | 20 ++++++++++---------
 2 files changed, 30 insertions(+), 10 deletions(-)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +19 -1

index 7308613a48b2..520aff23e587 100644
@@ -8,6 +8,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/usb/pd.h>
 #include "imx8mn-var-som.dtsi"

@@ -74,7 +75,24 @@ reg_per_3v3: regulator-peripheral-3v3 {
 };
 
 &ethphy {
-	reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
+	leds {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_YELLOW>;
+			function = LED_FUNCTION_LAN;
+			linux,default-trigger = "netdev";
+		};
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			linux,default-trigger = "netdev";
+		};
+	};
 };
 
 &i2c2 {

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +11 -9

index 71a2f0866822..09146ab76385 100644
@@ -35,6 +35,13 @@ reg_3v3_fixed: regulator-3v3-fixed {
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};
+
+	reg_phy_vddio: regulator-phy-vddio {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
 };
 
 &A53_0 {

@@ -96,24 +103,19 @@ &fec1 {
 	phy-mode = "rgmii";
 	phy-handle = <&ethphy>;
 	phy-supply = <&reg_eth_phy>;
-	fsl,magic-packet;
 	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
+		ethphy: ethernet-phy@4 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <4>;
 			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
-			/*
-			 * Deassert delay:
-			 * ADIN1300 requires 5ms.
-			 * AR8033   requires 1ms.
-			 */
-			reset-deassert-us = <20000>;
+			reset-deassert-us = <100000>;
+			vddio-supply = <&reg_phy_vddio>;
 		};
 	};
 };

@@ -342,7 +344,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
 			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
 			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
 			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x159
+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
 		>;
 	};

Signature · 1 line

2.47.3

[email protected]

AI review

2026-07-03 09:02 UTC #6 lore raw

Re: [PATCH v1 04/15] arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] Modifying the shared SOM `.dtsi` and carrier `.dts` in-place to support the latest hardware…

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Modifying the shared SOM .dtsi and carrier .dts in-place to support the latest hardware revision breaks backwards compatibility with older deployed SOMs and carrier boards.
- [Medium] The commit message claims to add a pinctrl sleep state for low-power operation, but the patch modifies the default active pinctrl state instead, and the sleep state already existed. --

commit 5e21026bff4a0a2d4def4c7f976bcf398976eb95
Author: Stefano Radaelli <[email protected]>

arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY

Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY.

Quoted 4 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +0 -0
index 7308613a48b2b..520aff23e5872 100644

[ ... ]

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts reg_per_3v3: regulator-peripheral-3v3 { · line 79

Quoted 7 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +2 -1

@@ -74,7 +75,24 @@ reg_per_3v3: regulator-peripheral-3v3 {
 };
 
 &ethphy {
-	reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
+	leds {
+		#address-cells = <1>;

[Severity: High]
Does removing the carrier board reset GPIO override break backwards compatibility with older deployed SOMs and carrier boards?

Booting a new kernel on older hardware (using AR8033 or ADIN1300 PHYs) will use the new MaxLinear PHY configuration and drop the carrier board's pca9534 reset GPIO line.

While later patches in this series add a legacy DTB to restore legacy Wi-Fi configuration, it includes imx8mn-var-som-symphony.dts without overriding the Ethernet configuration. Legacy boards might still receive the broken Ethernet bindings and lose networking.

Quoted 4 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -0
index 71a2f0866822f..09146ab763858 100644

[ ... ]

Quoted 18 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +1 -3

@@ -96,24 +103,19 @@ &fec1 {
 	phy-mode = "rgmii";
 	phy-handle = <&ethphy>;
 	phy-supply = <&reg_eth_phy>;
-	fsl,magic-packet;
 	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
+		ethphy: ethernet-phy@4 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <4>;
 			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
-			/*

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi &fec1 { · line 121

Quoted 10 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +2 -5

-			 * Deassert delay:
-			 * ADIN1300 requires 5ms.
-			 * AR8033   requires 1ms.
-			 */
-			reset-deassert-us = <20000>;
+			reset-deassert-us = <100000>;
+			vddio-supply = <&reg_phy_vddio>;
 		};
 	};
 };

[Severity: High]
Similarly, overwriting the shared SOM description in-place for the new hardware revision effectively drops Ethernet support for older models.

Will older revisions of the SOM that use the AR8033 or ADIN1300 PHYs fail to probe the Ethernet PHY after this change?

[ ... ]

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f · line 349

Quoted 8 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +1 -1

@@ -342,7 +344,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
 			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
 			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
 			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x159
+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
 		>;
 	};

[Severity: Medium]
The commit message states this patch will "add a pinctrl sleep state for low-power operation." Is this description accurate?

The patch modifies the default active pinctrl state, rather than adding or updating a sleep state, which already existed. Could the commit message be clarified to reflect that the pull-up configuration on the reset pin in the default state is being altered?

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=4

Stefano Radaelli

author

2026-07-03 08:46 UTC #7 lore raw

PATCH 5/15 arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

The VAR-SOM-MX8MN can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications.

Add the WM8904 device to the appropriate I2C bus, enable the SAI peripheral, and introduce the sound node to expose the sound card to the system.

Add I3C recovery gpio properties.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../boot/dts/freescale/imx8mn-var-som.dtsi    | 98 ++++++++++++++++++-
 1 file changed, 95 insertions(+), 3 deletions(-)

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +95 -3

index 09146ab76385..e2e04ad2fbb6 100644
@@ -16,6 +16,14 @@ memory@40000000 {
 		reg = <0x0 0x40000000 0 0x40000000>;
 	};
 
+	reg_audio_supply: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "wm8904-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
 	reg_eth_phy: regulator-eth-phy {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";

@@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio {
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
 	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "wm8904-audio";
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"IN2L", "Line In Jack",
+			"IN2R", "Line In Jack",
+			"IN1L", "Microphone Jack",
+			"IN1R", "Microphone Jack";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack",
+			"Line", "Line In Jack";
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&wm8904>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai5>;
+		};
+	};
 };
 
 &A53_0 {

@@ -246,18 +282,55 @@ eeprom_som: eeprom@52 {
 
 &i2c3 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
-	/* TODO: configure audio, as of now just put a placeholder */
 	wm8904: codec@1a {
 		compatible = "wlf,wm8904";
 		reg = <0x1a>;
-		status = "disabled";
+		#sound-dai-cells = <0>;
+		clocks = <&clk IMX8MN_CLK_SAI5_ROOT>;
+		clock-names = "mclk";
+		AVDD-supply = <&ldo5_reg>;
+		CPVDD-supply = <&ldo5_reg>;
+		DBVDD-supply = <&reg_audio_supply>;
+		DCVDD-supply = <&ldo5_reg>;
+		MICVDD-supply = <&ldo5_reg>;
+		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+				    "soft", "music";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
+		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
+		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
 	};
 };
 
+&sai5 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai5>;
+	assigned-clocks = <&clk IMX8MN_CLK_SAI5>;
+	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <1536000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };

@@ -375,6 +448,13 @@ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
 		>;
 	};
 
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18		0x1c3
+			MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19		0x1c3
+		>;
+	};
+
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3

@@ -400,6 +480,18 @@ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x1c0
 		>;
 	};
 
+	pinctrl_sai5: sai5grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0xd6
+			MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC		0xd6
+			MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0xd6
+			MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0xd6
+			MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK		0xd6
+			MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0xd6
+			MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK		0xd6
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x140

Signature · 1 line

2.47.3

[email protected]

AI review

2026-07-03 08:55 UTC #8 lore raw

Re: [PATCH v1 05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The commit message claims to add 'I3C' recovery GPIO properties, but the patch actually adds…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message claims to add 'I3C' recovery GPIO properties, but the patch actually adds standard I2C recovery properties to an I2C bus. --

commit 460d6d4855137d91e75cf4e76f05f397a7d5bb75
Author: Stefano Radaelli <[email protected]>

arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec

This commit adds support for the WM8904 audio codec to the VAR-SOM-MX8MN board. It enables the I2C device, the SAI peripheral, and exposes the sound node via a simple-audio-card configuration. Additionally, it configures the I2C bus recovery pins.

Quoted 1 line

Add I3C recovery gpio properties.

[Severity: Medium]
This isn't a bug in the code, but there appears to be a typo in the commit message. The patch adds standard I2C recovery properties to the i2c3 node rather than anything related to I3C. Could this be corrected to say "I2C3" or "I2C" instead of "I3C"?

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=5

Stefano Radaelli

author

2026-07-03 08:46 UTC #9 lore raw

PATCH 6/15 arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add support for the Microchip MCP251xFD CAN-FD controller connected to the SPI bus on the i.MX8MN VAR-SOM.

The controller uses a 40 MHz external oscillator and requires an interrupt line and a dedicated RX interrupt GPIO.

Add the fixed clock, the MCP251xFD device node with the required properties, and the corresponding pinctrl configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../boot/dts/freescale/imx8mn-var-som.dtsi    | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +27 -0

index e2e04ad2fbb6..ac22dd3e6542 100644
@@ -11,6 +11,13 @@ / {
 	model = "Variscite VAR-SOM-MX8MN module";
 	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
 
+	clk40m: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+		clock-output-names = "can_osc";
+	};
+
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0x0 0x40000000 0 0x40000000>;

@@ -130,6 +137,19 @@ touchscreen@0 {
 		ti,keep-vref-on;
 		wakeup-source;
 	};
+
+	/* CAN controller */
+	can0: can@1 {
+		compatible = "microchip,mcp251xfd";
+		reg = <1>;
+		clocks = <&clk40m>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_can>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		spi-max-frequency = <20000000>;
+		microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &fec1 {

@@ -391,6 +411,13 @@ &wdog1 {
 };
 
 &iomuxc {
+	pinctrl_can: cangrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x1c0
+			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12		0x16
+		>;
+	};
+
 	pinctrl_ecspi1: ecspi1grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #10 lore raw

PATCH 7/15 arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

The VAR-SOM-MX8MN currently integrates the NXP IW61x wireless module, providing WiFi over SDIO and Bluetooth over UART.

Move the wireless module configuration out of the base imx8mn-var-som.dtsi and provide dedicated variant includes. The IW61x configuration is moved to imx8mn-var-som-wifi-bt-iw61x.dtsi and used by the Symphony evaluation board device tree.

A separate imx8mn-var-som-wifi-brcm-legacy.dtsi include is added to keep the configuration for the legacy Broadcom SDIO WiFi module used on earlier SOM revisions.

To preserve compatibility with older SOM revisions, add a separate imx8mn-var-som-symphony-legacy.dtb, which disables the IW61x setup and applies the Broadcom-specific configuration.

The Broadcom-based SOM revision is no longer in production, but support is kept for existing users.

This keeps the VAR-SOM-MX8MN support aligned with the existing VAR-SOM-MX8MM implementation.

Signed-off-by Stefano Radaelli <[email protected]>

---
 arch/arm64/boot/dts/freescale/Makefile        |  1 +
 .../imx8mn-var-som-symphony-legacy.dts        | 19 ++++++++
 .../dts/freescale/imx8mn-var-som-symphony.dts |  1 +
 .../imx8mn-var-som-wifi-brcm-legacy.dtsi      | 12 +++++
 .../imx8mn-var-som-wifi-bt-iw61x.dtsi         | 45 +++++++++++++++++++
 .../boot/dts/freescale/imx8mn-var-som.dtsi    |  6 ---
 6 files changed, 78 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi

arch/arm64/boot/dts/freescale/Makefile +1 -0

index 430085123b4e..bdd3818d6e79 100644
@@ -206,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb
 DTC_FLAGS_imx8mn-solidsense-n8-compact += -@
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony-legacy.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
 
 imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file +19 -0

new file mode 100644
index 000000000000..5998ebcef474
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Variscite Ltd.
+ */
+
+#include "imx8mn-var-som-symphony.dts"
+#include "imx8mn-var-som-wifi-brcm-legacy.dtsi"
+
+&bluetooth_iw61x {
+	status = "disabled";
+};
+
+&iw61x_pwrseq {
+	status = "disabled";
+};
+
+&usdhc1 {
+	/delete-property/ mmc-pwrseq;
+};

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +1 -0

index 520aff23e587..53130b521b5b 100644
@@ -11,6 +11,7 @@
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/usb/pd.h>
 #include "imx8mn-var-som.dtsi"
+#include "imx8mn-var-som-wifi-bt-iw61x.dtsi"
 
 / {
 	model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";

arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi new file +12 -0

new file mode 100644
index 000000000000..f44a846ea6f9
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 Variscite Ltd.
+ */
+
+/* WIFI */
+&usdhc1 {
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};

arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi new file +45 -0

45 lines not on this page · raw message

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -6

index ac22dd3e6542..ff5f658b33de 100644
@@ -371,7 +371,6 @@ &usbotg1 {
 	status = "okay";
 };
 
-/* WIFI */
 &usdhc1 {
 	#address-cells = <1>;
 	#size-cells = <0>;

@@ -383,11 +382,6 @@ &usdhc1 {
 	non-removable;
 	keep-power-in-suspend;
 	status = "okay";
-
-	brcmf: wifi@1 {
-		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
-	};
 };
 
 /* eMMC */

Signature · 1 line

2.47.3

[email protected]

AI review

2026-07-03 08:57 UTC #11 lore raw

Re: [PATCH v1 07/15] arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] The removal of the Broadcom WiFi node from `imx8mn-var-som.dtsi` silently breaks WiFi support on…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The removal of the Broadcom WiFi node from imx8mn-var-som.dtsi silently breaks WiFi support on the downstream imx8mn-rve-gateway board.
- [Medium] Incomplete reversion of IW61x pinmux changes in the legacy device tree.
- [Low] Unnecessary #address-cells and #size-cells properties are left in usdhc1, which will trigger dtc warnings for boards without a WiFi child node. --

commit 5a726be8cbb43e633eba48d88581647aae4f82ba
Author: Stefano Radaelli <[email protected]>

arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts

The VAR-SOM-MX8MN currently integrates the NXP IW61x wireless module, providing WiFi over SDIO and Bluetooth over UART.

Move the wireless module configuration out of the base imx8mn-var-som.dtsi and provide dedicated variant includes.

Quoted 6 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file +0 -0
new file mode 100644
index 0000000000000..5998ebcef4740
@@ -0,0 +1,19 @@

[ ... ]

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts line 19

Quoted 11 lines

+&bluetooth_iw61x {
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file +10 -0
+	status = "disabled";
+};
+
+&iw61x_pwrseq {
+	status = "disabled";
+};
+
+&usdhc1 {
+	/delete-property/ mmc-pwrseq;
+};

[Severity: Medium]
Does this leave unintended pin configurations active for the legacy board?

Since this file includes imx8mn-var-som-symphony.dts, it inherits the pinctrl properties from imx8mn-var-som-wifi-bt-iw61x.dtsi:

&usdhc1 {
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
};

Should this legacy file also override the pinctrl properties to remove <&pinctrl_wifi> and <&pinctrl_bt> from usdhc1 and uart2 to prevent hardware conflicts on GPIO2_IO6, GPIO2_IO10, and GPIO2_IO20?

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi &usbotg1 { · line 376

Quoted 12 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -1

index ac22dd3e65421..ff5f658b33ded 100644
@@ -371,7 +371,6 @@ &usbotg1 {
 	status = "okay";
 };
 
-/* WIFI */
 &usdhc1 {
 	#address-cells = <1>;
 	#size-cells = <0>;

[Severity: Low]
Will leaving these properties here trigger avoid_unnecessary_addr_size dtc warnings for boards without a WiFi child node?

Since the wifi@1 child node is removed below, usdhc1 no longer has any child nodes for boards using the new IW61x module.

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi &usdhc1 { · line 385

Quoted 10 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -5

@@ -383,11 +382,6 @@ &usdhc1 {
 	non-removable;
 	keep-power-in-suspend;
 	status = "okay";
-
-	brcmf: wifi@1 {
-		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
-	};
 };

[Severity: High]
Does removing the Broadcom WiFi node from the shared SOM dtsi silently break WiFi support on downstream carrier boards?

Looking at arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts, it includes imx8mn-var-som.dtsi but was not updated to include a Wi-Fi variant include. Will the brcmfmac driver fail to bind to the device tree node for the gateway board, breaking DT-dependent configurations?

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=7

Stefano Radaelli

author

2026-07-03 08:46 UTC #12 lore raw

PATCH 8/15 arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

The VAR-SOM-MX8MN module does not provide an onboard USB connector.

The complete USB OTG description, including the Type-C role switch configuration, is already provided by the Symphony carrier board device tree. Remove the duplicate USB OTG node from the SOM dtsi to avoid describing the same hardware in two places.

Signed-off-by Stefano Radaelli <[email protected]>

---
 arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 6 ------
 1 file changed, 6 deletions(-)

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -6

index ff5f658b33de..0abc2d33e711 100644
@@ -365,12 +365,6 @@ &uart2 {
 	status = "okay";
 };
 
-&usbotg1 {
-	dr_mode = "otg";
-	usb-role-switch;
-	status = "okay";
-};
-
 &usdhc1 {
 	#address-cells = <1>;
 	#size-cells = <0>;

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #13 lore raw

PATCH 9/15 arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the FlexSPI controller on the VAR-SOM-MX8MN and add the corresponding pin multiplexing configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../boot/dts/freescale/imx8mn-var-som.dtsi      | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +17 -0

index 0abc2d33e711..259d9f36f8a3 100644
@@ -176,6 +176,12 @@ ethphy: ethernet-phy@4 {
 	};
 };
 
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";

@@ -456,6 +462,17 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120
 		>;
 	};
 
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c4
+			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x84
+			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x84
+			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x84
+			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x84
+			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x84
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3

Signature · 1 line

2.47.3

[email protected]

AI review

2026-07-03 08:56 UTC #14 lore raw

Re: [PATCH v1 09/15] arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The FlexSPI controller is enabled in the SOM `.dtsi` without a corresponding flash memory child…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The FlexSPI controller is enabled in the SOM .dtsi without a corresponding flash memory child node, preventing flash access and forcing pinmux usage on all carrier boards. --

commit c172727bc2bd192187db0f36d293f9c48809f6e4
Author: Stefano Radaelli <[email protected]>

arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface

This commit enables the FlexSPI controller on the VAR-SOM-MX8MN and configures the corresponding pin multiplexing.

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi ethphy: ethernet-phy@4 { · line 183

Quoted 13 lines

arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +5 -0

index 0abc2d33e7118..259d9f36f8a32 100644
@@ -176,6 +176,12 @@ ethphy: ethernet-phy@4 {
 	};
 };
 
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+};

[Severity: Medium]
Is this missing a child node for the flash device (e.g., flash@0)?

If the QSPI flash is physically located on the SOM, the kernel won't be able to probe or access it without the child node defined in this tree.

Alternatively, if the flash is intended to be located on the carrier board, does globally enabling the controller and its pinmux in the SOM's .dtsi prevent other carrier boards from repurposing these pins if they do not use FlexSPI?

[ ... ]

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=9

Stefano Radaelli

author

2026-07-03 08:46 UTC #15 lore raw

PATCH 10/15 arm64: dts: imx8mn-var-som-symphony: Add TPM2 support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add support for the TPM2 device on the VAR-SOM Symphony carrier board.

The ST33K TPM2 is connected over I2C, and A PCA6408 GPIO expander is used to control the reset signal required to release the TPM from reset.

Add the PCA6408 GPIO expander and the ST33K TPM2 device node.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../boot/dts/freescale/imx8mn-var-som-symphony.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +14 -0

index 53130b521b5b..7d016ed5e911 100644
@@ -160,6 +160,20 @@ typec1_dr_sw: endpoint {
 };
 
 &i2c3 {
+	pca6408: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	st33ktpm2xi2c: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+		label = "tpm";
+		reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>;
+	};
+
 	/* Capacitive touch controller */
 	ft5x06_ts: touchscreen@38 {
 		compatible = "edt,edt-ft5406";

Signature · 1 line

2.47.3

[email protected]

AI review

2026-07-03 09:00 UTC #16 lore raw

Re: [PATCH v1 10/15] arm64: dts: imx8mn-var-som-symphony: Add TPM2 support

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Incomplete hardware initialization for the TPM device due to missing `reset-gpios` driver…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete hardware initialization for the TPM device due to missing reset-gpios driver handling. --

Note: The format of this review is altered and does not include direct quotes of the patch code due to recitation restrictions. I am providing a free-form summary of the review findings instead.

commit 752fc746ff7ba94f6473f1446bfe64ae3aa4003c
Author: Stefano Radaelli <[email protected]>
Subject: arm64: dts: imx8mn-var-som-symphony: Add TPM2 support

This commit adds support for the ST33K TPM2 device on the VAR-SOM Symphony carrier board. It introduces device tree nodes for the ST33K TPM2 connected over I2C and a PCA6408 GPIO expander intended to control the TPM reset signal.

[Severity: Medium]
In the newly added st33ktpm2xi2c node, there is a reset-gpios property referencing pin 4 of the pca6408 GPIO expander. Will this actually bring the TPM out of reset during boot?

Looking at the tpm_tis_i2c driver, it does not appear to contain code to request and drive the reset-gpios property.

Furthermore, the pca6408 node does not declare a gpio-hog to statically configure the pin state. This implies the GPIO expander pin will default to a high-impedance input when the kernel boots.

Unless the board has a hardware pull-up resistor or the bootloader specifically configures this pin as an active output before handing off to Linux, won't the TPM remain held in reset and fail to probe?

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=10

Stefano Radaelli

author

2026-07-03 08:46 UTC #17 lore raw

PATCH 11/15 arm64: dts: imx8mn-var-som-symphony: Enable I2C4

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../dts/freescale/imx8mn-var-som-symphony.dts | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +24 -0

index 7d016ed5e911..4898018f030c 100644
@@ -195,6 +195,16 @@ rtc@68 {
 	};
 };
 
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
 /* Header */
 &uart1 {
 	pinctrl-names = "default";

@@ -262,6 +272,20 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
 		>;
 	};
 
+	pinctrl_i2c4_gpio: i2c4gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20	0x1c3
+			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0x1c3
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
+			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #18 lore raw

PATCH 12/15 arm64: dts: imx8mn-var-som-symphony: add wakeup sources

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources.

Signed-off-by Stefano Radaelli <[email protected]>

---
 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +4 -0

index 4898018f030c..c98dca8e7889 100644
@@ -40,18 +40,21 @@ key-back {
 			label = "Back";
 			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BACK>;
+			wakeup-source;
 		};
 
 		key-home {
 			label = "Home";
 			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
+			wakeup-source;
 		};
 
 		key-menu {
 			label = "Menu";
 			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_MENU>;
+			wakeup-source;
 		};
 	};

@@ -187,6 +190,7 @@ ft5x06_ts: touchscreen@38 {
 		touchscreen-size-y = <480>;
 		touchscreen-inverted-x;
 		touchscreen-inverted-y;
+		wakeup-source;
 	};
 
 	rtc@68 {

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #19 lore raw

PATCH 13/15 arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Keep the RGB_SEL line driven low on the Symphony carrier board.

This avoids leaving the line floating and ensures the board remains in the expected display configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +8 -0

index c98dca8e7889..ddd4651b35d7 100644
@@ -168,6 +168,14 @@ pca6408: gpio@21 {
 		reg = <0x21>;
 		gpio-controller;
 		#gpio-cells = <2>;
+
+		/* RGB_SEL */
+		lvds-brg-enable-hog {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "rgb_sel";
+		};
 	};
 
 	st33ktpm2xi2c: tpm@2e {

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #20 lore raw

PATCH 14/15 arm64: dts: imx8mn-var-som-symphony: enable PWM1

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
 .../boot/dts/freescale/imx8mn-var-som-symphony.dts   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +12 -0

index ddd4651b35d7..2afb5b438b68 100644
@@ -217,6 +217,12 @@ &i2c4 {
 	status = "okay";
 };
 
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
 /* Header */
 &uart1 {
 	pinctrl-names = "default";

@@ -310,6 +316,12 @@ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
 		>;
 	};
 
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT	0x06
+		>;
+	};
+
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x41

Signature · 1 line

2.47.3

Stefano Radaelli

author

2026-07-03 08:46 UTC #21 lore raw

PATCH 15/15 arm64: dts: imx8mn-var-som-symphony: Disable internal RTC

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Disable the internal SNVS RTC on the Symphony carrier board and use the external DS1337 RTC instead.

Signed-off-by Stefano Radaelli <[email protected]>

---
 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +4 -0

index 2afb5b438b68..364127257309 100644
@@ -223,6 +223,10 @@ &pwm1 {
 	status = "okay";
 };
 
+&snvs_rtc {
+	status = "disabled";
+};
+
 /* Header */
 &uart1 {
 	pinctrl-names = "default";

Signature · 1 line

2.47.3