Add USB3.1 support for Agilex5
Subsystems (3)
v5 cover Add USB3.1 support for Agilex5
Agilex5 integrates a Synopsys DesignWare USB3 controller via a SoC-specific wrapper that requires dedicated clock, reset, PHY, and optional SMMU integration. The USB DMA path on the interconnect is limited to a 40-bit address width.
This series adds a device tree binding for the Agilex5 DWC3 controller and introduces the corresponding USB3.1 node in the Agilex5 SoC and SoCDK device trees. The controller is placed under a simple-bus with a 40-bit dma-ranges window so the DMA/IOMMU stack respects the interconnect address width when SMMU is enabled. As the SoCDK only exposes the USB3.1 interface, the unused USB0 node is removed.
On this SoC the DWC3 "ref" and "suspend" inputs share the same hardware clock source, so both clock phandles use the already published AGILEX5_USB31_SUSPEND_CLK ID (no new clock binding ID).
Finally, the Agilex5 compatible string is added to the dwc3 generic platform driver so the controller can probe through that glue driver.
Merging:
- Patches 1 and 4 (dt-bindings + dwc3-generic-plat): USB tree
- Patches 2 and 3 (arm64 dts): SoC / arm64 dts tree (or taken with the USB series if preferred, with an appropriate Ack)
---
changelog:v4->v5:
* Binding: replace unevaluatedProperties: false with additionalProperties:
false, and allow only the extra DWC3 properties used on this SoC via "foo: true" (dr_mode, maximum-speed, snps,dis_u2_susphy_quirk, snps,dis_u3_susphy_quirk). Requested by Conor Dooley.
v4 patch link:
https://lore.kernel.org/all/[email protected]/
v3->v4:
* Drop dt-bindings/clock and clk driver patches; do not extend the published Agilex5 clock binding. Reuse AGILEX5_USB31_SUSPEND_CLK for both "ref" and "suspend" clock inputs.
* Fix usb31_bus dma-ranges cell layout (sashiko comment): use #address-cells = <2> and a Stingray-style 40-bit dma-ranges window instead of a 32-bit child address space with a truncated 1 TiB size.
* Update altr,agilex5-dwc3.yaml per review: drop obvious reg/resets descriptions, order clock-names as bus_early/ref/suspend (matching snps,dwc3.yaml), and rename reset-names to core/ecc.
* Limit the series to USB binding, DTS, and dwc3-generic-plat (no clk subsystem patches in the same series).
v3 patch link:
https://lore.kernel.org/all/[email protected]/
v2->v3:
* Add the missing USB3.1 reference clock ID and register usb31_ref_clk as a fixed-factor clock in the Agilex5 clock driver.
* Drop dma_addressable_bits core/glue changes; describe the 40-bit DMA limit in DT with dma-ranges instead.
* Wrap the USB3.1 node in a simple-bus with a 40-bit dma-ranges window.
* Keep Agilex5 support in dwc3-generic-plat as a compatible match only (no platform-specific DMA mask override).
v2 patch link:
https://lore.kernel.org/all/[email protected]/
v1->v2:
* Update new binding name to match compatible.
* Update binding to use single node instead of parent child node structure.
* Update binding according to comments from maintainer.
* Split USB3 and USB2 changes in dts into separate commits.
* Update to use flattened model and use dwc3-generic-plat driver instead of dwc3-of-simple driver.
* Add dma_addressable_bits as a dwc3 property which is set by the glue driver which is used to configure the dma mask in the core driver.
v1 patch link:
https://lore.kernel.org/all/[email protected]/
---
Adrian Ng Ho Yin (4):
dt-bindings: usb: add Altera Agilex5 DWC3 controller
arm64: dts: intel: agilex5: add USB3.1 controller node
arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK
usb: dwc3: add Altera Agilex5 support to generic platform driver
.../bindings/usb/altr,agilex5-dwc3.yaml | 108 ++++++++++++++++++ .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 ++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 4 +- drivers/usb/dwc3/dwc3-generic-plat.c | 1 + 4 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
Signature · 1 line
2.49.GIT
PATCH v5 1/4 dt-bindings: usb: add Altera Agilex5 DWC3 controller
Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3 USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets, PHYs, and optional IOMMU support.
Clock names follow the snps,dwc3.yaml example order (bus_early, ref, suspend). Reset names use core/ecc. On this SoC ref and suspend are the same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.
--- .../bindings/usb/altr,agilex5-dwc3.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +108 -0
@@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Agilex5 DWC3 USB SoC Controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +description: + The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3) + controller that supports host, device and DRD modes. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: altr,agilex5-dwc3 + + reg: + maxItems: 1 + + clocks: + items: + - description: Master/Core bus clock + - description: Controller reference clock + - description: Controller suspend clock + + clock-names: + items: + - const: bus_early + - const: ref + - const: suspend + + interrupts: + maxItems: 1 + + phys: + minItems: 2 + maxItems: 2 + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + iommus: + maxItems: 1 + + resets: + items: + - description: DWC3 core reset + - description: DWC3 ECC reset + + reset-names: + items: + - const: core + - const: ecc + + dr_mode: true + + maximum-speed: true + + snps,dis_u2_susphy_quirk: true + + snps,dis_u3_susphy_quirk: true + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/altr,rst-mgr-s10.h> + #include <dt-bindings/clock/intel,agilex5-clkmgr.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + usb@11000000 { + compatible = "altr,agilex5-dwc3"; + reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>; + clock-names = "bus_early", "ref", "suspend"; + phys = <&usbphy0>, <&usbphy1>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "core", "ecc"; + iommus = <&smmu 7>; + }; + };
Signature · 1 line
2.49.GIT
[email protected]
AI reviewRe: [PATCH v5 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The schema incorrectly uses `additionalProperties: false` instead of `unevaluatedProperties…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The schema incorrectly uses additionalProperties: false instead of unevaluatedProperties: false, which negates inherited schemas and forces redundant property declarations. --
commit 9d62a972209f1de97f540bff2202c5f7fd9c1a48
Author: Adrian Ng Ho Yin <[email protected]>
dt-bindings: usb: add Altera Agilex5 DWC3 controller
Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3 USB controller, covering clocks, resets, PHYs, and optional IOMMU support.
Quoted 5 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +0
-0
[ ... ]
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml line 69
Quoted 12 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +12
-0+ reset-names: + items: + - const: core + - const: ecc + + dr_mode: true + + maximum-speed: true + + snps,dis_u2_susphy_quirk: true + + snps,dis_u3_susphy_quirk: true
[Severity: Medium]
Are these property declarations necessary?
These dummy redeclarations appear to be a workaround for the additionalProperties restriction below. Once unevaluatedProperties: false is used instead, these can be safely removed as they will be properly inherited from the common schema.
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml line 82
Quoted 13 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +13
-0+ +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - reset-names + +additionalProperties: false
[Severity: Medium]
Does this incorrectly reject standard properties inherited from snps,dwc3-common.yaml?
Using additionalProperties: false instead of unevaluatedProperties: false strictly restricts properties to only those defined in this file. This breaks schema inheritance, meaning any standard DWC3 properties not explicitly redefined here will cause dt_binding_check to fail.
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
Re: [PATCH v5 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller
In reply to Adrian Ng Ho YinQuoted 79 lines · Adrian Ng Ho Yin
Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3 USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets, PHYs, and optional IOMMU support.
Clock names follow the snps,dwc3.yaml example order (
bus_early, ref, suspend). Reset names use core/ecc. On this SoC ref and suspend are the same hardware source, so the example reusesAGILEX5_USB31_SUSPEND_CLK.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/altr,agilex5-dwc3.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yamlDocumentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +59
-0@@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Agilex5 DWC3 USB SoC Controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +description: + The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3) + controller that supports host, device and DRD modes. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: altr,agilex5-dwc3 + + reg: + maxItems: 1 + + clocks: + items: + - description: Master/Core bus clock + - description: Controller reference clock + - description: Controller suspend clock + + clock-names: + items: + - const: bus_early + - const: ref + - const: suspend + + interrupts: + maxItems: 1 + + phys: + minItems: 2 + maxItems: 2 + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + iommus: + maxItems: 1 + + resets: + items: + - description: DWC3 core reset + - description: DWC3 ECC reset + + reset-names: + items:
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml line 69
Quoted 10 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +10
-0+ - const: core + - const: ecc + + dr_mode: true + + maximum-speed: true + + snps,dis_u2_susphy_quirk: true + + snps,dis_u3_susphy_quirk: true
You add these two as possible but not required properties. Why is that? Does the agilex5 have some instances of the IP where these are needed and not others?
Cheers,
Conor.
Quoted 42 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +39
-0+ +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/altr,rst-mgr-s10.h> + #include <dt-bindings/clock/intel,agilex5-clkmgr.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + usb@11000000 { + compatible = "altr,agilex5-dwc3"; + reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>; + clock-names = "bus_early", "ref", "suspend"; + phys = <&usbphy0>, <&usbphy1>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "core", "ecc"; + iommus = <&smmu 7>; + }; + };Signature · 1 line
2.49.GIT
Re: [PATCH v5 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller
Quoted 85 lines · Conor Dooley
Quoted 84 lines · Adrian Ng Ho Yin
Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3 USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets, PHYs, and optional IOMMU support.
Clock names follow the snps,dwc3.yaml example order (
bus_early, ref, suspend). Reset names use core/ecc. On this SoC ref and suspend are the same hardware source, so the example reusesAGILEX5_USB31_SUSPEND_CLK.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/altr,agilex5-dwc3.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+)create mode 100644
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yamlDocumentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +64
-0@@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Agilex5 DWC3 USB SoC Controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +description: + The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3) + controller that supports host, device and DRD modes. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: altr,agilex5-dwc3 + + reg: + maxItems: 1 + + clocks: + items: + - description: Master/Core bus clock + - description: Controller reference clock + - description: Controller suspend clock + + clock-names: + items: + - const: bus_early + - const: ref + - const: suspend + + interrupts: + maxItems: 1 + + phys: + minItems: 2 + maxItems: 2 + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + iommus: + maxItems: 1 + + resets: + items: + - description: DWC3 core reset + - description: DWC3 ECC reset + + reset-names: + items: + - const: core + - const: ecc + + dr_mode: true +
Quoted 8 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml line 69
Quoted 5 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +5
-0+ maximum-speed: true + + snps,dis_u2_susphy_quirk: true + + snps,dis_u3_susphy_quirk: trueYou add these two as possible but not required properties. Why is that? Does the agilex5 have some instances of the IP where these are needed and not others?
Hi Conor,
There is only one DWC3 instance for Agilex 5, and these 2 quirks are used on that node. I left them as optional because i followed how snps,dwc3-common.yaml models them:
boolean flags, not required properties. I listed them as "foo: true" so additionalProperties:
false would still accept the properties the SoC DT uses.
Thank You
Adrian
Quoted 46 lines
Cheers,
Conor.Quoted 42 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +39
-0+ +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/altr,rst-mgr-s10.h> + #include <dt-bindings/clock/intel,agilex5-clkmgr.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + usb@11000000 { + compatible = "altr,agilex5-dwc3"; + reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>; + clock-names = "bus_early", "ref", "suspend"; + phys = <&usbphy0>, <&usbphy1>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "core", "ecc"; + iommus = <&smmu 7>; + }; + };Signature · 1 line
2.49.GIT
Re: [PATCH v5 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller
Quoted 96 lines · ADRIAN HO YIN
Quoted 85 lines · Conor Dooley
Quoted 84 lines · Adrian Ng Ho Yin
Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3 USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets, PHYs, and optional IOMMU support.
Clock names follow the snps,dwc3.yaml example order (
bus_early, ref, suspend). Reset names use core/ecc. On this SoC ref and suspend are the same hardware source, so the example reusesAGILEX5_USB31_SUSPEND_CLK.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/altr,agilex5-dwc3.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+)create mode 100644
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yamlDocumentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +64
-0@@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Agilex5 DWC3 USB SoC Controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +description: + The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3) + controller that supports host, device and DRD modes. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: altr,agilex5-dwc3 + + reg: + maxItems: 1 + + clocks: + items: + - description: Master/Core bus clock + - description: Controller reference clock + - description: Controller suspend clock + + clock-names: + items: + - const: bus_early + - const: ref + - const: suspend + + interrupts: + maxItems: 1 + + phys: + minItems: 2 + maxItems: 2 + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + iommus: + maxItems: 1 + + resets: + items: + - description: DWC3 core reset + - description: DWC3 ECC reset + + reset-names: + items: + - const: core + - const: ecc + + dr_mode: true +Quoted 8 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml line 69
Quoted 5 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +5
-0+ maximum-speed: true + + snps,dis_u2_susphy_quirk: true + + snps,dis_u3_susphy_quirk: trueYou add these two as possible but not required properties. Why is that? Does the agilex5 have some instances of the IP where these are needed and not others?
Quoted 4 lines
Hi Conor,
There is only one DWC3 instance for Agilex 5, and these 2 quirks are used on that node.
Then they should be mandatory.
pw-bot: changes-requested
Quoted 3 lines
I left them as optional because i followed how snps,dwc3-common.yaml models them:
boolean flags, not required properties.
That file cannot make them mandatory since they might not apply to all the various devices that use them.
Thanks,
Conor.
Quoted 53 lines
I listed them as "foo: true" so additionalProperties:
false would still accept the properties the SoC DT uses.Thank You
AdrianQuoted 46 lines
Cheers,
Conor.Quoted 42 lines
Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file +39
-0+ +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/altr,rst-mgr-s10.h> + #include <dt-bindings/clock/intel,agilex5-clkmgr.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + usb@11000000 { + compatible = "altr,agilex5-dwc3"; + reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>; + clock-names = "bus_early", "ref", "suspend"; + phys = <&usbphy0>, <&usbphy1>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "core", "ecc"; + iommus = <&smmu 7>; + }; + };Signature · 1 line
2.49.GIT
PATCH v5 2/4 arm64: dts: intel: agilex5: add USB3.1 controller node
In reply to Adrian Ng Ho YinAdd a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC. Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells = 2) to match the USB DMA address width of the interconnect. Enable it in host mode on the SoCDK board.
ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the same hardware clock source on this SoC.
--- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 +++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 5 +++ 2 files changed, 40 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +35 -0
@@ -493,6 +493,41 @@ usb0: usb@10b00000 { status = "disabled"; }; + usb31_bus: usb-bus@11000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x11000000 0x0 0x100000>; + /* + * USB interconnect DMA is limited to 40-bit addresses + * (1 TiB window from 0). + */ + dma-ranges = <0x0 0x0 0x0 0x100 0x0>; + + usb31: usb@0 { + compatible = "altr,agilex5-dwc3"; + reg = <0x0 0x0 0x0 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + /* + * ref and suspend share the same hardware + * source; reuse the published suspend clock ID. + */ + clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>; + clock-names = "bus_early", "ref", "suspend"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "core", "ecc"; + iommus = <&smmu 7>; + phys = <&usbphy0>, <&usbphy0>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + status = "disabled"; + }; + }; + watchdog0: watchdog@10d00200 { compatible = "snps,dw-wdt"; reg = <0x10d00200 0x100>;
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +5 -0
@@ -109,6 +109,11 @@ &usb0 { disable-over-current; }; +&usb31 { + dr_mode = "host"; + status = "okay"; +}; + &watchdog0 { status = "okay"; };
Signature · 1 line
2.49.GIT
[email protected]
AI reviewRe: [PATCH v5 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] The `dma-ranges` property attempts to map a 40-bit (1 TiB) address window into a strictly 32-bit…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The dma-ranges property attempts to map a 40-bit (1 TiB) address window into a strictly 32-bit parent bus, which will break DMA addressing above 4 GiB. --
commit 37652f3fe88e1fdb5283901dda73de167a957be5
Author: Adrian Ng Ho Yin <[email protected]>
arm64: dts: intel: agilex5: add USB3.1 controller node
This commit adds a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC. It places the node under a simple-bus with a 40-bit dma-ranges window to match the interconnect's USB DMA address width.
Quoted 4 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0
-0
[ ... ]
Quoted 4 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0
-0@@ -493,6 +493,41 @@ usb0: usb@10b00000 { status = "disabled"; };
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi usb0: usb@10b00000 { · line 505
Quoted 10 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +10
-0+ usb31_bus: usb-bus@11000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x11000000 0x0 0x100000>; + /* + * USB interconnect DMA is limited to 40-bit addresses + * (1 TiB window from 0). + */ + dma-ranges = <0x0 0x0 0x0 0x100 0x0>;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[Severity: High]
Does this 1 TiB DMA mapping conflict with the 32-bit parent bus?
The usb31_bus node defines a 1 TiB DMA window (0x100 0x0 size) mapped into its parent node starting at address 0x0. However, the parent node appears to define #address-cells = <1>, representing a strictly 32-bit (4 GiB) address space.
Since a 1 TiB mapping cannot logically fit within a 32-bit parent address space, will this truncate addresses above 4 GiB during DMA translation in of_translate_dma_address(), leading to DMA mapping errors or IOMMU faults when the USB 3.1 controller performs a DMA transaction to memory above the 4 GiB physical address boundary?
Quoted 3 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +3
-0+ + usb31: usb@0 { + compatible = "altr,agilex5-dwc3";
[ ... ]
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
PATCH v5 3/4 arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK
In reply to Adrian Ng Ho YinThe Agilex5 SoCDK daughter card only provides a USB3.1 interface (USB1). USB0 is not connected or used on this board. Remove the USB0 node to avoid unnecessary initialization and potential resource conflicts.
--- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 5 ----- 1 file changed, 5 deletions(-)
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +0 -5
@@ -104,11 +104,6 @@ &uart0 { status = "okay"; }; -&usb0 { - status = "okay"; - disable-over-current; -}; - &usb31 { dr_mode = "host"; status = "okay";
Signature · 1 line
2.49.GIT
PATCH v5 4/4 usb: dwc3: add Altera Agilex5 support to generic platform driver
In reply to Adrian Ng Ho YinAdd the "altr,agilex5-dwc3" compatible string to dwc3-generic-plat so the Agilex5 USB3.1 DWC3 controller can probe through the generic DWC3 platform glue.
--- drivers/usb/dwc3/dwc3-generic-plat.c | 1 + 1 file changed, 1 insertion(+)
drivers/usb/dwc3/dwc3-generic-plat.c +1 -0
@@ -232,6 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { };static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible ="altr,agilex5-dwc3" , }, { .compatible ="spacemit,k1-dwc3" , &spacemit_k1_dwc3}, { .compatible ="spacemit,k3-dwc3" , }, { .compatible ="fsl,ls1028a-dwc3" , &fsl_ls1028_dwc3},
Signature · 1 line
2.49.GIT