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ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC support

PATCH Superseded Jacky Huang 3 participants 8 messages Oct 29

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Device tree bindings Arm/Aspeed machine support

v1 of 2 Superseded Latest is v2 →

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Jacky Huang

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#0 lore raw

cover ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC support

This series adds support for the NVIDIA MGX Vera C2 BMC, which is based on the ASPEED AST2600.

The board declares its boot-flash properties explicitly, allowing the same DTS to work with aspeed-g6.dtsi both before and after the pending flash-node cleanup [1].

The board DTS passes scripts/dtc/dt-check-style --mode=strict.

[1] https://lore.kernel.org/all/[email protected]/

Jacky Huang (2):
dt-bindings: arm: aspeed: Add NVIDIA MGX Vera C2 BMC
ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

 .../bindings/arm/aspeed/aspeed.yaml           |    1 +
 arch/arm/boot/dts/aspeed/Makefile             |    1 +
 .../aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts    | 1321 +++++++++++++++++
 3 files changed, 1323 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts

base-commit: ba3f2c447203166c640e40dc8e9b4b91fc613aa5

Signature · 1 line
2.43.0
author
#1 lore raw

PATCH 1/2 dt-bindings: arm: aspeed: Add NVIDIA MGX Vera C2 BMC

Add the board compatible for the NVIDIA MGX Vera C2 BMC, which is based on the ASPEED AST2600 SoC.

Signed-off-by Jacky Huang <[email protected]>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +1 -0
index b7e70868e..92127d7c4 100644
@@ -115,6 +115,7 @@ properties:
               - jabil,rbp-bmc
               - nvidia,gb200nvl-bmc
               - nvidia,msx4-bmc
+              - nvidia,vr-c2-bmc
               - qcom,dc-scm-v1-bmc
               - quanta,s6q-bmc
               - ufispace,ncplite-bmc
Signature · 1 line
2.43.0
author
#3 lore raw

PATCH 2/2 ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

In reply to Jacky Huang

Add support for the NVIDIA MGX Vera C2 BMC based on the ASPEED AST2600 SoC.

Signed-off-by Jacky Huang <[email protected]>
---
 arch/arm/boot/dts/aspeed/Makefile             |    1 +
 .../aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts    | 1321 +++++++++++++++++
 2 files changed, 1322 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts
arch/arm/boot/dts/aspeed/Makefile +1 -0
index 6874b621d..e5c44d423 100644
@@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-microsoft-olympus.dtb \
 	aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
 	aspeed-bmc-nvidia-msx4-bmc.dtb \
+	aspeed-bmc-nvidia-vr-c2-bmc.dtb \
 	aspeed-bmc-opp-lanyang.dtb \
 	aspeed-bmc-opp-mowgli.dtb \
 	aspeed-bmc-opp-nicole.dtb \
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +1321 -0

1,321 lines not on this page · raw message

Signature · 1 line
2.43.0
AI review
#4 lore raw

Re: [PATCH 2/2] ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] ARM: dts: aspeed: vr-c2: missing i2c-mux-idle-disconnect on i2c4 muxes - [Medium] ARM: dts…

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] ARM: dts: aspeed: vr-c2: missing i2c-mux-idle-disconnect on i2c4 muxes
- [Medium] ARM: dts: aspeed: duplicate gpio-line-names in vr-c2-bmc
--

commit a1ef1efffcf5e5e21a0a7edd3526a31cbe156f2d
Author: Jacky Huang <[email protected]>

ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

This commit adds the device tree for the NVIDIA MGX Vera C2 BMC platform based on the ASPEED AST2600 SoC.

Quoted 6 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +0 -0
new file mode 100644
index 0000000000000..7e8ae8afea088
@@ -0,0 +1,1321 @@

[ ... ]

Quoted 2 lines

+&gpio0 {

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +1 -0
+	gpio-line-names =

[ ... ]

Quoted 7 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +7 -0
+	/*V0-V7*/
+	"AP_EROT_REQ-O",
+	"EROT_AP_GNT-I",
+	"",
+	"",
+	"PCB_TEMP_ALERT-I",
+	"", "", "",

[ ... ]

Quoted 14 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +14 -0
+};
+
+&gpio1 {
+	gpio-line-names =
+	/*A0-A7*/
+	"", "", "", "", "", "", "", "",
+
+	/*B0-B7*/
+	"", "", "", "",
+	"AP_EROT_REQ-O",
+	"EROT_AP_GNT-I",
+	"IO_EXPANDER_INT_L-I",
+	"",
+

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts line 465

Quoted 10 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +10 -0
+	/*C0-C7*/
+	"", "", "", "", "", "", "", "",
+
+	/*D0-D7*/
+	"", "", "", "", "", "", "",
+	"I2C_SSIF_ALERT_L-I",
+
+	/*E0-E7*/
+	"", "", "", "", "", "", "", "";
+};

[Severity: Medium]
Are "AP_EROT_REQ-O" and "EROT_AP_GNT-I" intentionally defined on both &gpio0 (pins V0-V1) and &gpio1 (pins B4-B5)?

Because both AST2600 GPIO controllers are active at the same time and &gpio0 probes before &gpio1, name-based GPIO lookups via gpio_name_to_desc() or libgpiod will always resolve to &gpio0 and shadow the lines on &gpio1.

Similarly, further down in this file, the pca6408@20 expanders on &i2c_mcio_c0_south0 and &i2c_mcio_c1_south0 define identical "GPU1_*" gpio-line-names, and the pca6408@20 expanders on &i2c_mcio_c0c1_north3 and &i2c_mcio_c0c1_north6 define identical "E1S_*" gpio-line-names. Should those line names be disambiguated (for example with C1/C2 prefixes) so that consumers can address both instances by name?

[ ... ]

Quoted 17 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +17 -0
+/* MCIO expansion muxes */
+&i2c4 {
+	multi-master;
+
+	status = "okay";
+
+	mctp@18 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x18 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		vdd-supply = <&standby_power_regulator>;

[ ... ]

Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +8 -0
+	};
+
+	i2c-mux@71 {
+		compatible = "nxp,pca9548";
+		reg = <0x71>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		vdd-supply = <&standby_power_regulator>;

[ ... ]

Quoted 8 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +8 -0
+	};
+
+	i2c-mux@75 {
+		compatible = "nxp,pca9548";
+		reg = <0x75>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		vdd-supply = <&standby_power_regulator>;

[ ... ]

Quoted 2 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +2 -0
+	};
+};

[ ... ]

Quoted 94 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +94 -0
+/* GPU1 GPIO expander (C1) */
+&i2c_mcio_c0_south0 {
+	/* GPU 1, Expander @0x20 */
+	pca6408@20 {
+		compatible = "nxp,pca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&standby_power_regulator>;
+		gpio-line-names =
+		"GPU1_GLOBAL_WP-O",
+		"GPU1_OOB_RST_N-O",
+		"GPU1_OOB_RECOVERY-O",
+		"GPU1_MCU_RECOVERY_N-O",
+		"GPU1_MCU_RST_N-O",
+		"GPU1_MCU_BYPASS_N-O",
+		"GPU1_SMBUS_FRU_EEPROM_WP-O",
+		"";
+	};
+};
+
+/* GPU0 GPIO expander */
+&i2c_mcio_c0_south2 {
+	/* GPU 0, Expander @0x20 */
+	pca6408@20 {
+		compatible = "nxp,pca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&standby_power_regulator>;
+		gpio-line-names =
+		"GPU0_GLOBAL_WP-O",
+		"GPU0_OOB_RST_N-O",
+		"GPU0_OOB_RECOVERY-O",
+		"GPU0_MCU_RECOVERY_N-O",
+		"GPU0_MCU_RST_N-O",
+		"GPU0_MCU_BYPASS_N-O",
+		"GPU0_SMBUS_FRU_EEPROM_WP-O",
+		"";
+	};
+};
+
+/* E1.S backplane GPIO expander (C1) */
+&i2c_mcio_c0c1_north3 {
+	/* E1S Backplane, Expander @0x20 */
+	pca6408@20 {
+		compatible = "nxp,pca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&standby_power_regulator>;
+		gpio-line-names =
+		"E1S_MCU_RESET_L-O",
+		"E1S_MCU_RECOVERY_L-O",
+		"",
+		"",
+		"",
+		"",
+		"E1S_LOWER_PERST-O",
+		"E1S_UPPER_PERST-O";
+	};
+};
+
+/* E1.S backplane GPIO expander (C2) */
+&i2c_mcio_c0c1_north6 {
+	/* E1S Backplane, Expander @0x20 */
+	pca6408@20 {
+		compatible = "nxp,pca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&standby_power_regulator>;
+		gpio-line-names =
+		"E1S_MCU_RESET_L-O",
+		"E1S_MCU_RECOVERY_L-O",
+		"",
+		"",
+		"",
+		"",
+		"E1S_LOWER_PERST-O",
+		"E1S_UPPER_PERST-O";
+	};
+};
+
+/* GPU1 GPIO expander (C2) */
+&i2c_mcio_c1_south0 {
+	/* GPU 1, Expander @0x20 */
+	pca6408@20 {
+		compatible = "nxp,pca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&standby_power_regulator>;
+		gpio-line-names =

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts line 1257

Quoted 10 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +10 -0
+		"GPU1_GLOBAL_WP-O",
+		"GPU1_OOB_RST_N-O",
+		"GPU1_OOB_RECOVERY-O",
+		"GPU1_MCU_RECOVERY_N-O",
+		"GPU1_MCU_RST_N-O",
+		"GPU1_MCU_BYPASS_N-O",
+		"GPU1_SMBUS_FRU_EEPROM_WP-O",
+		"";
+	};
+};

[Severity: High]
Should i2c-mux@70, i2c-mux@71, and i2c-mux@75 on &i2c4 include the i2c-mux-idle-disconnect property (like the pca9546 muxes on &i2c6 and &i2c9)?

In pca954x_probe() and pca954x_deselect_mux(), when neither idle-state nor i2c-mux-idle-disconnect is specified, data->idle_state defaults to MUX_IDLE_AS_IS and each PCA9548 leaves its last selected downstream channel connected to &i2c4 after transfers complete.

Because five pca6408@20 GPIO expanders sit behind these three switches on &i2c4 (&i2c_mcio_c0_south0, &i2c_mcio_c0_south2, &i2c_mcio_c0c1_north3, &i2c_mcio_c0c1_north6, and &i2c_mcio_c1_south0) at the same slave address 0x20, leaving channels connected across the three switches bridges multiple pca6408@20 devices onto &i2c4 simultaneously. Wouldn't this cause I2C address contention at 0x20, false-positive probing of unpopulated C1/C2 expanders, and cross-writes to the wrong GPU or E1.S reset/recovery/PERST GPIOs?

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
author
#5 lore raw

Re: [PATCH 2/2] ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

Quoted 6 lines · On Thu, Oct 29, 2026 at 05:13:56AM +0000, [email protected] wrote:

Similarly, further down in this file, the pca6408@20 expanders on &i2c_mcio_c0_south0 and &i2c_mcio_c1_south0 define identical "GPU1_*" gpio-line-names, and the pca6408@20 expanders on &i2c_mcio_c0c1_north3 and &i2c_mcio_c0c1_north6 define identical "E1S_*" gpio-line-names. Should those line names be disambiguated (for example with C1/C2 prefixes) so that consumers can address both instances by name?

These are alternative placements for different configurations. I'll drop the C1 ones in v2, so the DTS only describes the C2 board and the names become unique.

[ ... ]

Quoted 3 lines

[Severity: High]
Should i2c-mux@70, i2c-mux@71, and i2c-mux@75 on &i2c4 include the i2c-mux-idle-disconnect property (like the pca9546 muxes on &i2c6 and &i2c9)?

The muxes on i2c4 intentionally don't use i2c-mux-idle-disconnect. Each of them carries MCTP-over-I2C channels, and MCTP endpoints send their responses back to the BMC as separate transfers through the selected channel. With idle-disconnect the channel is closed right after the request, so responses can get lost. So I'd like to keep them as is.

Thanks,
Jacky

#6 lore raw

Re: [PATCH 2/2] ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

In reply to Jacky Huang

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts line 50

Quoted 2 lines · Jacky Huang
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +2 -0
+	chosen {
+		bootargs = "console=tty0 console=ttyS4,115200n8 earlycon";

Drop bootargs. Console (and baudrate) goes to stdout-path. earlycon is for debugging, not mainline wide-usage.

Quoted 18 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +18 -0
+		stdout-path = &uart5;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		fault-led {
+			gpios = <&exp7 12 GPIO_ACTIVE_LOW>;
+		};
+
+		power-led {
+			gpios = <&exp7 8 GPIO_ACTIVE_LOW>;
+		};
+
+		uid-led {
+			gpios = <&exp7 10 GPIO_ACTIVE_LOW>;
+		};
+	};

...

Quoted 10 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +10 -0
+				device@1 {
+					compatible = "usb955,cf11";
+					reg = <1>;
+					#address-cells = <2>;
+					#size-cells = <0>;
+
+					cp2112: interface@1 {
+						compatible = "usbif955,cf11.config1.1";
+						reg = <1 1>;
+						#gpio-cells = <2>;

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts line 166

Quoted 10 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +10 -0
+						gpio-controller;
+						#interrupt-cells = <2>;
+						interrupt-controller;
+
+						i2c {
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							/* CPU0 IROT/thermal/SOCAMM/JTAG */
+							pca9555@50 {

Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
If you cannot find a name matching your device, please check in kernel sources for similar cases or you can grow the spec (via pull request to DT spec repo).

Quoted 2 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +2 -0
+								compatible = "nxp,pca9555";
+								reg = <0x50>;

...

Quoted 17 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +17 -0
+
+/* Board 0 management bus 1: GPIO expanders + HPM MCU MCTP */
+&i2c1 {
+	mctp-controller;
+	multi-master;
+
+	status = "okay";
+
+	/* MCTP for HPM MCU */
+	mctp@18 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x18 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+
+	/* Board 0 management bus 1 GPIO expander 0 */
+	pca9555@20 {
+		compatible = "nxp,pca9555";

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts line 502

Quoted 10 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +10 -0
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		vcc-supply = <&standby_power_regulator>;
+		gpio-line-names =
+		"B0_M1_MCU_RESET_L-O",

Messed indentation.

Are you sure you run dt-check-style here?

Best regards,
Krzysztof

author
#7 lore raw

Re: [PATCH 2/2] ARM: dts: aspeed: Add NVIDIA MGX Vera C2 BMC

Hi Krzysztof,

Thanks for taking the time to review this.

Quoted 6 lines · Krzysztof Kozlowski

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts line 50

Quoted 2 lines · Jacky Huang
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +2 -0
+	chosen {
+		bootargs = "console=tty0 console=ttyS4,115200n8 earlycon";

Drop bootargs. Console (and baudrate) goes to stdout-path. earlycon is for debugging, not mainline wide-usage.

Will drop bootargs and use stdout-path = "serial4:115200n8" in v2.

[ ... ]

Quoted 9 lines

arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts line 166

Quoted 2 lines
arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-c2-bmc.dts new file +2 -0
+							/* CPU0 IROT/thermal/SOCAMM/JTAG */
+							pca9555@50 {

Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
If you cannot find a name matching your device, please check in kernel sources for similar cases or you can grow the spec (via pull request to DT spec repo).

Will rename the GPIO expanders to gpio@ and the fan controllers to fan-controller@ in v2.

[ ... ]

Quoted 6 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+		gpio-line-names =
+		"B0_M1_MCU_RESET_L-O",

Messed indentation.

Are you sure you run dt-check-style here?

Will fix the indentation of all gpio-line-names in v2. Thanks for pointing it out. I did run it and it passed, but it looks like the continuation alignment check only considers values that start on the same line as the '=', so this case wasn't caught.

Best regards,
Jacky