Skip to contentSkip to conversation

MIPS: io: prevent compiler reordering on the default writeX() implementation

PATCH In review Sinan Kaya 2 participants 4 messages Apr 13, 2018

Subsystems (2)
Arm Qualcomm mailing list MIPS
lore
Share & tools
lore

Sinan Kaya

author
#0 lore raw

PATCH v4 1/2 MIPS: io: prevent compiler reordering on the default writeX() implementation

writeX() has a strong ordering semantics with respect to memory updates. In the abscence of a write barrier or a compiler barrier, commpiler can reorder register and memory update instructions. This breaks the writeX() API.

Signed-off-by Sinan Kaya <[email protected]>
---
 arch/mips/include/asm/io.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/include/asm/io.h +1 -1
index 0cbf3af..fd00ddaf 100644
@@ -307,7 +307,7 @@ static inline void iounmap(const volatile void __iomem *addr)
 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
 #define war_io_reorder_wmb()		wmb()
 #else
-#define war_io_reorder_wmb()		do { } while (0)
+#define war_io_reorder_wmb()		barrier()
 #endif
 
 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH v4 2/2 MIPS: io: add a barrier after register read in readX()

While a barrier is present in writeX() function before the register write, a similar barrier is missing in the readX() function after the register read. This could allow memory accesses following readX() to observe stale data.

Signed-off-by Sinan Kaya <[email protected]>
Reported-by Arnd Bergmann <[email protected]>
---
 arch/mips/include/asm/io.h | 2 ++
 1 file changed, 2 insertions(+)
arch/mips/include/asm/io.h +2 -0
index fd00ddaf..d96af41 100644
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
 		BUG();							\
 	}								\
 									\
+	/* prevent prefetching of coherent DMA dma prematurely */	\
+	rmb();								\
 	return pfx##ioswab##bwlq(__mem, __val);				\
 }
Signature · 1 line
2.7.4
author
#2 lore raw

Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

arch/mips/include/asm/io.h static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ · line 380

Quoted 1 line · Sinan Kaya
arch/mips/include/asm/io.h +1 -0
+	/* prevent prefetching of coherent DMA dma prematurely */	\

I tried to write DMA data but my keyboard is not cooperating. I'll hold onto posting another version until I hear back from you for wmb().

Signature · 3 lines
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
#3 lore raw

Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

Quoted 5 lines · Sinan Kaya

arch/mips/include/asm/io.h static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ · line 380

Quoted 1 line · Sinan Kaya
arch/mips/include/asm/io.h +1 -0
+	/* prevent prefetching of coherent DMA dma prematurely */	\

I tried to write DMA data but my keyboard is not cooperating. I'll hold onto posting another version until I hear back from you for wmb().

No problem, I've applied both for 4.17 and tweaked the comment.

Thanks
James
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20180414/a3da563c/attachment.sig>