Use global pages with PTI
Subsystems (5)
Dave Hansen
maintainerv5 cover Use global pages with PTI
Changes from v4
* Fix compile error reported by Tom Lendacky
* Avoid setting _PAGE_GLOBAL on non-present entries
Changes from v3:
* Fix whitespace issue noticed by willy
* Clarify comments about X86_FEATURE_PGE checks
* Clarify commit message around the necessity of _PAGE_GLOBAL filtering when CR4.PGE=0 or PGE is unsupported.
Changes from v2:
* Add performance numbers to changelogs
* Fix compile error resulting from use of x86-specific __default_kernel_pte_mask in arch-generic mm/early_ioremap.c
* Delay kernel text cloning until after we are done messing with it (patch 11).
* Blacklist K8 explicitly from mapping all kernel text as global (this should never happen because K8 does not use pti when pti=auto, but we on the safe side). (patch 11)
--
The later versions of the KAISER patches (pre-PTI) allowed the user/kernel shared areas to be GLOBAL. The thought was that this would reduce the TLB overhead of keeping two copies of these mappings.
During the switch over to PTI, we seem to have lost our ability to have GLOBAL mappings. This adds them back.
To measure the benefits of this, I took a modern Atom system without PCIDs and ran a microbenchmark[1] (higher is better):
No Global Lines (baseline ): 6077741 lseeks/sec 88 Global Lines (kern entry): 7528609 lseeks/sec (+23.9%) 94 Global Lines (all ktext ): 8433111 lseeks/sec (+38.8%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not huge:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
I also double-checked with a kernel compile on the Skylake system (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)1. https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
Dave Hansen
maintainerPATCH v5 1/11 x86/mm: factor out pageattr _PAGE_GLOBAL setting
From: Dave Hansen <[email protected]>
The pageattr code has a pattern repeated where it sets _PAGE_GLOBAL for present PTEs but clears it for non-present PTEs. The intention is to keep _PAGE_GLOBAL from getting confused with _PAGE_PROTNONE since _PAGE_GLOBAL is for present PTEs and _PAGE_PROTNONE is for non-present
But, this pattern makes no sense. Effectively, it says, if you use the pageattr code, always set _PAGE_GLOBAL when _PAGE_PRESENT. canon_pgprot() will clear it if unsupported (because it masks the value with __supported_pte_mask) but we *always* set it. Even if canon_pgprot() did not filter _PAGE_GLOBAL, it would be OK. _PAGE_GLOBAL is ignored when CR4.PGE=0 by the hardware.
This unconditional setting of _PAGE_GLOBAL is a problem when we have PTI and non-PTI and we want some areas to have _PAGE_GLOBAL and some not.
This updated version of the code says:
1. Clear _PAGE_GLOBAL when !_PAGE_PRESENT
2. Never set _PAGE_GLOBAL implicitly
3. Allow _PAGE_GLOBAL to be in cpa.set_mask
4. Allow _PAGE_GLOBAL to be inherited from previous PTE
---
b/arch/x86/mm/pageattr.c | 66 ++++++++++++++++------------------------------- 1 file changed, 23 insertions(+), 43 deletions(-)
arch/x86/mm/pageattr.c renamed from arch/x86/mm/pageattr.c~kpti-centralize-global-setting +23 -43
@@ -512,6 +512,23 @@ static void __set_pmd_pte(pte_t *kpte, u#endif } +static pgprot_t pgprot_clear_protnone_bits (pgprot_t prot) +{ +/* +* _PAGE_GLOBAL means "global page" for present PTEs. +* But, it is also used to indicate _PAGE_PROTNONE +* for non-present PTEs. +* +* This ensures that a _PAGE_GLOBAL PTE going from +* present to non-present is not confused as +* _PAGE_PROTNONE. +*/ +if (!(pgprot_val (prot) & _PAGE_PRESENT)) +pgprot_val (prot) &= ~_PAGE_GLOBAL; + +return prot; +} +static int try_preserve_large_page (pte_t *kpte,unsigned long address,struct cpa_data *cpa)
@@ -577,18 +594,11 @@ try_preserve_large_page(pte_t *kpte, uns* different bit positions in the two formats. */ req_prot =pgprot_4k_2_large (req_prot); - -/* -* Set the PSE and GLOBAL flags only if the PRESENT flag is -* set otherwise pmd_present/pmd_huge will return true even on -* a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL -* for the ancient hardware that doesn't support it. -*/ + req_prot =pgprot_clear_protnone_bits (req_prot);if (pgprot_val (req_prot) & _PAGE_PRESENT) -pgprot_val (req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; +pgprot_val (req_prot) |= _PAGE_PSE;else -pgprot_val (req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); - +pgprot_val (req_prot) &= ~_PAGE_PSE; req_prot =canon_pgprot (req_prot);/*
@@ -698,16 +708,7 @@ __split_large_page(struct cpa_data *cpa,return 1 ; } -/* -* Set the GLOBAL flags only if the PRESENT flag is set -* otherwise pmd/pte_present will return true even on a non -* present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL -* for the ancient hardware that doesn't support it. -*/ -if (pgprot_val (ref_prot) & _PAGE_PRESENT) -pgprot_val (ref_prot) |= _PAGE_GLOBAL; -else -pgprot_val (ref_prot) &= ~_PAGE_GLOBAL; + ref_prot =pgprot_clear_protnone_bits (ref_prot);/* * Get the target pfn from the original entry:
@@ -930,18 +931,7 @@ static void populate_pte(struct cpa_data pte =pte_offset_kernel (pmd, start); -/* -* Set the GLOBAL flags only if the PRESENT flag is -* set otherwise pte_present will return true even on -* a non present pte. The canon_pgprot will clear -* _PAGE_GLOBAL for the ancient hardware that doesn't -* support it. -*/ -if (pgprot_val (pgprot) & _PAGE_PRESENT) -pgprot_val (pgprot) |= _PAGE_GLOBAL; -else -pgprot_val (pgprot) &= ~_PAGE_GLOBAL; - + pgprot =pgprot_clear_protnone_bits (pgprot); pgprot =canon_pgprot (pgprot);while (num_pages-- && start < end) {
@@ -1234,17 +1224,7 @@ repeat: new_prot =static_protections (new_prot, address, pfn); -/* -* Set the GLOBAL flags only if the PRESENT flag is -* set otherwise pte_present will return true even on -* a non present pte. The canon_pgprot will clear -* _PAGE_GLOBAL for the ancient hardware that doesn't -* support it. -*/ -if (pgprot_val (new_prot) & _PAGE_PRESENT) -pgprot_val (new_prot) |= _PAGE_GLOBAL; -else -pgprot_val (new_prot) &= ~_PAGE_GLOBAL; + new_prot =pgprot_clear_protnone_bits (new_prot);/* * We need to keep the pfn from the existing PTE,
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Factor out pageattr _PAGE_GLOBAL setting
x86/mm: Factor out pageattr _PAGE_GLOBAL setting
Commit-ID: d1440b23c922d845ff039f64694a32ff356e89fa Gitweb: https://git.kernel.org/tip/d1440b23c922d845ff039f64694a32ff356e89fa Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:02 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:32 +0200
x86/mm: Factor out pageattr _PAGE_GLOBAL setting
The pageattr code has a pattern repeated where it sets _PAGE_GLOBAL for present PTEs but clears it for non-present PTEs. The intention is to keep _PAGE_GLOBAL from getting confused with _PAGE_PROTNONE since _PAGE_GLOBAL is for present PTEs and _PAGE_PROTNONE is for non-present
But, this pattern makes no sense. Effectively, it says, if you use the pageattr code, always set _PAGE_GLOBAL when _PAGE_PRESENT. canon_pgprot() will clear it if unsupported (because it masks the value with __supported_pte_mask) but we *always* set it. Even if canon_pgprot() did not filter _PAGE_GLOBAL, it would be OK. _PAGE_GLOBAL is ignored when CR4.PGE=0 by the hardware.
This unconditional setting of _PAGE_GLOBAL is a problem when we have PTI and non-PTI and we want some areas to have _PAGE_GLOBAL and some not.
This updated version of the code says:
1. Clear _PAGE_GLOBAL when !_PAGE_PRESENT
2. Never set _PAGE_GLOBAL implicitly
3. Allow _PAGE_GLOBAL to be in cpa.set_mask
4. Allow _PAGE_GLOBAL to be inherited from previous PTE
--- arch/x86/mm/pageattr.c | 66 ++++++++++++++++++-------------------------------- 1 file changed, 23 insertions(+), 43 deletions(-)
arch/x86/mm/pageattr.c +23 -43
@@ -512,6 +512,23 @@ static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)#endif } +static pgprot_t pgprot_clear_protnone_bits (pgprot_t prot) +{ +/* +* _PAGE_GLOBAL means "global page" for present PTEs. +* But, it is also used to indicate _PAGE_PROTNONE +* for non-present PTEs. +* +* This ensures that a _PAGE_GLOBAL PTE going from +* present to non-present is not confused as +* _PAGE_PROTNONE. +*/ +if (!(pgprot_val (prot) & _PAGE_PRESENT)) +pgprot_val (prot) &= ~_PAGE_GLOBAL; + +return prot; +} +static int try_preserve_large_page (pte_t *kpte,unsigned long address,struct cpa_data *cpa)
@@ -577,18 +594,11 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,* different bit positions in the two formats. */ req_prot =pgprot_4k_2_large (req_prot); - -/* -* Set the PSE and GLOBAL flags only if the PRESENT flag is -* set otherwise pmd_present/pmd_huge will return true even on -* a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL -* for the ancient hardware that doesn't support it. -*/ + req_prot =pgprot_clear_protnone_bits (req_prot);if (pgprot_val (req_prot) & _PAGE_PRESENT) -pgprot_val (req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; +pgprot_val (req_prot) |= _PAGE_PSE;else -pgprot_val (req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); - +pgprot_val (req_prot) &= ~_PAGE_PSE; req_prot =canon_pgprot (req_prot);/*
@@ -698,16 +708,7 @@ __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,return 1 ; } -/* -* Set the GLOBAL flags only if the PRESENT flag is set -* otherwise pmd/pte_present will return true even on a non -* present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL -* for the ancient hardware that doesn't support it. -*/ -if (pgprot_val (ref_prot) & _PAGE_PRESENT) -pgprot_val (ref_prot) |= _PAGE_GLOBAL; -else -pgprot_val (ref_prot) &= ~_PAGE_GLOBAL; + ref_prot =pgprot_clear_protnone_bits (ref_prot);/* * Get the target pfn from the original entry:
@@ -930,18 +931,7 @@ static void populate_pte(struct cpa_data *cpa, pte =pte_offset_kernel (pmd, start); -/* -* Set the GLOBAL flags only if the PRESENT flag is -* set otherwise pte_present will return true even on -* a non present pte. The canon_pgprot will clear -* _PAGE_GLOBAL for the ancient hardware that doesn't -* support it. -*/ -if (pgprot_val (pgprot) & _PAGE_PRESENT) -pgprot_val (pgprot) |= _PAGE_GLOBAL; -else -pgprot_val (pgprot) &= ~_PAGE_GLOBAL; - + pgprot =pgprot_clear_protnone_bits (pgprot); pgprot =canon_pgprot (pgprot);while (num_pages-- && start < end) {
@@ -1234,17 +1224,7 @@ repeat: new_prot =static_protections (new_prot, address, pfn); -/* -* Set the GLOBAL flags only if the PRESENT flag is -* set otherwise pte_present will return true even on -* a non present pte. The canon_pgprot will clear -* _PAGE_GLOBAL for the ancient hardware that doesn't -* support it. -*/ -if (pgprot_val (new_prot) & _PAGE_PRESENT) -pgprot_val (new_prot) |= _PAGE_GLOBAL; -else -pgprot_val (new_prot) &= ~_PAGE_GLOBAL; + new_prot =pgprot_clear_protnone_bits (new_prot);/* * We need to keep the pfn from the existing PTE,
Dave Hansen
maintainerPATCH v5 2/11 x86/mm: undo double _PAGE_PSE clearing
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
When clearing _PAGE_PRESENT on a huge page, we need to be careful to also clear _PAGE_PSE, otherwise it might still get confused for a valid large page table entry.
We do that near the spot where we *set* _PAGE_PSE. That's fine, but it's unnecessary. pgprot_large_2_4k() already did it.
BTW, I also noticed that pgprot_large_2_4k() and pgprot_4k_2_large() are not symmetric. pgprot_large_2_4k() clears _PAGE_PSE (because it is aliased to _PAGE_PAT) but pgprot_4k_2_large() does not put _PAGE_PSE back. Bummer.
Also, add some comments and change "promote" to "move". "Promote" seems an odd word to move when we are logically moving a bit to a lower bit position. Also add an extra line return to make it clear to which line the comment applies.
---
b/arch/x86/mm/pageattr.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
arch/x86/mm/pageattr.c renamed from arch/x86/mm/pageattr.c~kpti-undo-double-_PAGE_PSE-clear +6 -3
@@ -583,6 +583,7 @@ try_preserve_large_page(pte_t *kpte, uns* up accordingly. */ old_pte = *kpte; +/* Clear PSE (aka _PAGE_PAT) and move PAT bit to correct position */ req_prot =pgprot_large_2_4k (old_prot);pgprot_val (req_prot) &= ~pgprot_val (cpa->mask_clr);
@@ -597,8 +598,6 @@ try_preserve_large_page(pte_t *kpte, uns req_prot =pgprot_clear_protnone_bits (req_prot);if (pgprot_val (req_prot) & _PAGE_PRESENT)pgprot_val (req_prot) |= _PAGE_PSE; -else -pgprot_val (req_prot) &= ~_PAGE_PSE; req_prot =canon_pgprot (req_prot);/*
@@ -684,8 +683,12 @@ __split_large_page(struct cpa_data *cpa,switch (level) {case PG_LEVEL_2M : ref_prot =pmd_pgprot (*(pmd_t *)kpte); -/* clear PSE and promote PAT bit to correct position */ +/* +* Clear PSE (aka _PAGE_PAT) and move +* PAT bit to correct position. +*/ ref_prot =pgprot_large_2_4k (ref_prot); + ref_pfn =pmd_pfn (*(pmd_t *)kpte);break ;
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Undo double _PAGE_PSE clearing
x86/mm: Undo double _PAGE_PSE clearing
Commit-ID: 606c7193d5fbf8ea3dafc8a9468f719fbf1d7160 Gitweb: https://git.kernel.org/tip/606c7193d5fbf8ea3dafc8a9468f719fbf1d7160 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:04 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:32 +0200
x86/mm: Undo double _PAGE_PSE clearing
When clearing _PAGE_PRESENT on a huge page, we need to be careful to also clear _PAGE_PSE, otherwise it might still get confused for a valid large page table entry.
We do that near the spot where we *set* _PAGE_PSE. That's fine, but it's unnecessary. pgprot_large_2_4k() already did it.
BTW, I also noticed that pgprot_large_2_4k() and pgprot_4k_2_large() are not symmetric. pgprot_large_2_4k() clears _PAGE_PSE (because it is aliased to _PAGE_PAT) but pgprot_4k_2_large() does not put _PAGE_PSE back. Bummer.
Also, add some comments and change "promote" to "move". "Promote" seems an odd word to move when we are logically moving a bit to a lower bit position. Also add an extra line return to make it clear to which line the comment applies.
--- arch/x86/mm/pageattr.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
arch/x86/mm/pageattr.c +6 -3
@@ -583,6 +583,7 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,* up accordingly. */ old_pte = *kpte; +/* Clear PSE (aka _PAGE_PAT) and move PAT bit to correct position */ req_prot =pgprot_large_2_4k (old_prot);pgprot_val (req_prot) &= ~pgprot_val (cpa->mask_clr);
@@ -597,8 +598,6 @@ try_preserve_large_page(pte_t *kpte, unsigned long address, req_prot =pgprot_clear_protnone_bits (req_prot);if (pgprot_val (req_prot) & _PAGE_PRESENT)pgprot_val (req_prot) |= _PAGE_PSE; -else -pgprot_val (req_prot) &= ~_PAGE_PSE; req_prot =canon_pgprot (req_prot);/*
@@ -684,8 +683,12 @@ __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,switch (level) {case PG_LEVEL_2M : ref_prot =pmd_pgprot (*(pmd_t *)kpte); -/* clear PSE and promote PAT bit to correct position */ +/* +* Clear PSE (aka _PAGE_PAT) and move +* PAT bit to correct position. +*/ ref_prot =pgprot_large_2_4k (ref_prot); + ref_pfn =pmd_pfn (*(pmd_t *)kpte);break ;
Dave Hansen
maintainerPATCH v5 3/11 x86/mm: introduce "default" kernel PTE mask
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
The __PAGE_KERNEL_* page permissions are "raw". They contain bits that may or may not be supported on the current processor. They need to be filtered by a mask (currently __supported_pte_mask) to turn them into a value that we can actually set in a PTE.
These __PAGE_KERNEL_* values all contain _PAGE_GLOBAL. But, with PTI, we want to be able to support _PAGE_GLOBAL (have the bit set in __supported_pte_mask) but not have it appear in any of these masks by default.
This patch creates a new mask, __default_kernel_pte_mask, and applies it when creating all of the PAGE_KERNEL_* masks. This makes PAGE_KERNEL_* safe to use anywhere (they only contain supported bits). It also ensures that PAGE_KERNEL_* contains _PAGE_GLOBAL on PTI=n kernels but clears _PAGE_GLOBAL when PTI=y.
We also make __default_kernel_pte_mask a non-GPL exported symbol because there are plenty of driver-available interfaces that take PAGE_KERNEL_* permissions.
---
b/arch/x86/include/asm/pgtable_types.h | 27 +++++++++++++++------------ b/arch/x86/mm/init.c | 6 ++++++ b/arch/x86/mm/init_32.c | 8 +++++++- b/arch/x86/mm/init_64.c | 5 +++++ 4 files changed, 33 insertions(+), 13 deletions(-)
arch/x86/include/asm/pgtable_types.h renamed from arch/x86/include/asm/pgtable_types.h~KERN-pgprot-default +15 -12
@@ -196,19 +196,21 @@ enum page_cache_mode {#define __PAGE_KERNEL_NOENC (__PAGE_KERNEL)#define __PAGE_KERNEL_NOENC_WP (__PAGE_KERNEL_WP) -#define PAGE_KERNEL __pgprot(__PAGE_KERNEL | _PAGE_ENC) -#define PAGE_KERNEL_NOENC __pgprot(__PAGE_KERNEL) -#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO | _PAGE_ENC) -#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC | _PAGE_ENC) -#define PAGE_KERNEL_EXEC_NOENC __pgprot(__PAGE_KERNEL_EXEC) -#define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX | _PAGE_ENC) -#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE | _PAGE_ENC) -#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE | _PAGE_ENC) -#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC | _PAGE_ENC) -#define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR | _PAGE_ENC) +#define default_pgprot (x) __pgprot((x) & __default_kernel_pte_mask) -#define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO) -#define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE) +#define PAGE_KERNEL default_pgprot(__PAGE_KERNEL | _PAGE_ENC) +#define PAGE_KERNEL_NOENC default_pgprot(__PAGE_KERNEL) +#define PAGE_KERNEL_RO default_pgprot(__PAGE_KERNEL_RO | _PAGE_ENC) +#define PAGE_KERNEL_EXEC default_pgprot(__PAGE_KERNEL_EXEC | _PAGE_ENC) +#define PAGE_KERNEL_EXEC_NOENC default_pgprot(__PAGE_KERNEL_EXEC) +#define PAGE_KERNEL_RX default_pgprot(__PAGE_KERNEL_RX | _PAGE_ENC) +#define PAGE_KERNEL_NOCACHE default_pgprot(__PAGE_KERNEL_NOCACHE | _PAGE_ENC) +#define PAGE_KERNEL_LARGE default_pgprot(__PAGE_KERNEL_LARGE | _PAGE_ENC) +#define PAGE_KERNEL_LARGE_EXEC default_pgprot(__PAGE_KERNEL_LARGE_EXEC | _PAGE_ENC) +#define PAGE_KERNEL_VVAR default_pgprot(__PAGE_KERNEL_VVAR | _PAGE_ENC) + +#define PAGE_KERNEL_IO default_pgprot(__PAGE_KERNEL_IO) +#define PAGE_KERNEL_IO_NOCACHE default_pgprot(__PAGE_KERNEL_IO_NOCACHE)#endif /* __ASSEMBLY__ */
@@ -483,6 +485,7 @@ static inline pgprot_t pgprot_large_2_4ktypedef struct page *pgtable_t ;extern pteval_t __supported_pte_mask; +extern pteval_t __default_kernel_pte_mask;extern void set_nx (void );extern int nx_enabled;
arch/x86/mm/init_32.c renamed from arch/x86/mm/init_32.c~KERN-pgprot-default +7 -1
@@ -558,8 +558,14 @@ static void __init pagetable_init(void)permanent_kmaps_init (pgd_base); } -pteval_t __supported_pte_mask__read_mostly = ~(_PAGE_NX | _PAGE_GLOBAL); +#define DEFAULT_PTE_MASK ~(_PAGE_NX | _PAGE_GLOBAL) +/* Bits supported by the hardware: */ +pteval_t __supported_pte_mask__read_mostly =DEFAULT_PTE_MASK ; +/* Bits allowed in normal kernel mappings: */ +pteval_t __default_kernel_pte_mask__read_mostly =DEFAULT_PTE_MASK ;EXPORT_SYMBOL_GPL (__supported_pte_mask); +/* Used in PAGE_KERNEL_* macros which are reasonably used out-of-tree: */ +EXPORT_SYMBOL (__default_kernel_pte_mask);/* user-defined highmem size */ static unsigned int highmem_pages =-1 ;
arch/x86/mm/init_64.c renamed from arch/x86/mm/init_64.c~KERN-pgprot-default +5 -0
@@ -65,8 +65,13 @@* around without checking the pgd every time. */ +/* Bits supported by the hardware: */ pteval_t __supported_pte_mask__read_mostly = ~0 ; +/* Bits allowed in normal kernel mappings: */ +pteval_t __default_kernel_pte_mask__read_mostly = ~0 ;EXPORT_SYMBOL_GPL (__supported_pte_mask); +/* Used in PAGE_KERNEL_* macros which are reasonably used out-of-tree: */ +EXPORT_SYMBOL (__default_kernel_pte_mask);int force_personality32;
arch/x86/mm/init.c renamed from arch/x86/mm/init.c~KERN-pgprot-default +6 -0
@@ -190,6 +190,12 @@ static void __init probe_page_size_mask(enable_global_pages (); } +/* By the default is everything supported: */ + __default_kernel_pte_mask = __supported_pte_mask; +/* Except when with PTI where the kernel is mostly non-Global: */ +if (cpu_feature_enabled (X86_FEATURE_PTI )) + __default_kernel_pte_mask &= ~_PAGE_GLOBAL; +/* Enable 1 GB linear kernel mappings if available: */ if (direct_gbpages &&boot_cpu_has (X86_FEATURE_GBPAGES )) {printk (KERN_INFO "Using GB pages for direct mapping\n" );
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Introduce "default" kernel PTE mask
x86/mm: Introduce "default" kernel PTE mask
Commit-ID: 8a57f4849f4fa22ed18a941164a214083fc020a2 Gitweb: https://git.kernel.org/tip/8a57f4849f4fa22ed18a941164a214083fc020a2 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:06 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:32 +0200
x86/mm: Introduce "default" kernel PTE mask
The __PAGE_KERNEL_* page permissions are "raw". They contain bits that may or may not be supported on the current processor. They need to be filtered by a mask (currently __supported_pte_mask) to turn them into a value that we can actually set in a PTE.
These __PAGE_KERNEL_* values all contain _PAGE_GLOBAL. But, with PTI, we want to be able to support _PAGE_GLOBAL (have the bit set in __supported_pte_mask) but not have it appear in any of these masks by default.
This patch creates a new mask, __default_kernel_pte_mask, and applies it when creating all of the PAGE_KERNEL_* masks. This makes PAGE_KERNEL_* safe to use anywhere (they only contain supported bits). It also ensures that PAGE_KERNEL_* contains _PAGE_GLOBAL on PTI=n kernels but clears _PAGE_GLOBAL when PTI=y.
We also make __default_kernel_pte_mask a non-GPL exported symbol because there are plenty of driver-available interfaces that take PAGE_KERNEL_* permissions.
--- arch/x86/include/asm/pgtable_types.h | 29 ++++++++++++++++------------- arch/x86/mm/init.c | 6 ++++++ arch/x86/mm/init_32.c | 8 +++++++- arch/x86/mm/init_64.c | 5 +++++ 4 files changed, 34 insertions(+), 14 deletions(-)
arch/x86/include/asm/pgtable_types.h +16 -13
@@ -196,19 +196,21 @@ enum page_cache_mode {#define __PAGE_KERNEL_NOENC (__PAGE_KERNEL)#define __PAGE_KERNEL_NOENC_WP (__PAGE_KERNEL_WP) -#define PAGE_KERNEL __pgprot(__PAGE_KERNEL | _PAGE_ENC) -#define PAGE_KERNEL_NOENC __pgprot(__PAGE_KERNEL) -#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO | _PAGE_ENC) -#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC | _PAGE_ENC) -#define PAGE_KERNEL_EXEC_NOENC __pgprot(__PAGE_KERNEL_EXEC) -#define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX | _PAGE_ENC) -#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE | _PAGE_ENC) -#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE | _PAGE_ENC) -#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC | _PAGE_ENC) -#define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR | _PAGE_ENC) - -#define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO) -#define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE) +#define default_pgprot (x) __pgprot((x) & __default_kernel_pte_mask) + +#define PAGE_KERNEL default_pgprot(__PAGE_KERNEL | _PAGE_ENC) +#define PAGE_KERNEL_NOENC default_pgprot(__PAGE_KERNEL) +#define PAGE_KERNEL_RO default_pgprot(__PAGE_KERNEL_RO | _PAGE_ENC) +#define PAGE_KERNEL_EXEC default_pgprot(__PAGE_KERNEL_EXEC | _PAGE_ENC) +#define PAGE_KERNEL_EXEC_NOENC default_pgprot(__PAGE_KERNEL_EXEC) +#define PAGE_KERNEL_RX default_pgprot(__PAGE_KERNEL_RX | _PAGE_ENC) +#define PAGE_KERNEL_NOCACHE default_pgprot(__PAGE_KERNEL_NOCACHE | _PAGE_ENC) +#define PAGE_KERNEL_LARGE default_pgprot(__PAGE_KERNEL_LARGE | _PAGE_ENC) +#define PAGE_KERNEL_LARGE_EXEC default_pgprot(__PAGE_KERNEL_LARGE_EXEC | _PAGE_ENC) +#define PAGE_KERNEL_VVAR default_pgprot(__PAGE_KERNEL_VVAR | _PAGE_ENC) + +#define PAGE_KERNEL_IO default_pgprot(__PAGE_KERNEL_IO) +#define PAGE_KERNEL_IO_NOCACHE default_pgprot(__PAGE_KERNEL_IO_NOCACHE)#endif /* __ASSEMBLY__ */
@@ -483,6 +485,7 @@ static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)typedef struct page *pgtable_t ;extern pteval_t __supported_pte_mask; +extern pteval_t __default_kernel_pte_mask;extern void set_nx (void );extern int nx_enabled;
arch/x86/mm/init.c +6 -0
@@ -190,6 +190,12 @@ static void __init probe_page_size_mask(void)enable_global_pages (); } +/* By the default is everything supported: */ + __default_kernel_pte_mask = __supported_pte_mask; +/* Except when with PTI where the kernel is mostly non-Global: */ +if (cpu_feature_enabled (X86_FEATURE_PTI )) + __default_kernel_pte_mask &= ~_PAGE_GLOBAL; +/* Enable 1 GB linear kernel mappings if available: */ if (direct_gbpages &&boot_cpu_has (X86_FEATURE_GBPAGES )) {printk (KERN_INFO "Using GB pages for direct mapping\n" );
arch/x86/mm/init_32.c +7 -1
@@ -558,8 +558,14 @@ static void __init pagetable_init(void)permanent_kmaps_init (pgd_base); } -pteval_t __supported_pte_mask__read_mostly = ~(_PAGE_NX | _PAGE_GLOBAL); +#define DEFAULT_PTE_MASK ~(_PAGE_NX | _PAGE_GLOBAL) +/* Bits supported by the hardware: */ +pteval_t __supported_pte_mask__read_mostly =DEFAULT_PTE_MASK ; +/* Bits allowed in normal kernel mappings: */ +pteval_t __default_kernel_pte_mask__read_mostly =DEFAULT_PTE_MASK ;EXPORT_SYMBOL_GPL (__supported_pte_mask); +/* Used in PAGE_KERNEL_* macros which are reasonably used out-of-tree: */ +EXPORT_SYMBOL (__default_kernel_pte_mask);/* user-defined highmem size */ static unsigned int highmem_pages =-1 ;
arch/x86/mm/init_64.c +5 -0
@@ -65,8 +65,13 @@* around without checking the pgd every time. */ +/* Bits supported by the hardware: */ pteval_t __supported_pte_mask__read_mostly = ~0 ; +/* Bits allowed in normal kernel mappings: */ +pteval_t __default_kernel_pte_mask__read_mostly = ~0 ;EXPORT_SYMBOL_GPL (__supported_pte_mask); +/* Used in PAGE_KERNEL_* macros which are reasonably used out-of-tree: */ +EXPORT_SYMBOL (__default_kernel_pte_mask);int force_personality32;
Dave Hansen
maintainerPATCH v5 4/11 x86/espfix: document use of _PAGE_GLOBAL
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
The "normal" kernel page table creation mechanisms using PAGE_KERNEL_* page protections will never set _PAGE_GLOBAL with PTI. The few places in the kernel that always want _PAGE_GLOBAL must avoid using PAGE_KERNEL_*.
Document that we want it here and its use is not accidental.
---
b/arch/x86/kernel/espfix_64.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/x86/kernel/espfix_64.c renamed from arch/x86/kernel/espfix_64.c~espfix-use-kern-defaults-not-supported +4 -0
@@ -195,6 +195,10 @@ void init_espfix_ap(int cpu) pte_p =pte_offset_kernel (&pmd, addr); stack_page =page_address (alloc_pages_node (node,GFP_KERNEL ,0 )); +/* +* __PAGE_KERNEL_* includes _PAGE_GLOBAL, which we want since +* this is mapped to userspace. +*/ pte =__pte (__pa (stack_page) | ((__PAGE_KERNEL_RO | _PAGE_ENC) & ptemask));for (n =0 ; n <ESPFIX_PTE_CLONES ; n++)set_pte (&pte_p[n*PTE_STRIDE ], pte);
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/espfix: Document use of _PAGE_GLOBAL
x86/espfix: Document use of _PAGE_GLOBAL
Commit-ID: 6baf4bec02dbc41645c3a5130ee15a8e1d62b80f Gitweb: https://git.kernel.org/tip/6baf4bec02dbc41645c3a5130ee15a8e1d62b80f Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:07 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:33 +0200
x86/espfix: Document use of _PAGE_GLOBAL
The "normal" kernel page table creation mechanisms using PAGE_KERNEL_* page protections will never set _PAGE_GLOBAL with PTI. The few places in the kernel that always want _PAGE_GLOBAL must avoid using PAGE_KERNEL_*.
Document that we want it here and its use is not accidental.
--- arch/x86/kernel/espfix_64.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/x86/kernel/espfix_64.c +4 -0
@@ -195,6 +195,10 @@ void init_espfix_ap(int cpu) pte_p =pte_offset_kernel (&pmd, addr); stack_page =page_address (alloc_pages_node (node,GFP_KERNEL ,0 )); +/* +* __PAGE_KERNEL_* includes _PAGE_GLOBAL, which we want since +* this is mapped to userspace. +*/ pte =__pte (__pa (stack_page) | ((__PAGE_KERNEL_RO | _PAGE_ENC) & ptemask));for (n =0 ; n <ESPFIX_PTE_CLONES ; n++)set_pte (&pte_p[n*PTE_STRIDE ], pte);
Dave Hansen
maintainerPATCH v5 5/11 x86/mm: do not auto-massage page protections
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
A PTE is constructed from a physical address and a pgprotval_t. __PAGE_KERNEL, for instance, is a pgprot_t and must be converted into a pgprotval_t before it can be used to create a PTE. This is done implicitly within functions like pfn_pte() by massage_pgprot().
However, this makes it very challenging to set bits (and keep them set) if your bit is being filtered out by massage_pgprot().
This moves the bit filtering out of pfn_pte() and friends. For users of PAGE_KERNEL*, filtering will be done automatically inside those macros but for users of __PAGE_KERNEL*, they need to do their own filtering now.
Note that we also just move pfn_pte/pmd/pud() over to check_pgprot() instead of massage_pgprot(). This way, we still *look* for unsupported bits and properly warn about them if we find them. This might happen if an unfiltered __PAGE_KERNEL* value was passed in, for instance.
---
b/arch/x86/boot/compressed/kaslr.c | 3 +++ b/arch/x86/include/asm/pgtable.h | 27 ++++++++++++++++++++++----- b/arch/x86/kernel/head64.c | 2 ++ b/arch/x86/kernel/ldt.c | 6 +++++- b/arch/x86/mm/ident_map.c | 3 +++ b/arch/x86/mm/iomap_32.c | 6 ++++++ b/arch/x86/mm/ioremap.c | 3 +++ b/arch/x86/mm/kasan_init_64.c | 14 +++++++++++++- b/arch/x86/mm/pgtable.c | 3 +++ b/arch/x86/power/hibernate_64.c | 20 +++++++++++++++----- 10 files changed, 75 insertions(+), 12 deletions(-)
arch/x86/boot/compressed/kaslr.c renamed from arch/x86/boot/compressed/kaslr.c~x86-no-auto-massage +3 -0
@@ -54,6 +54,9 @@ unsigned int ptrs_per_p4d __ro_after_iniextern unsigned long get_cmd_line_ptr (void ); +/* Used by PAGE_KERN* macros: */ +pteval_t __default_kernel_pte_mask__read_mostly ; +/* Simplified build-specific string for starting entropy. */ static const char build_str[] =UTS_RELEASE " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ") (" LINUX_COMPILER ") " UTS_VERSION ;
arch/x86/include/asm/pgtable.h renamed from arch/x86/include/asm/pgtable.h~x86-no-auto-massage +22 -5
@@ -526,22 +526,39 @@ static inline pgprotval_t massage_pgprotreturn protval; } +static inline pgprotval_t check_pgprot (pgprot_t pgprot) +{ +pgprotval_t massaged_val =massage_pgprot (pgprot); + +/* mmdebug.h can not be included here because of dependencies */ +#ifdef CONFIG_DEBUG_VM +WARN_ONCE (pgprot_val (pgprot) != massaged_val, +"attempted to set unsupported pgprot: %016lx " +"bits: %016lx supported: %016lx\n" , +pgprot_val (pgprot), +pgprot_val (pgprot) ^ massaged_val, + __supported_pte_mask); +#endif + +return massaged_val; +} +static inline pte_t pfn_pte (unsigned long page_nr,pgprot_t pgprot) {return __pte (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pmd_t pfn_pmd (unsigned long page_nr,pgprot_t pgprot) {return __pmd (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pud_t pfn_pud (unsigned long page_nr,pgprot_t pgprot) {return __pud (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pte_t pte_modify (pte_t pte,pgprot_t newprot)
@@ -553,7 +570,7 @@ static inline pte_t pte_modify(pte_t pte* the newprot (if present): */ val &= _PAGE_CHG_MASK; - val |=massage_pgprot (newprot) & ~_PAGE_CHG_MASK; + val |=check_pgprot (newprot) & ~_PAGE_CHG_MASK;return __pte (val); }
@@ -563,7 +580,7 @@ static inline pmd_t pmd_modify(pmd_t pmdpmdval_t val =pmd_val (pmd); val &= _HPAGE_CHG_MASK; - val |=massage_pgprot (newprot) & ~_HPAGE_CHG_MASK; + val |=check_pgprot (newprot) & ~_HPAGE_CHG_MASK;return __pmd (val); }
arch/x86/kernel/head64.c renamed from arch/x86/kernel/head64.c~x86-no-auto-massage +2 -0
@@ -195,6 +195,8 @@ unsigned long __head __startup_64(unsign pud[i +1 ] = (pudval_t )pmd + pgtable_flags; pmd_entry = __PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL; +/* Filter out unsupported __PAGE_KERNEL_* bits: */ + pmd_entry &= __supported_pte_mask; pmd_entry +=sme_get_me_mask (); pmd_entry += physaddr;
arch/x86/kernel/ldt.c renamed from arch/x86/kernel/ldt.c~x86-no-auto-massage +5 -1
@@ -145,6 +145,7 @@ map_ldt_struct(struct mm_struct *mm, strunsigned long offset = i <<PAGE_SHIFT ;const void *src = (char *)ldt->entries + offset;unsigned long pfn; +pgprot_t pte_prot;pte_t pte, *ptep; va = (unsigned long )ldt_slot_va (slot) + offset;
@@ -163,7 +164,10 @@ map_ldt_struct(struct mm_struct *mm, str* target via some kernel interface which misses a * permission check. */ - pte =pfn_pte (pfn,__pgprot (__PAGE_KERNEL_RO & ~_PAGE_GLOBAL)); + pte_prot =__pgprot (__PAGE_KERNEL_RO & ~_PAGE_GLOBAL); +/* Filter out unsuppored __PAGE_KERNEL* bits: */ +pgprot_val (pte_prot) |= __supported_pte_mask; + pte =pfn_pte (pfn, pte_prot);set_pte_at (mm, va, ptep, pte);pte_unmap_unlock (ptep, ptl); }
arch/x86/mm/ident_map.c renamed from arch/x86/mm/ident_map.c~x86-no-auto-massage +3 -0
@@ -98,6 +98,9 @@ int kernel_ident_mapping_init(struct x86if (!info->kernpg_flag) info->kernpg_flag = _KERNPG_TABLE; +/* Filter out unsupported __PAGE_KERNEL_* bits: */ + info->kernpg_flag &= __default_kernel_pte_mask; +for (; addr < end; addr = next) {pgd_t *pgd = pgd_page +pgd_index (addr);p4d_t *p4d;
arch/x86/mm/iomap_32.c renamed from arch/x86/mm/iomap_32.c~x86-no-auto-massage +6 -0
@@ -44,6 +44,9 @@ int iomap_create_wc(resource_size_t basereturn ret; *prot =__pgprot (__PAGE_KERNEL |cachemode2protval (pcm)); +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (*prot) &= __default_kernel_pte_mask; +return 0 ; }EXPORT_SYMBOL_GPL (iomap_create_wc);
@@ -88,6 +91,9 @@ iomap_atomic_prot_pfn(unsigned long pfn, prot =__pgprot (__PAGE_KERNEL |cachemode2protval (_PAGE_CACHE_MODE_UC_MINUS)); +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (prot) &= __default_kernel_pte_mask; +return (void __force __iomem *)kmap_atomic_prot_pfn (pfn, prot); }EXPORT_SYMBOL_GPL (iomap_atomic_prot_pfn);
arch/x86/mm/ioremap.c renamed from arch/x86/mm/ioremap.c~x86-no-auto-massage +3 -0
@@ -816,6 +816,9 @@ void __init __early_set_fixmap(enum fixe } pte =early_ioremap_pte (addr); +/* Sanitize 'prot' against any unsupported bits: */ +pgprot_val (flags) &= __default_kernel_pte_mask; +if (pgprot_val (flags))set_pte (pte,pfn_pte (phys >>PAGE_SHIFT , flags));else
arch/x86/mm/kasan_init_64.c renamed from arch/x86/mm/kasan_init_64.c~x86-no-auto-massage +13 -1
@@ -269,6 +269,12 @@ void __init kasan_early_init(void)pudval_t pud_val =__pa_nodebug (kasan_zero_pmd) | _KERNPG_TABLE;p4dval_t p4d_val =__pa_nodebug (kasan_zero_pud) | _KERNPG_TABLE; +/* Mask out unsupported __PAGE_KERNEL bits: */ + pte_val &= __default_kernel_pte_mask; + pmd_val &= __default_kernel_pte_mask; + pud_val &= __default_kernel_pte_mask; + p4d_val &= __default_kernel_pte_mask; +for (i =0 ; i <PTRS_PER_PTE ; i++) kasan_zero_pte[i] =__pte (pte_val);
@@ -371,7 +377,13 @@ void __init kasan_init(void)*/ memset (kasan_zero_page,0 ,PAGE_SIZE );for (i =0 ; i <PTRS_PER_PTE ; i++) { -pte_t pte =__pte (__pa (kasan_zero_page) | __PAGE_KERNEL_RO | _PAGE_ENC); +pte_t pte; +pgprot_t prot; + + prot =__pgprot (__PAGE_KERNEL_RO | _PAGE_ENC); +pgprot_val (prot) &= __default_kernel_pte_mask; + + pte =__pte (__pa (kasan_zero_page) |pgprot_val (prot));set_pte (&kasan_zero_pte[i], pte); }/* Flush TLBs again to be sure that write protection applied. */
arch/x86/mm/pgtable.c renamed from arch/x86/mm/pgtable.c~x86-no-auto-massage +3 -0
@@ -583,6 +583,9 @@ void __native_set_fixmap(enum fixed_addrvoid native_set_fixmap (enum fixed_addresses idx,phys_addr_t phys,pgprot_t flags) { +/* Sanitize 'prot' against any unsupported bits: */ +pgprot_val (flags) &= __default_kernel_pte_mask; +__native_set_fixmap (idx,pfn_pte (phys >>PAGE_SHIFT , flags)); }
arch/x86/power/hibernate_64.c renamed from arch/x86/power/hibernate_64.c~x86-no-auto-massage +15 -5
@@ -51,6 +51,12 @@ static int set_up_temporary_text_mappingpmd_t *pmd;pud_t *pud;p4d_t *p4d =NULL ; +pgprot_t pgtable_prot =__pgprot (_KERNPG_TABLE); +pgprot_t pmd_text_prot =__pgprot (__PAGE_KERNEL_LARGE_EXEC); + +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (pmd_text_prot) &= __default_kernel_pte_mask; +pgprot_val (pgtable_prot) &= __default_kernel_pte_mask;/* * The new mapping only has to cover the page containing the image
@@ -81,15 +87,19 @@ static int set_up_temporary_text_mappingreturn -ENOMEM ;set_pmd (pmd +pmd_index (restore_jump_address), -__pmd ((jump_address_phys &PMD_MASK ) | __PAGE_KERNEL_LARGE_EXEC)); +__pmd ((jump_address_phys &PMD_MASK ) |pgprot_val (pmd_text_prot)));set_pud (pud +pud_index (restore_jump_address), -__pud (__pa (pmd) | _KERNPG_TABLE)); +__pud (__pa (pmd) |pgprot_val (pgtable_prot)));if (p4d) { -set_p4d (p4d +p4d_index (restore_jump_address),__p4d (__pa (pud) | _KERNPG_TABLE)); -set_pgd (pgd +pgd_index (restore_jump_address),__pgd (__pa (p4d) | _KERNPG_TABLE)); +p4d_t new_p4d =__p4d (__pa (pud) |pgprot_val (pgtable_prot)); +pgd_t new_pgd =__pgd (__pa (p4d) |pgprot_val (pgtable_prot)); + +set_p4d (p4d +p4d_index (restore_jump_address), new_p4d); +set_pgd (pgd +pgd_index (restore_jump_address), new_pgd); }else {/* No p4d for 4-level paging: point the pgd to the pud page table */ -set_pgd (pgd +pgd_index (restore_jump_address),__pgd (__pa (pud) | _KERNPG_TABLE)); +pgd_t new_pgd =__pgd (__pa (p4d) |pgprot_val (pgtable_prot)); +set_pgd (pgd +pgd_index (restore_jump_address), new_pgd); }return 0 ;
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Do not auto-massage page protections
x86/mm: Do not auto-massage page protections
Commit-ID: 64c80759408f1c47d2414bfa79f80a4573a8d68d Gitweb: https://git.kernel.org/tip/64c80759408f1c47d2414bfa79f80a4573a8d68d Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:09 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:33 +0200
x86/mm: Do not auto-massage page protections
A PTE is constructed from a physical address and a pgprotval_t. __PAGE_KERNEL, for instance, is a pgprot_t and must be converted into a pgprotval_t before it can be used to create a PTE. This is done implicitly within functions like pfn_pte() by massage_pgprot().
However, this makes it very challenging to set bits (and keep them set) if your bit is being filtered out by massage_pgprot().
This moves the bit filtering out of pfn_pte() and friends. For users of PAGE_KERNEL*, filtering will be done automatically inside those macros but for users of __PAGE_KERNEL*, they need to do their own filtering now.
Note that we also just move pfn_pte/pmd/pud() over to check_pgprot() instead of massage_pgprot(). This way, we still *look* for unsupported bits and properly warn about them if we find them. This might happen if an unfiltered __PAGE_KERNEL* value was passed in, for instance.
--- arch/x86/boot/compressed/kaslr.c | 3 +++ arch/x86/include/asm/pgtable.h | 27 ++++++++++++++++++++++----- arch/x86/kernel/head64.c | 2 ++ arch/x86/kernel/ldt.c | 6 +++++- arch/x86/mm/ident_map.c | 3 +++ arch/x86/mm/iomap_32.c | 6 ++++++ arch/x86/mm/ioremap.c | 3 +++ arch/x86/mm/kasan_init_64.c | 14 +++++++++++++- arch/x86/mm/pgtable.c | 3 +++ arch/x86/power/hibernate_64.c | 20 +++++++++++++++----- 10 files changed, 75 insertions(+), 12 deletions(-)
arch/x86/boot/compressed/kaslr.c +3 -0
@@ -54,6 +54,9 @@ unsigned int ptrs_per_p4d __ro_after_init = 1;extern unsigned long get_cmd_line_ptr (void ); +/* Used by PAGE_KERN* macros: */ +pteval_t __default_kernel_pte_mask__read_mostly ; +/* Simplified build-specific string for starting entropy. */ static const char build_str[] =UTS_RELEASE " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ") (" LINUX_COMPILER ") " UTS_VERSION ;
arch/x86/include/asm/pgtable.h +22 -5
@@ -526,22 +526,39 @@ static inline pgprotval_t massage_pgprot(pgprot_t pgprot)return protval; } +static inline pgprotval_t check_pgprot (pgprot_t pgprot) +{ +pgprotval_t massaged_val =massage_pgprot (pgprot); + +/* mmdebug.h can not be included here because of dependencies */ +#ifdef CONFIG_DEBUG_VM +WARN_ONCE (pgprot_val (pgprot) != massaged_val, +"attempted to set unsupported pgprot: %016lx " +"bits: %016lx supported: %016lx\n" , +pgprot_val (pgprot), +pgprot_val (pgprot) ^ massaged_val, + __supported_pte_mask); +#endif + +return massaged_val; +} +static inline pte_t pfn_pte (unsigned long page_nr,pgprot_t pgprot) {return __pte (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pmd_t pfn_pmd (unsigned long page_nr,pgprot_t pgprot) {return __pmd (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pud_t pfn_pud (unsigned long page_nr,pgprot_t pgprot) {return __pud (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pte_t pte_modify (pte_t pte,pgprot_t newprot)
@@ -553,7 +570,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)* the newprot (if present): */ val &= _PAGE_CHG_MASK; - val |=massage_pgprot (newprot) & ~_PAGE_CHG_MASK; + val |=check_pgprot (newprot) & ~_PAGE_CHG_MASK;return __pte (val); }
@@ -563,7 +580,7 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)pmdval_t val =pmd_val (pmd); val &= _HPAGE_CHG_MASK; - val |=massage_pgprot (newprot) & ~_HPAGE_CHG_MASK; + val |=check_pgprot (newprot) & ~_HPAGE_CHG_MASK;return __pmd (val); }
arch/x86/kernel/head64.c +2 -0
@@ -195,6 +195,8 @@ unsigned long __head __startup_64(unsigned long physaddr, pud[i +1 ] = (pudval_t )pmd + pgtable_flags; pmd_entry = __PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL; +/* Filter out unsupported __PAGE_KERNEL_* bits: */ + pmd_entry &= __supported_pte_mask; pmd_entry +=sme_get_me_mask (); pmd_entry += physaddr;
arch/x86/kernel/ldt.c +5 -1
@@ -145,6 +145,7 @@ map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot)unsigned long offset = i <<PAGE_SHIFT ;const void *src = (char *)ldt->entries + offset;unsigned long pfn; +pgprot_t pte_prot;pte_t pte, *ptep; va = (unsigned long )ldt_slot_va (slot) + offset;
@@ -163,7 +164,10 @@ map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot)* target via some kernel interface which misses a * permission check. */ - pte =pfn_pte (pfn,__pgprot (__PAGE_KERNEL_RO & ~_PAGE_GLOBAL)); + pte_prot =__pgprot (__PAGE_KERNEL_RO & ~_PAGE_GLOBAL); +/* Filter out unsuppored __PAGE_KERNEL* bits: */ +pgprot_val (pte_prot) |= __supported_pte_mask; + pte =pfn_pte (pfn, pte_prot);set_pte_at (mm, va, ptep, pte);pte_unmap_unlock (ptep, ptl); }
arch/x86/mm/ident_map.c +3 -0
@@ -98,6 +98,9 @@ int kernel_ident_mapping_init(struct x86_mapping_info *info, pgd_t *pgd_page,if (!info->kernpg_flag) info->kernpg_flag = _KERNPG_TABLE; +/* Filter out unsupported __PAGE_KERNEL_* bits: */ + info->kernpg_flag &= __default_kernel_pte_mask; +for (; addr < end; addr = next) {pgd_t *pgd = pgd_page +pgd_index (addr);p4d_t *p4d;
arch/x86/mm/iomap_32.c +6 -0
@@ -44,6 +44,9 @@ int iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot)return ret; *prot =__pgprot (__PAGE_KERNEL |cachemode2protval (pcm)); +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (*prot) &= __default_kernel_pte_mask; +return 0 ; }EXPORT_SYMBOL_GPL (iomap_create_wc);
@@ -88,6 +91,9 @@ iomap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot) prot =__pgprot (__PAGE_KERNEL |cachemode2protval (_PAGE_CACHE_MODE_UC_MINUS)); +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (prot) &= __default_kernel_pte_mask; +return (void __force __iomem *)kmap_atomic_prot_pfn (pfn, prot); }EXPORT_SYMBOL_GPL (iomap_atomic_prot_pfn);
arch/x86/mm/ioremap.c +3 -0
@@ -816,6 +816,9 @@ void __init __early_set_fixmap(enum fixed_addresses idx, } pte =early_ioremap_pte (addr); +/* Sanitize 'prot' against any unsupported bits: */ +pgprot_val (flags) &= __default_kernel_pte_mask; +if (pgprot_val (flags))set_pte (pte,pfn_pte (phys >>PAGE_SHIFT , flags));else
arch/x86/mm/kasan_init_64.c +13 -1
@@ -269,6 +269,12 @@ void __init kasan_early_init(void)pudval_t pud_val =__pa_nodebug (kasan_zero_pmd) | _KERNPG_TABLE;p4dval_t p4d_val =__pa_nodebug (kasan_zero_pud) | _KERNPG_TABLE; +/* Mask out unsupported __PAGE_KERNEL bits: */ + pte_val &= __default_kernel_pte_mask; + pmd_val &= __default_kernel_pte_mask; + pud_val &= __default_kernel_pte_mask; + p4d_val &= __default_kernel_pte_mask; +for (i =0 ; i <PTRS_PER_PTE ; i++) kasan_zero_pte[i] =__pte (pte_val);
@@ -371,7 +377,13 @@ void __init kasan_init(void)*/ memset (kasan_zero_page,0 ,PAGE_SIZE );for (i =0 ; i <PTRS_PER_PTE ; i++) { -pte_t pte =__pte (__pa (kasan_zero_page) | __PAGE_KERNEL_RO | _PAGE_ENC); +pte_t pte; +pgprot_t prot; + + prot =__pgprot (__PAGE_KERNEL_RO | _PAGE_ENC); +pgprot_val (prot) &= __default_kernel_pte_mask; + + pte =__pte (__pa (kasan_zero_page) |pgprot_val (prot));set_pte (&kasan_zero_pte[i], pte); }/* Flush TLBs again to be sure that write protection applied. */
arch/x86/mm/pgtable.c +3 -0
@@ -583,6 +583,9 @@ void __native_set_fixmap(enum fixed_addresses idx, pte_t pte)void native_set_fixmap (enum fixed_addresses idx,phys_addr_t phys,pgprot_t flags) { +/* Sanitize 'prot' against any unsupported bits: */ +pgprot_val (flags) &= __default_kernel_pte_mask; +__native_set_fixmap (idx,pfn_pte (phys >>PAGE_SHIFT , flags)); }
arch/x86/power/hibernate_64.c +15 -5
@@ -51,6 +51,12 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)pmd_t *pmd;pud_t *pud;p4d_t *p4d =NULL ; +pgprot_t pgtable_prot =__pgprot (_KERNPG_TABLE); +pgprot_t pmd_text_prot =__pgprot (__PAGE_KERNEL_LARGE_EXEC); + +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (pmd_text_prot) &= __default_kernel_pte_mask; +pgprot_val (pgtable_prot) &= __default_kernel_pte_mask;/* * The new mapping only has to cover the page containing the image
@@ -81,15 +87,19 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)return -ENOMEM ;set_pmd (pmd +pmd_index (restore_jump_address), -__pmd ((jump_address_phys &PMD_MASK ) | __PAGE_KERNEL_LARGE_EXEC)); +__pmd ((jump_address_phys &PMD_MASK ) |pgprot_val (pmd_text_prot)));set_pud (pud +pud_index (restore_jump_address), -__pud (__pa (pmd) | _KERNPG_TABLE)); +__pud (__pa (pmd) |pgprot_val (pgtable_prot)));if (p4d) { -set_p4d (p4d +p4d_index (restore_jump_address),__p4d (__pa (pud) | _KERNPG_TABLE)); -set_pgd (pgd +pgd_index (restore_jump_address),__pgd (__pa (p4d) | _KERNPG_TABLE)); +p4d_t new_p4d =__p4d (__pa (pud) |pgprot_val (pgtable_prot)); +pgd_t new_pgd =__pgd (__pa (p4d) |pgprot_val (pgtable_prot)); + +set_p4d (p4d +p4d_index (restore_jump_address), new_p4d); +set_pgd (pgd +pgd_index (restore_jump_address), new_pgd); }else {/* No p4d for 4-level paging: point the pgd to the pud page table */ -set_pgd (pgd +pgd_index (restore_jump_address),__pgd (__pa (pud) | _KERNPG_TABLE)); +pgd_t new_pgd =__pgd (__pa (p4d) |pgprot_val (pgtable_prot)); +set_pgd (pgd +pgd_index (restore_jump_address), new_pgd); }return 0 ;
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Do not auto-massage page protections
In reply to Dave Hansenx86/mm: Do not auto-massage page protections
Commit-ID: fb43d6cb91ef57d9e58d5f69b423784ff4a4c374 Gitweb: https://git.kernel.org/tip/fb43d6cb91ef57d9e58d5f69b423784ff4a4c374 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:09 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 12 Apr 2018 09:04:22 +0200
x86/mm: Do not auto-massage page protections
A PTE is constructed from a physical address and a pgprotval_t. __PAGE_KERNEL, for instance, is a pgprot_t and must be converted into a pgprotval_t before it can be used to create a PTE. This is done implicitly within functions like pfn_pte() by massage_pgprot().
However, this makes it very challenging to set bits (and keep them set) if your bit is being filtered out by massage_pgprot().
This moves the bit filtering out of pfn_pte() and friends. For users of PAGE_KERNEL*, filtering will be done automatically inside those macros but for users of __PAGE_KERNEL*, they need to do their own filtering now.
Note that we also just move pfn_pte/pmd/pud() over to check_pgprot() instead of massage_pgprot(). This way, we still *look* for unsupported bits and properly warn about them if we find them. This might happen if an unfiltered __PAGE_KERNEL* value was passed in, for instance.
- printk format warning fix from: Arnd Bergmann <[email protected]>
- boot crash fix from: Tom Lendacky <[email protected]>
- crash bisected by: Mike Galbraith <[email protected]>
--- arch/x86/boot/compressed/kaslr.c | 3 +++ arch/x86/include/asm/pgtable.h | 27 ++++++++++++++++++++++----- arch/x86/kernel/head64.c | 2 ++ arch/x86/kernel/ldt.c | 6 +++++- arch/x86/mm/ident_map.c | 3 +++ arch/x86/mm/iomap_32.c | 6 ++++++ arch/x86/mm/ioremap.c | 3 +++ arch/x86/mm/kasan_init_64.c | 14 +++++++++++++- arch/x86/mm/pgtable.c | 3 +++ arch/x86/power/hibernate_64.c | 20 +++++++++++++++----- 10 files changed, 75 insertions(+), 12 deletions(-)
arch/x86/boot/compressed/kaslr.c +3 -0
@@ -54,6 +54,9 @@ unsigned int ptrs_per_p4d __ro_after_init = 1;extern unsigned long get_cmd_line_ptr (void ); +/* Used by PAGE_KERN* macros: */ +pteval_t __default_kernel_pte_mask__read_mostly = ~0 ; +/* Simplified build-specific string for starting entropy. */ static const char build_str[] =UTS_RELEASE " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ") (" LINUX_COMPILER ") " UTS_VERSION ;
arch/x86/include/asm/pgtable.h +22 -5
@@ -526,22 +526,39 @@ static inline pgprotval_t massage_pgprot(pgprot_t pgprot)return protval; } +static inline pgprotval_t check_pgprot (pgprot_t pgprot) +{ +pgprotval_t massaged_val =massage_pgprot (pgprot); + +/* mmdebug.h can not be included here because of dependencies */ +#ifdef CONFIG_DEBUG_VM +WARN_ONCE (pgprot_val (pgprot) != massaged_val, +"attempted to set unsupported pgprot: %016llx " +"bits: %016llx supported: %016llx\n" , + (u64 )pgprot_val (pgprot), + (u64 )pgprot_val (pgprot) ^ massaged_val, + (u64 )__supported_pte_mask); +#endif + +return massaged_val; +} +static inline pte_t pfn_pte (unsigned long page_nr,pgprot_t pgprot) {return __pte (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pmd_t pfn_pmd (unsigned long page_nr,pgprot_t pgprot) {return __pmd (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pud_t pfn_pud (unsigned long page_nr,pgprot_t pgprot) {return __pud (((phys_addr_t )page_nr <<PAGE_SHIFT ) | -massage_pgprot (pgprot)); +check_pgprot (pgprot)); }static inline pte_t pte_modify (pte_t pte,pgprot_t newprot)
@@ -553,7 +570,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)* the newprot (if present): */ val &= _PAGE_CHG_MASK; - val |=massage_pgprot (newprot) & ~_PAGE_CHG_MASK; + val |=check_pgprot (newprot) & ~_PAGE_CHG_MASK;return __pte (val); }
@@ -563,7 +580,7 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)pmdval_t val =pmd_val (pmd); val &= _HPAGE_CHG_MASK; - val |=massage_pgprot (newprot) & ~_HPAGE_CHG_MASK; + val |=check_pgprot (newprot) & ~_HPAGE_CHG_MASK;return __pmd (val); }
arch/x86/kernel/head64.c +2 -0
@@ -195,6 +195,8 @@ unsigned long __head __startup_64(unsigned long physaddr, pud[i +1 ] = (pudval_t )pmd + pgtable_flags; pmd_entry = __PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL; +/* Filter out unsupported __PAGE_KERNEL_* bits: */ + pmd_entry &= __supported_pte_mask; pmd_entry +=sme_get_me_mask (); pmd_entry += physaddr;
arch/x86/kernel/ldt.c +5 -1
@@ -145,6 +145,7 @@ map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot)unsigned long offset = i <<PAGE_SHIFT ;const void *src = (char *)ldt->entries + offset;unsigned long pfn; +pgprot_t pte_prot;pte_t pte, *ptep; va = (unsigned long )ldt_slot_va (slot) + offset;
@@ -163,7 +164,10 @@ map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot)* target via some kernel interface which misses a * permission check. */ - pte =pfn_pte (pfn,__pgprot (__PAGE_KERNEL_RO & ~_PAGE_GLOBAL)); + pte_prot =__pgprot (__PAGE_KERNEL_RO & ~_PAGE_GLOBAL); +/* Filter out unsuppored __PAGE_KERNEL* bits: */ +pgprot_val (pte_prot) |= __supported_pte_mask; + pte =pfn_pte (pfn, pte_prot);set_pte_at (mm, va, ptep, pte);pte_unmap_unlock (ptep, ptl); }
arch/x86/mm/ident_map.c +3 -0
@@ -98,6 +98,9 @@ int kernel_ident_mapping_init(struct x86_mapping_info *info, pgd_t *pgd_page,if (!info->kernpg_flag) info->kernpg_flag = _KERNPG_TABLE; +/* Filter out unsupported __PAGE_KERNEL_* bits: */ + info->kernpg_flag &= __default_kernel_pte_mask; +for (; addr < end; addr = next) {pgd_t *pgd = pgd_page +pgd_index (addr);p4d_t *p4d;
arch/x86/mm/iomap_32.c +6 -0
@@ -44,6 +44,9 @@ int iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot)return ret; *prot =__pgprot (__PAGE_KERNEL |cachemode2protval (pcm)); +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (*prot) &= __default_kernel_pte_mask; +return 0 ; }EXPORT_SYMBOL_GPL (iomap_create_wc);
@@ -88,6 +91,9 @@ iomap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot) prot =__pgprot (__PAGE_KERNEL |cachemode2protval (_PAGE_CACHE_MODE_UC_MINUS)); +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (prot) &= __default_kernel_pte_mask; +return (void __force __iomem *)kmap_atomic_prot_pfn (pfn, prot); }EXPORT_SYMBOL_GPL (iomap_atomic_prot_pfn);
arch/x86/mm/ioremap.c +3 -0
@@ -816,6 +816,9 @@ void __init __early_set_fixmap(enum fixed_addresses idx, } pte =early_ioremap_pte (addr); +/* Sanitize 'prot' against any unsupported bits: */ +pgprot_val (flags) &= __default_kernel_pte_mask; +if (pgprot_val (flags))set_pte (pte,pfn_pte (phys >>PAGE_SHIFT , flags));else
arch/x86/mm/kasan_init_64.c +13 -1
@@ -269,6 +269,12 @@ void __init kasan_early_init(void)pudval_t pud_val =__pa_nodebug (kasan_zero_pmd) | _KERNPG_TABLE;p4dval_t p4d_val =__pa_nodebug (kasan_zero_pud) | _KERNPG_TABLE; +/* Mask out unsupported __PAGE_KERNEL bits: */ + pte_val &= __default_kernel_pte_mask; + pmd_val &= __default_kernel_pte_mask; + pud_val &= __default_kernel_pte_mask; + p4d_val &= __default_kernel_pte_mask; +for (i =0 ; i <PTRS_PER_PTE ; i++) kasan_zero_pte[i] =__pte (pte_val);
@@ -371,7 +377,13 @@ void __init kasan_init(void)*/ memset (kasan_zero_page,0 ,PAGE_SIZE );for (i =0 ; i <PTRS_PER_PTE ; i++) { -pte_t pte =__pte (__pa (kasan_zero_page) | __PAGE_KERNEL_RO | _PAGE_ENC); +pte_t pte; +pgprot_t prot; + + prot =__pgprot (__PAGE_KERNEL_RO | _PAGE_ENC); +pgprot_val (prot) &= __default_kernel_pte_mask; + + pte =__pte (__pa (kasan_zero_page) |pgprot_val (prot));set_pte (&kasan_zero_pte[i], pte); }/* Flush TLBs again to be sure that write protection applied. */
arch/x86/mm/pgtable.c +3 -0
@@ -583,6 +583,9 @@ void __native_set_fixmap(enum fixed_addresses idx, pte_t pte)void native_set_fixmap (enum fixed_addresses idx,phys_addr_t phys,pgprot_t flags) { +/* Sanitize 'prot' against any unsupported bits: */ +pgprot_val (flags) &= __default_kernel_pte_mask; +__native_set_fixmap (idx,pfn_pte (phys >>PAGE_SHIFT , flags)); }
arch/x86/power/hibernate_64.c +15 -5
@@ -51,6 +51,12 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)pmd_t *pmd;pud_t *pud;p4d_t *p4d =NULL ; +pgprot_t pgtable_prot =__pgprot (_KERNPG_TABLE); +pgprot_t pmd_text_prot =__pgprot (__PAGE_KERNEL_LARGE_EXEC); + +/* Filter out unsupported __PAGE_KERNEL* bits: */ +pgprot_val (pmd_text_prot) &= __default_kernel_pte_mask; +pgprot_val (pgtable_prot) &= __default_kernel_pte_mask;/* * The new mapping only has to cover the page containing the image
@@ -81,15 +87,19 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)return -ENOMEM ;set_pmd (pmd +pmd_index (restore_jump_address), -__pmd ((jump_address_phys &PMD_MASK ) | __PAGE_KERNEL_LARGE_EXEC)); +__pmd ((jump_address_phys &PMD_MASK ) |pgprot_val (pmd_text_prot)));set_pud (pud +pud_index (restore_jump_address), -__pud (__pa (pmd) | _KERNPG_TABLE)); +__pud (__pa (pmd) |pgprot_val (pgtable_prot)));if (p4d) { -set_p4d (p4d +p4d_index (restore_jump_address),__p4d (__pa (pud) | _KERNPG_TABLE)); -set_pgd (pgd +pgd_index (restore_jump_address),__pgd (__pa (p4d) | _KERNPG_TABLE)); +p4d_t new_p4d =__p4d (__pa (pud) |pgprot_val (pgtable_prot)); +pgd_t new_pgd =__pgd (__pa (p4d) |pgprot_val (pgtable_prot)); + +set_p4d (p4d +p4d_index (restore_jump_address), new_p4d); +set_pgd (pgd +pgd_index (restore_jump_address), new_pgd); }else {/* No p4d for 4-level paging: point the pgd to the pud page table */ -set_pgd (pgd +pgd_index (restore_jump_address),__pgd (__pa (pud) | _KERNPG_TABLE)); +pgd_t new_pgd =__pgd (__pa (p4d) |pgprot_val (pgtable_prot)); +set_pgd (pgd +pgd_index (restore_jump_address), new_pgd); }return 0 ;
Dave Hansen
maintainerPATCH v5 6/11 x86/mm: remove extra filtering in pageattr code
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
The pageattr code has a mode where it can set or clear PTE bits in existing PTEs, so the page protections of the *new* PTEs come from one of two places:
1. The set/clear masks: cpa->mask_clr / cpa->mask_set
2. The existing PTE
We filter ->mask_set/clr for supported PTE bits at entry to __change_page_attr() so we never need to filter them again.
The only other place permissions can come from is an existing PTE and those already presumably have good bits. We do not need to filter them again.
---
b/arch/x86/mm/pageattr.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
arch/x86/mm/pageattr.c renamed from arch/x86/mm/pageattr.c~x86-pageattr-dont-filter-global +2 -4
@@ -598,7 +598,6 @@ try_preserve_large_page(pte_t *kpte, uns req_prot =pgprot_clear_protnone_bits (req_prot);if (pgprot_val (req_prot) & _PAGE_PRESENT)pgprot_val (req_prot) |= _PAGE_PSE; - req_prot =canon_pgprot (req_prot);/* * old_pfn points to the large page base pfn. So we need
@@ -718,7 +717,7 @@ __split_large_page(struct cpa_data *cpa,*/ pfn = ref_pfn;for (i =0 ; i <PTRS_PER_PTE ; i++, pfn += pfninc) -set_pte (&pbase[i],pfn_pte (pfn,canon_pgprot (ref_prot))); +set_pte (&pbase[i],pfn_pte (pfn, ref_prot));if (virt_addr_valid (address)) {unsigned long pfn =PFN_DOWN (__pa (address));
@@ -935,7 +934,6 @@ static void populate_pte(struct cpa_data pte =pte_offset_kernel (pmd, start); pgprot =pgprot_clear_protnone_bits (pgprot); - pgprot =canon_pgprot (pgprot);while (num_pages-- && start < end) {set_pte (pte,pfn_pte (cpa->pfn, pgprot));
@@ -1234,7 +1232,7 @@ repeat:* after all we're only going to change it's attributes * not the memory it points to */ - new_pte =pfn_pte (pfn,canon_pgprot (new_prot)); + new_pte =pfn_pte (pfn, new_prot); cpa->pfn = pfn;/* * Do we really change anything ?
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Remove extra filtering in pageattr code
x86/mm: Remove extra filtering in pageattr code
Commit-ID: e71e836f463dd2cfb319ce88ae4a6e4f83904e6c Gitweb: https://git.kernel.org/tip/e71e836f463dd2cfb319ce88ae4a6e4f83904e6c Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:11 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:33 +0200
x86/mm: Remove extra filtering in pageattr code
The pageattr code has a mode where it can set or clear PTE bits in existing PTEs, so the page protections of the *new* PTEs come from one of two places:
1. The set/clear masks: cpa->mask_clr / cpa->mask_set
2. The existing PTE
We filter ->mask_set/clr for supported PTE bits at entry to __change_page_attr() so we never need to filter them again.
The only other place permissions can come from is an existing PTE and those already presumably have good bits. We do not need to filter them again.
--- arch/x86/mm/pageattr.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
arch/x86/mm/pageattr.c +2 -4
@@ -598,7 +598,6 @@ try_preserve_large_page(pte_t *kpte, unsigned long address, req_prot =pgprot_clear_protnone_bits (req_prot);if (pgprot_val (req_prot) & _PAGE_PRESENT)pgprot_val (req_prot) |= _PAGE_PSE; - req_prot =canon_pgprot (req_prot);/* * old_pfn points to the large page base pfn. So we need
@@ -718,7 +717,7 @@ __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,*/ pfn = ref_pfn;for (i =0 ; i <PTRS_PER_PTE ; i++, pfn += pfninc) -set_pte (&pbase[i],pfn_pte (pfn,canon_pgprot (ref_prot))); +set_pte (&pbase[i],pfn_pte (pfn, ref_prot));if (virt_addr_valid (address)) {unsigned long pfn =PFN_DOWN (__pa (address));
@@ -935,7 +934,6 @@ static void populate_pte(struct cpa_data *cpa, pte =pte_offset_kernel (pmd, start); pgprot =pgprot_clear_protnone_bits (pgprot); - pgprot =canon_pgprot (pgprot);while (num_pages-- && start < end) {set_pte (pte,pfn_pte (cpa->pfn, pgprot));
@@ -1234,7 +1232,7 @@ repeat:* after all we're only going to change it's attributes * not the memory it points to */ - new_pte =pfn_pte (pfn,canon_pgprot (new_prot)); + new_pte =pfn_pte (pfn, new_prot); cpa->pfn = pfn;/* * Do we really change anything ?
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Remove extra filtering in pageattr code
In reply to Dave Hansenx86/mm: Remove extra filtering in pageattr code
Commit-ID: 1a54420aeb4da1ba5b28283aa5696898220c9a27 Gitweb: https://git.kernel.org/tip/1a54420aeb4da1ba5b28283aa5696898220c9a27 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:11 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 12 Apr 2018 09:05:58 +0200
x86/mm: Remove extra filtering in pageattr code
The pageattr code has a mode where it can set or clear PTE bits in existing PTEs, so the page protections of the *new* PTEs come from one of two places:
1. The set/clear masks: cpa->mask_clr / cpa->mask_set
2. The existing PTE
We filter ->mask_set/clr for supported PTE bits at entry to __change_page_attr() so we never need to filter them again.
The only other place permissions can come from is an existing PTE and those already presumably have good bits. We do not need to filter them again.
--- arch/x86/mm/pageattr.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
arch/x86/mm/pageattr.c +2 -4
@@ -598,7 +598,6 @@ try_preserve_large_page(pte_t *kpte, unsigned long address, req_prot =pgprot_clear_protnone_bits (req_prot);if (pgprot_val (req_prot) & _PAGE_PRESENT)pgprot_val (req_prot) |= _PAGE_PSE; - req_prot =canon_pgprot (req_prot);/* * old_pfn points to the large page base pfn. So we need
@@ -718,7 +717,7 @@ __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,*/ pfn = ref_pfn;for (i =0 ; i <PTRS_PER_PTE ; i++, pfn += pfninc) -set_pte (&pbase[i],pfn_pte (pfn,canon_pgprot (ref_prot))); +set_pte (&pbase[i],pfn_pte (pfn, ref_prot));if (virt_addr_valid (address)) {unsigned long pfn =PFN_DOWN (__pa (address));
@@ -935,7 +934,6 @@ static void populate_pte(struct cpa_data *cpa, pte =pte_offset_kernel (pmd, start); pgprot =pgprot_clear_protnone_bits (pgprot); - pgprot =canon_pgprot (pgprot);while (num_pages-- && start < end) {set_pte (pte,pfn_pte (cpa->pfn, pgprot));
@@ -1234,7 +1232,7 @@ repeat:* after all we're only going to change it's attributes * not the memory it points to */ - new_pte =pfn_pte (pfn,canon_pgprot (new_prot)); + new_pte =pfn_pte (pfn, new_prot); cpa->pfn = pfn;/* * Do we really change anything ?
Dave Hansen
maintainerPATCH v5 7/11 x86/mm: comment _PAGE_GLOBAL mystery
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
I was mystified as to where the _PAGE_GLOBAL in the kernel page tables for kernel text came from. I audited all the places I could find, but I missed one: head_64.S.
The page tables that we create in here live for a long time, and they also have _PAGE_GLOBAL set, despite whether the processor supports it or not. It's harmless, and we got *lucky* that the pageattr code accidentally clears it when we wipe it out of __supported_pte_mask and then later try to mark kernel text read-only.
Comment some of these properties to make it easier to find and understand in the future.
---
b/arch/x86/kernel/head_64.S | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
arch/x86/kernel/head_64.S renamed from arch/x86/kernel/head_64.S~comment-global-page +10 -1
@@ -399,8 +399,13 @@ NEXT_PAGE(level3_ident_pgt) .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC .fill 511, 8, 0 NEXT_PAGE(level2_ident_pgt) - /* Since I easily can, map the first 1G. + /* + * Since I easily can, map the first 1G. * Don't set NX because code runs from these pages. + * + * Note: This sets _PAGE_GLOBAL despite whether + * the CPU supports it or it is enabled. But, + * the CPU should ignore the bit. */ PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) #else
@@ -431,6 +436,10 @@ NEXT_PAGE(level2_kernel_pgt) * (NOTE: at +512MB starts the module area, see MODULES_VADDR. * If you want to increase this then increase MODULES_VADDR * too.) + * + * This table is eventually used by the kernel during normal + * runtime. Care must be taken to clear out undesired bits + * later, like _PAGE_RW or _PAGE_GLOBAL in some cases. */ PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Comment _PAGE_GLOBAL mystery
x86/mm: Comment _PAGE_GLOBAL mystery
Commit-ID: 4ddee6efdcd0259fdd5014312bd536325e6d3429 Gitweb: https://git.kernel.org/tip/4ddee6efdcd0259fdd5014312bd536325e6d3429 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:13 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:33 +0200
x86/mm: Comment _PAGE_GLOBAL mystery
I was mystified as to where the _PAGE_GLOBAL in the kernel page tables for kernel text came from. I audited all the places I could find, but I missed one: head_64.S.
The page tables that we create in here live for a long time, and they also have _PAGE_GLOBAL set, despite whether the processor supports it or not. It's harmless, and we got *lucky* that the pageattr code accidentally clears it when we wipe it out of __supported_pte_mask and then later try to mark kernel text read-only.
Comment some of these properties to make it easier to find and understand in the future.
--- arch/x86/kernel/head_64.S | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
arch/x86/kernel/head_64.S +10 -1
@@ -399,8 +399,13 @@ NEXT_PAGE(level3_ident_pgt) .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC .fill 511, 8, 0 NEXT_PAGE(level2_ident_pgt) - /* Since I easily can, map the first 1G. + /* + * Since I easily can, map the first 1G. * Don't set NX because code runs from these pages. + * + * Note: This sets _PAGE_GLOBAL despite whether + * the CPU supports it or it is enabled. But, + * the CPU should ignore the bit. */ PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) #else
@@ -431,6 +436,10 @@ NEXT_PAGE(level2_kernel_pgt) * (NOTE: at +512MB starts the module area, see MODULES_VADDR. * If you want to increase this then increase MODULES_VADDR * too.) + * + * This table is eventually used by the kernel during normal + * runtime. Care must be taken to clear out undesired bits + * later, like _PAGE_RW or _PAGE_GLOBAL in some cases. */ PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Comment _PAGE_GLOBAL mystery
In reply to Dave Hansenx86/mm: Comment _PAGE_GLOBAL mystery
Commit-ID: 430d4005b8b41c19966dd3bfdb33004bdb2de01c Gitweb: https://git.kernel.org/tip/430d4005b8b41c19966dd3bfdb33004bdb2de01c Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:13 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 12 Apr 2018 09:05:58 +0200
x86/mm: Comment _PAGE_GLOBAL mystery
I was mystified as to where the _PAGE_GLOBAL in the kernel page tables for kernel text came from. I audited all the places I could find, but I missed one: head_64.S.
The page tables that we create in here live for a long time, and they also have _PAGE_GLOBAL set, despite whether the processor supports it or not. It's harmless, and we got *lucky* that the pageattr code accidentally clears it when we wipe it out of __supported_pte_mask and then later try to mark kernel text read-only.
Comment some of these properties to make it easier to find and understand in the future.
--- arch/x86/kernel/head_64.S | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
arch/x86/kernel/head_64.S +10 -1
@@ -399,8 +399,13 @@ NEXT_PAGE(level3_ident_pgt) .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC .fill 511, 8, 0 NEXT_PAGE(level2_ident_pgt) - /* Since I easily can, map the first 1G. + /* + * Since I easily can, map the first 1G. * Don't set NX because code runs from these pages. + * + * Note: This sets _PAGE_GLOBAL despite whether + * the CPU supports it or it is enabled. But, + * the CPU should ignore the bit. */ PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) #else
@@ -431,6 +436,10 @@ NEXT_PAGE(level2_kernel_pgt) * (NOTE: at +512MB starts the module area, see MODULES_VADDR. * If you want to increase this then increase MODULES_VADDR * too.) + * + * This table is eventually used by the kernel during normal + * runtime. Care must be taken to clear out undesired bits + * later, like _PAGE_RW or _PAGE_GLOBAL in some cases. */ PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
Dave Hansen
maintainerPATCH v5 8/11 x86/mm: do not forbid _PAGE_RW before init for __ro_after_init
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
__ro_after_init data gets stuck in the .rodata section. That's normally fine because the kernel itself manages the R/W properties.
But, if we run __change_page_attr() on an area which is __ro_after_init, the .rodata checks will trigger and force the area to be immediately read-only, even if it is early-ish in boot. This caused problems when trying to clear the _PAGE_GLOBAL bit for these area in the PTI code:
it cleared _PAGE_GLOBAL like I asked, but also took it up on itself to clear _PAGE_RW. The kernel then oopses the next time it wrote to a __ro_after_init data structure.
To fix this, add the kernel_set_to_readonly check, just like we have for kernel text, just a few lines below in this function.
---
b/arch/x86/mm/pageattr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
arch/x86/mm/pageattr.c renamed from arch/x86/mm/pageattr.c~check-kernel_set_to_readonly +4 -2
@@ -298,9 +298,11 @@ static inline pgprot_t static_protection/* * The .rodata section needs to be read-only. Using the pfn -* catches all aliases. +* catches all aliases. This also includes __ro_after_init, +* so do not enforce until kernel_set_to_readonly is true. */ -if (within (pfn,__pa_symbol (__start_rodata) >>PAGE_SHIFT , +if (kernel_set_to_readonly && +within (pfn,__pa_symbol (__start_rodata) >>PAGE_SHIFT ,__pa_symbol (__end_rodata) >>PAGE_SHIFT ))pgprot_val (forbidden) |= _PAGE_RW;
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
x86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
Commit-ID: efad2b4151521c944e405272035a673c74125c65 Gitweb: https://git.kernel.org/tip/efad2b4151521c944e405272035a673c74125c65 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:14 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:34 +0200
x86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
__ro_after_init data gets stuck in the .rodata section. That's normally fine because the kernel itself manages the R/W properties.
But, if we run __change_page_attr() on an area which is __ro_after_init, the .rodata checks will trigger and force the area to be immediately read-only, even if it is early-ish in boot. This caused problems when trying to clear the _PAGE_GLOBAL bit for these area in the PTI code:
it cleared _PAGE_GLOBAL like I asked, but also took it up on itself to clear _PAGE_RW. The kernel then oopses the next time it wrote to a __ro_after_init data structure.
To fix this, add the kernel_set_to_readonly check, just like we have for kernel text, just a few lines below in this function.
--- arch/x86/mm/pageattr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
arch/x86/mm/pageattr.c +4 -2
@@ -298,9 +298,11 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,/* * The .rodata section needs to be read-only. Using the pfn -* catches all aliases. +* catches all aliases. This also includes __ro_after_init, +* so do not enforce until kernel_set_to_readonly is true. */ -if (within (pfn,__pa_symbol (__start_rodata) >>PAGE_SHIFT , +if (kernel_set_to_readonly && +within (pfn,__pa_symbol (__start_rodata) >>PAGE_SHIFT ,__pa_symbol (__end_rodata) >>PAGE_SHIFT ))pgprot_val (forbidden) |= _PAGE_RW;
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
In reply to Dave Hansenx86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
Commit-ID: 639d6aafe437a7464399d2a77d006049053df06f Gitweb: https://git.kernel.org/tip/639d6aafe437a7464399d2a77d006049053df06f Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:14 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 12 Apr 2018 09:05:59 +0200
x86/mm: Do not forbid _PAGE_RW before init for __ro_after_init
__ro_after_init data gets stuck in the .rodata section. That's normally fine because the kernel itself manages the R/W properties.
But, if we run __change_page_attr() on an area which is __ro_after_init, the .rodata checks will trigger and force the area to be immediately read-only, even if it is early-ish in boot. This caused problems when trying to clear the _PAGE_GLOBAL bit for these area in the PTI code:
it cleared _PAGE_GLOBAL like I asked, but also took it up on itself to clear _PAGE_RW. The kernel then oopses the next time it wrote to a __ro_after_init data structure.
To fix this, add the kernel_set_to_readonly check, just like we have for kernel text, just a few lines below in this function.
--- arch/x86/mm/pageattr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
arch/x86/mm/pageattr.c +4 -2
@@ -298,9 +298,11 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,/* * The .rodata section needs to be read-only. Using the pfn -* catches all aliases. +* catches all aliases. This also includes __ro_after_init, +* so do not enforce until kernel_set_to_readonly is true. */ -if (within (pfn,__pa_symbol (__start_rodata) >>PAGE_SHIFT , +if (kernel_set_to_readonly && +within (pfn,__pa_symbol (__start_rodata) >>PAGE_SHIFT ,__pa_symbol (__end_rodata) >>PAGE_SHIFT ))pgprot_val (forbidden) |= _PAGE_RW;
Dave Hansen
maintainerPATCH v5 9/11 x86/pti: enable global pages for shared areas
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
The entry/exit text and cpu_entry_area are mapped into userspace and the kernel. But, they are not _PAGE_GLOBAL. This creates unnecessary TLB misses.
Add the _PAGE_GLOBAL flag for these areas.
---
b/arch/x86/mm/cpu_entry_area.c | 14 +++++++++++++- b/arch/x86/mm/pti.c | 23 ++++++++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-)
arch/x86/mm/cpu_entry_area.c renamed from arch/x86/mm/cpu_entry_area.c~kpti-why-no-global +13 -1
@@ -27,8 +27,20 @@ EXPORT_SYMBOL(get_cpu_entry_area);void cea_set_pte (void *cea_vaddr,phys_addr_t pa,pgprot_t flags) {unsigned long va = (unsigned long ) cea_vaddr; +pte_t pte =pfn_pte (pa >>PAGE_SHIFT , flags); -set_pte_vaddr (va,pfn_pte (pa >>PAGE_SHIFT , flags)); +/* +* The cpu_entry_area is shared between the user and kernel +* page tables. All of its ptes can safely be global. +* _PAGE_GLOBAL gets reused to help indicate PROT_NONE for +* non-present PTEs, so be careful not to set it in that +* case to avoid confusion. +*/ +if (boot_cpu_has (X86_FEATURE_PGE ) && + (pgprot_val (flags) & _PAGE_PRESENT)) + pte =pte_set_flags (pte, _PAGE_GLOBAL); + +set_pte_vaddr (va, pte); } static void __init
arch/x86/mm/pti.c renamed from arch/x86/mm/pti.c~kpti-why-no-global +22 -1
@@ -300,6 +300,27 @@ pti_clone_pmds(unsigned long start, unsireturn ;/* +* Only clone present PMDs. This ensures only setting +* _PAGE_GLOBAL on present PMDs. This should only be +* called on well-known addresses anyway, so a non- +* present PMD would be a surprise. +*/ +if (WARN_ON (!(pmd_flags (*pmd) & _PAGE_PRESENT))) +return ; + +/* +* Setting 'target_pmd' below creates a mapping in both +* the user and kernel page tables. It is effectively +* global, so set it as global in both copies. Note: +* the X86_FEATURE_PGE check is not _required_ because +* the CPU ignores _PAGE_GLOBAL when PGE is not +* supported. The check keeps consistentency with +* code that only set this bit when supported. +*/ +if (boot_cpu_has (X86_FEATURE_PGE )) + *pmd =pmd_set_flags (*pmd, _PAGE_GLOBAL); + +/* * Copy the PMD. That is, the kernelmode and usermode * tables will share the last-level page tables of this * address range
@@ -348,7 +369,7 @@ static void __init pti_clone_entry_text( {pti_clone_pmds ((unsigned long ) __entry_text_start, (unsigned long ) __irqentry_text_end, - _PAGE_RW | _PAGE_GLOBAL); + _PAGE_RW); }/*
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/pti: Enable global pages for shared areas
x86/pti: Enable global pages for shared areas
Commit-ID: e0bb456e32505b08e42477714169111fbdbff95b Gitweb: https://git.kernel.org/tip/e0bb456e32505b08e42477714169111fbdbff95b Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:15 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:34 +0200
x86/pti: Enable global pages for shared areas
The entry/exit text and cpu_entry_area are mapped into userspace and the kernel. But, they are not _PAGE_GLOBAL. This creates unnecessary TLB misses.
Add the _PAGE_GLOBAL flag for these areas.
--- arch/x86/mm/cpu_entry_area.c | 14 +++++++++++++- arch/x86/mm/pti.c | 23 ++++++++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-)
arch/x86/mm/cpu_entry_area.c +13 -1
@@ -27,8 +27,20 @@ EXPORT_SYMBOL(get_cpu_entry_area);void cea_set_pte (void *cea_vaddr,phys_addr_t pa,pgprot_t flags) {unsigned long va = (unsigned long ) cea_vaddr; +pte_t pte =pfn_pte (pa >>PAGE_SHIFT , flags); -set_pte_vaddr (va,pfn_pte (pa >>PAGE_SHIFT , flags)); +/* +* The cpu_entry_area is shared between the user and kernel +* page tables. All of its ptes can safely be global. +* _PAGE_GLOBAL gets reused to help indicate PROT_NONE for +* non-present PTEs, so be careful not to set it in that +* case to avoid confusion. +*/ +if (boot_cpu_has (X86_FEATURE_PGE ) && + (pgprot_val (flags) & _PAGE_PRESENT)) + pte =pte_set_flags (pte, _PAGE_GLOBAL); + +set_pte_vaddr (va, pte); } static void __init
arch/x86/mm/pti.c +22 -1
@@ -299,6 +299,27 @@ pti_clone_pmds(unsigned long start, unsigned long end, pmdval_t clear)if (WARN_ON (!target_pmd))return ; +/* +* Only clone present PMDs. This ensures only setting +* _PAGE_GLOBAL on present PMDs. This should only be +* called on well-known addresses anyway, so a non- +* present PMD would be a surprise. +*/ +if (WARN_ON (!(pmd_flags (*pmd) & _PAGE_PRESENT))) +return ; + +/* +* Setting 'target_pmd' below creates a mapping in both +* the user and kernel page tables. It is effectively +* global, so set it as global in both copies. Note: +* the X86_FEATURE_PGE check is not _required_ because +* the CPU ignores _PAGE_GLOBAL when PGE is not +* supported. The check keeps consistentency with +* code that only set this bit when supported. +*/ +if (boot_cpu_has (X86_FEATURE_PGE )) + *pmd =pmd_set_flags (*pmd, _PAGE_GLOBAL); +/* * Copy the PMD. That is, the kernelmode and usermode * tables will share the last-level page tables of this
@@ -348,7 +369,7 @@ static void __init pti_clone_entry_text(void) {pti_clone_pmds ((unsigned long ) __entry_text_start, (unsigned long ) __irqentry_text_end, - _PAGE_RW | _PAGE_GLOBAL); + _PAGE_RW); }/*
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/pti: Enable global pages for shared areas
In reply to Dave Hansenx86/pti: Enable global pages for shared areas
Commit-ID: 0f561fce4d6979a50415616896512f87a6d1d5c8 Gitweb: https://git.kernel.org/tip/0f561fce4d6979a50415616896512f87a6d1d5c8 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:15 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 12 Apr 2018 09:05:59 +0200
x86/pti: Enable global pages for shared areas
The entry/exit text and cpu_entry_area are mapped into userspace and the kernel. But, they are not _PAGE_GLOBAL. This creates unnecessary TLB misses.
Add the _PAGE_GLOBAL flag for these areas.
--- arch/x86/mm/cpu_entry_area.c | 14 +++++++++++++- arch/x86/mm/pti.c | 23 ++++++++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-)
arch/x86/mm/cpu_entry_area.c +13 -1
@@ -27,8 +27,20 @@ EXPORT_SYMBOL(get_cpu_entry_area);void cea_set_pte (void *cea_vaddr,phys_addr_t pa,pgprot_t flags) {unsigned long va = (unsigned long ) cea_vaddr; +pte_t pte =pfn_pte (pa >>PAGE_SHIFT , flags); -set_pte_vaddr (va,pfn_pte (pa >>PAGE_SHIFT , flags)); +/* +* The cpu_entry_area is shared between the user and kernel +* page tables. All of its ptes can safely be global. +* _PAGE_GLOBAL gets reused to help indicate PROT_NONE for +* non-present PTEs, so be careful not to set it in that +* case to avoid confusion. +*/ +if (boot_cpu_has (X86_FEATURE_PGE ) && + (pgprot_val (flags) & _PAGE_PRESENT)) + pte =pte_set_flags (pte, _PAGE_GLOBAL); + +set_pte_vaddr (va, pte); } static void __init
arch/x86/mm/pti.c +22 -1
@@ -299,6 +299,27 @@ pti_clone_pmds(unsigned long start, unsigned long end, pmdval_t clear)if (WARN_ON (!target_pmd))return ; +/* +* Only clone present PMDs. This ensures only setting +* _PAGE_GLOBAL on present PMDs. This should only be +* called on well-known addresses anyway, so a non- +* present PMD would be a surprise. +*/ +if (WARN_ON (!(pmd_flags (*pmd) & _PAGE_PRESENT))) +return ; + +/* +* Setting 'target_pmd' below creates a mapping in both +* the user and kernel page tables. It is effectively +* global, so set it as global in both copies. Note: +* the X86_FEATURE_PGE check is not _required_ because +* the CPU ignores _PAGE_GLOBAL when PGE is not +* supported. The check keeps consistentency with +* code that only set this bit when supported. +*/ +if (boot_cpu_has (X86_FEATURE_PGE )) + *pmd =pmd_set_flags (*pmd, _PAGE_GLOBAL); +/* * Copy the PMD. That is, the kernelmode and usermode * tables will share the last-level page tables of this
@@ -348,7 +369,7 @@ static void __init pti_clone_entry_text(void) {pti_clone_pmds ((unsigned long ) __entry_text_start, (unsigned long ) __irqentry_text_end, - _PAGE_RW | _PAGE_GLOBAL); + _PAGE_RW); }/*
Dave Hansen
maintainerPATCH v5 10/11 x86/pti: never implicitly clear _PAGE_GLOBAL for kernel image
In reply to Dave HansenFrom: Dave Hansen <[email protected]>
Summary:
In current kernels, with PTI enabled, no pages are marked Global. This potentially increases TLB misses. But, the mechanism by which the Global bit is set and cleared is rather haphazard. This patch makes the process more explicit. In the end, it leaves us with Global entries in the page tables for the areas truly shared by userspace and kernel and increases TLB hit rates.
The place this patch really shines in on systems without PCIDs. In this case, we are using an lseek microbenchmark[1] to see how a reasonably non-trivial syscall behaves. Higher is better:
No Global pages (baseline): 6077741 lseeks/sec 88 Global Pages (this set): 7528609 lseeks/sec (+23.9%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not huge for a kernel compile (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)I also re-checked everything using the lseek1 test[1]:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
The effect is more visible, but still modest.
Details:
The kernel page tables are inherited from head_64.S which rudely marks them as _PAGE_GLOBAL. For PTI, we have been relying on the grace of $DEITY and some insane behavior in pageattr.c to clear _PAGE_GLOBAL. This patch tries to do better.
First, stop filtering out "unsupported" bits from being cleared in the pageattr code. It's fine to filter out *setting* these bits but it is insane to keep us from clearing them.
Then, *explicitly* go clear _PAGE_GLOBAL from the kernel identity map. Do not rely on pageattr to do it magically.
After this patch, we can see that "GLB" shows up in each copy of the page tables, that we have the same number of global entries in each and that they are the *same* entries.
# grep -c GLB /sys/kernel/debug/page_tables/* /sys/kernel/debug/page_tables/current_kernel:11 /sys/kernel/debug/page_tables/current_user:11 /sys/kernel/debug/page_tables/kernel:11
# for f in `ls /sys/kernel/debug/page_tables/`; do grep GLB /sys/kernel/debug/page_tables/$f > $f.GLB; done # md5sum *.GLB 9caae8ad6a1fb53aca2407ec037f612d current_kernel.GLB 9caae8ad6a1fb53aca2407ec037f612d current_user.GLB 9caae8ad6a1fb53aca2407ec037f612d kernel.GLB
A quick visual audit also shows that all the entries make sense. 0xfffffe0000000000 is the cpu_entry_area and 0xffffffff81c00000 is the entry/exit text:
# grep -c GLB /sys/kernel/debug/page_tables/current_user 0xfffffe0000000000-0xfffffe0000002000 8K ro GLB NX pte 0xfffffe0000002000-0xfffffe0000003000 4K RW GLB NX pte 0xfffffe0000003000-0xfffffe0000006000 12K ro GLB NX pte 0xfffffe0000006000-0xfffffe0000007000 4K ro GLB x pte 0xfffffe0000007000-0xfffffe000000d000 24K RW GLB NX pte 0xfffffe000002d000-0xfffffe000002e000 4K ro GLB NX pte 0xfffffe000002e000-0xfffffe000002f000 4K RW GLB NX pte 0xfffffe000002f000-0xfffffe0000032000 12K ro GLB NX pte 0xfffffe0000032000-0xfffffe0000033000 4K ro GLB x pte 0xfffffe0000033000-0xfffffe0000039000 24K RW GLB NX pte 0xffffffff81c00000-0xffffffff81e00000 2M ro PSE GLB x pmd
1. https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
---
b/arch/x86/mm/init.c | 8 +------- b/arch/x86/mm/pageattr.c | 12 +++++++++--- b/arch/x86/mm/pti.c | 25 +++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 10 deletions(-)
arch/x86/mm/init.c renamed from arch/x86/mm/init.c~clear-global-for-pti +1 -7
@@ -161,12 +161,6 @@ struct map_range {static int page_size_mask; -static void enable_global_pages (void ) -{ -if (!static_cpu_has (X86_FEATURE_PTI )) - __supported_pte_mask |= _PAGE_GLOBAL; -} -static void __init probe_page_size_mask (void ) {/*
@@ -187,7 +181,7 @@ static void __init probe_page_size_mask( __supported_pte_mask &= ~_PAGE_GLOBAL;if (boot_cpu_has (X86_FEATURE_PGE )) {cr4_set_bits_and_update_boot (X86_CR4_PGE ); -enable_global_pages (); + __supported_pte_mask |= _PAGE_GLOBAL; }/* By the default is everything supported: */
arch/x86/mm/pageattr.c renamed from arch/x86/mm/pageattr.c~clear-global-for-pti +9 -3
@@ -1411,11 +1411,11 @@ static int change_page_attr_set_clr(unsimemset (&cpa,0 ,sizeof (cpa));/* -* Check, if we are requested to change a not supported -* feature: +* Check, if we are requested to set a not supported +* feature. Clearing non-supported features is OK. */ mask_set =canon_pgprot (mask_set); - mask_clr =canon_pgprot (mask_clr); +if (!pgprot_val (mask_set) && !pgprot_val (mask_clr) && !force_split)return 0 ;
@@ -1758,6 +1758,12 @@ int set_memory_4k(unsigned long addr, in __pgprot(0), 1, 0, NULL); } +int set_memory_nonglobal (unsigned long addr,int numpages) +{ +return change_page_attr_clear (&addr, numpages, +__pgprot (_PAGE_GLOBAL),0 ); +} +static int __set_memory_enc_dec (unsigned long addr,int numpages,bool enc) {struct cpa_data cpa;
arch/x86/mm/pti.c renamed from arch/x86/mm/pti.c~clear-global-for-pti +25 -0
@@ -373,6 +373,27 @@ static void __init pti_clone_entry_text( }/* +* This is the only user for it and it is not arch-generic like +* the other set_memory.h functions. Just extern it. +*/ +extern int set_memory_nonglobal (unsigned long addr,int numpages); +void pti_set_kernel_image_nonglobal (void ) +{ +/* +* The identity map is created with PMDs, regardless of the +* actual length of the kernel. We need to clear +* _PAGE_GLOBAL up to a PMD boundary, not just to the end +* of the image. +*/ +unsigned long start =PFN_ALIGN (_text); +unsigned long end =ALIGN ((unsigned long )_end,PMD_PAGE_SIZE ); + +pr_debug ("set kernel image non-global\n" ); + +set_memory_nonglobal (start, (end - start) >>PAGE_SHIFT ); +} + +/* * Initialize kernel page table isolation */ void __init pti_init (void )
@@ -383,6 +404,10 @@ void __init pti_init(void)pr_info ("enabled\n" );pti_clone_user_shared (); + +/* Undo all global bits from the init pagetables in head_64.S: */ +pti_set_kernel_image_nonglobal (); +/* Replace some of the global bits just for shared entry text: */ pti_clone_entry_text ();pti_setup_espfix64 ();pti_setup_vsyscall ();
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Commit-ID: a5df4f1f0d7872f6030dd12b166e570e60ae9e1d Gitweb: https://git.kernel.org/tip/a5df4f1f0d7872f6030dd12b166e570e60ae9e1d Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:17 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:34 +0200
x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Summary:
In current kernels, with PTI enabled, no pages are marked Global. This potentially increases TLB misses. But, the mechanism by which the Global bit is set and cleared is rather haphazard. This patch makes the process more explicit. In the end, it leaves us with Global entries in the page tables for the areas truly shared by userspace and kernel and increases TLB hit rates.
The place this patch really shines in on systems without PCIDs. In this case, we are using an lseek microbenchmark[1] to see how a reasonably non-trivial syscall behaves. Higher is better:
No Global pages (baseline): 6077741 lseeks/sec 88 Global Pages (this set): 7528609 lseeks/sec (+23.9%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not huge for a kernel compile (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)I also re-checked everything using the lseek1 test[1]:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
The effect is more visible, but still modest.
Details:
The kernel page tables are inherited from head_64.S which rudely marks them as _PAGE_GLOBAL. For PTI, we have been relying on the grace of $DEITY and some insane behavior in pageattr.c to clear _PAGE_GLOBAL. This patch tries to do better.
First, stop filtering out "unsupported" bits from being cleared in the pageattr code. It's fine to filter out *setting* these bits but it is insane to keep us from clearing them.
Then, *explicitly* go clear _PAGE_GLOBAL from the kernel identity map. Do not rely on pageattr to do it magically.
After this patch, we can see that "GLB" shows up in each copy of the page tables, that we have the same number of global entries in each and that they are the *same* entries.
/sys/kernel/debug/page_tables/current_kernel:11
/sys/kernel/debug/page_tables/current_user:11
/sys/kernel/debug/page_tables/kernel:11
9caae8ad6a1fb53aca2407ec037f612d current_kernel.GLB 9caae8ad6a1fb53aca2407ec037f612d current_user.GLB 9caae8ad6a1fb53aca2407ec037f612d kernel.GLB
A quick visual audit also shows that all the entries make sense. 0xfffffe0000000000 is the cpu_entry_area and 0xffffffff81c00000 is the entry/exit text:
0xfffffe0000000000-0xfffffe0000002000 8K ro GLB NX pte 0xfffffe0000002000-0xfffffe0000003000 4K RW GLB NX pte 0xfffffe0000003000-0xfffffe0000006000 12K ro GLB NX pte 0xfffffe0000006000-0xfffffe0000007000 4K ro GLB x pte 0xfffffe0000007000-0xfffffe000000d000 24K RW GLB NX pte 0xfffffe000002d000-0xfffffe000002e000 4K ro GLB NX pte 0xfffffe000002e000-0xfffffe000002f000 4K RW GLB NX pte 0xfffffe000002f000-0xfffffe0000032000 12K ro GLB NX pte 0xfffffe0000032000-0xfffffe0000033000 4K ro GLB x pte 0xfffffe0000033000-0xfffffe0000039000 24K RW GLB NX pte 0xffffffff81c00000-0xffffffff81e00000 2M ro PSE GLB x pmd
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
--- arch/x86/mm/init.c | 8 +------- arch/x86/mm/pageattr.c | 12 +++++++++--- arch/x86/mm/pti.c | 25 +++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 10 deletions(-)
arch/x86/mm/init.c +1 -7
@@ -161,12 +161,6 @@ struct map_range {static int page_size_mask; -static void enable_global_pages (void ) -{ -if (!static_cpu_has (X86_FEATURE_PTI )) - __supported_pte_mask |= _PAGE_GLOBAL; -} -static void __init probe_page_size_mask (void ) {/*
@@ -187,7 +181,7 @@ static void __init probe_page_size_mask(void) __supported_pte_mask &= ~_PAGE_GLOBAL;if (boot_cpu_has (X86_FEATURE_PGE )) {cr4_set_bits_and_update_boot (X86_CR4_PGE ); -enable_global_pages (); + __supported_pte_mask |= _PAGE_GLOBAL; }/* By the default is everything supported: */
arch/x86/mm/pageattr.c +9 -3
@@ -1411,11 +1411,11 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,memset (&cpa,0 ,sizeof (cpa));/* -* Check, if we are requested to change a not supported -* feature: +* Check, if we are requested to set a not supported +* feature. Clearing non-supported features is OK. */ mask_set =canon_pgprot (mask_set); - mask_clr =canon_pgprot (mask_clr); +if (!pgprot_val (mask_set) && !pgprot_val (mask_clr) && !force_split)return 0 ;
@@ -1758,6 +1758,12 @@ int set_memory_4k(unsigned long addr, int numpages) __pgprot(0), 1, 0, NULL); } +int set_memory_nonglobal (unsigned long addr,int numpages) +{ +return change_page_attr_clear (&addr, numpages, +__pgprot (_PAGE_GLOBAL),0 ); +} +static int __set_memory_enc_dec (unsigned long addr,int numpages,bool enc) {struct cpa_data cpa;
arch/x86/mm/pti.c +25 -0
@@ -372,6 +372,27 @@ static void __init pti_clone_entry_text(void) _PAGE_RW); } +/* +* This is the only user for it and it is not arch-generic like +* the other set_memory.h functions. Just extern it. +*/ +extern int set_memory_nonglobal (unsigned long addr,int numpages); +void pti_set_kernel_image_nonglobal (void ) +{ +/* +* The identity map is created with PMDs, regardless of the +* actual length of the kernel. We need to clear +* _PAGE_GLOBAL up to a PMD boundary, not just to the end +* of the image. +*/ +unsigned long start =PFN_ALIGN (_text); +unsigned long end =ALIGN ((unsigned long )_end,PMD_PAGE_SIZE ); + +pr_debug ("set kernel image non-global\n" ); + +set_memory_nonglobal (start, (end - start) >>PAGE_SHIFT ); +} +/* * Initialize kernel page table isolation */
@@ -383,6 +404,10 @@ void __init pti_init(void)pr_info ("enabled\n" );pti_clone_user_shared (); + +/* Undo all global bits from the init pagetables in head_64.S: */ +pti_set_kernel_image_nonglobal (); +/* Replace some of the global bits just for shared entry text: */ pti_clone_entry_text ();pti_setup_espfix64 ();pti_setup_vsyscall ();
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
In reply to Dave Hansenx86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Commit-ID: 39114b7a743e6759bab4d96b7d9651d44d17e3f9 Gitweb: https://git.kernel.org/tip/39114b7a743e6759bab4d96b7d9651d44d17e3f9 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:17 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 12 Apr 2018 09:06:00 +0200
x86/pti: Never implicitly clear _PAGE_GLOBAL for kernel image
Summary:
In current kernels, with PTI enabled, no pages are marked Global. This potentially increases TLB misses. But, the mechanism by which the Global bit is set and cleared is rather haphazard. This patch makes the process more explicit. In the end, it leaves us with Global entries in the page tables for the areas truly shared by userspace and kernel and increases TLB hit rates.
The place this patch really shines in on systems without PCIDs. In this case, we are using an lseek microbenchmark[1] to see how a reasonably non-trivial syscall behaves. Higher is better:
No Global pages (baseline): 6077741 lseeks/sec 88 Global Pages (this set): 7528609 lseeks/sec (+23.9%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not huge for a kernel compile (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% )
28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% )
-1.195 seconds (-0.64%)I also re-checked everything using the lseek1 test[1]:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec
+270737 lseeks/sec (+1.71%)
The effect is more visible, but still modest.
Details:
The kernel page tables are inherited from head_64.S which rudely marks them as _PAGE_GLOBAL. For PTI, we have been relying on the grace of $DEITY and some insane behavior in pageattr.c to clear _PAGE_GLOBAL. This patch tries to do better.
First, stop filtering out "unsupported" bits from being cleared in the pageattr code. It's fine to filter out *setting* these bits but it is insane to keep us from clearing them.
Then, *explicitly* go clear _PAGE_GLOBAL from the kernel identity map. Do not rely on pageattr to do it magically.
After this patch, we can see that "GLB" shows up in each copy of the page tables, that we have the same number of global entries in each and that they are the *same* entries.
/sys/kernel/debug/page_tables/current_kernel:11
/sys/kernel/debug/page_tables/current_user:11
/sys/kernel/debug/page_tables/kernel:11
9caae8ad6a1fb53aca2407ec037f612d current_kernel.GLB 9caae8ad6a1fb53aca2407ec037f612d current_user.GLB 9caae8ad6a1fb53aca2407ec037f612d kernel.GLB
A quick visual audit also shows that all the entries make sense. 0xfffffe0000000000 is the cpu_entry_area and 0xffffffff81c00000 is the entry/exit text:
0xfffffe0000000000-0xfffffe0000002000 8K ro GLB NX pte 0xfffffe0000002000-0xfffffe0000003000 4K RW GLB NX pte 0xfffffe0000003000-0xfffffe0000006000 12K ro GLB NX pte 0xfffffe0000006000-0xfffffe0000007000 4K ro GLB x pte 0xfffffe0000007000-0xfffffe000000d000 24K RW GLB NX pte 0xfffffe000002d000-0xfffffe000002e000 4K ro GLB NX pte 0xfffffe000002e000-0xfffffe000002f000 4K RW GLB NX pte 0xfffffe000002f000-0xfffffe0000032000 12K ro GLB NX pte 0xfffffe0000032000-0xfffffe0000033000 4K ro GLB x pte 0xfffffe0000033000-0xfffffe0000039000 24K RW GLB NX pte 0xffffffff81c00000-0xffffffff81e00000 2M ro PSE GLB x pmd
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
--- arch/x86/mm/init.c | 8 +------- arch/x86/mm/pageattr.c | 12 +++++++++--- arch/x86/mm/pti.c | 25 +++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 10 deletions(-)
arch/x86/mm/init.c +1 -7
@@ -161,12 +161,6 @@ struct map_range {static int page_size_mask; -static void enable_global_pages (void ) -{ -if (!static_cpu_has (X86_FEATURE_PTI )) - __supported_pte_mask |= _PAGE_GLOBAL; -} -static void __init probe_page_size_mask (void ) {/*
@@ -187,7 +181,7 @@ static void __init probe_page_size_mask(void) __supported_pte_mask &= ~_PAGE_GLOBAL;if (boot_cpu_has (X86_FEATURE_PGE )) {cr4_set_bits_and_update_boot (X86_CR4_PGE ); -enable_global_pages (); + __supported_pte_mask |= _PAGE_GLOBAL; }/* By the default is everything supported: */
arch/x86/mm/pageattr.c +9 -3
@@ -1411,11 +1411,11 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,memset (&cpa,0 ,sizeof (cpa));/* -* Check, if we are requested to change a not supported -* feature: +* Check, if we are requested to set a not supported +* feature. Clearing non-supported features is OK. */ mask_set =canon_pgprot (mask_set); - mask_clr =canon_pgprot (mask_clr); +if (!pgprot_val (mask_set) && !pgprot_val (mask_clr) && !force_split)return 0 ;
@@ -1758,6 +1758,12 @@ int set_memory_4k(unsigned long addr, int numpages) __pgprot(0), 1, 0, NULL); } +int set_memory_nonglobal (unsigned long addr,int numpages) +{ +return change_page_attr_clear (&addr, numpages, +__pgprot (_PAGE_GLOBAL),0 ); +} +static int __set_memory_enc_dec (unsigned long addr,int numpages,bool enc) {struct cpa_data cpa;
arch/x86/mm/pti.c +25 -0
@@ -372,6 +372,27 @@ static void __init pti_clone_entry_text(void) _PAGE_RW); } +/* +* This is the only user for it and it is not arch-generic like +* the other set_memory.h functions. Just extern it. +*/ +extern int set_memory_nonglobal (unsigned long addr,int numpages); +void pti_set_kernel_image_nonglobal (void ) +{ +/* +* The identity map is created with PMDs, regardless of the +* actual length of the kernel. We need to clear +* _PAGE_GLOBAL up to a PMD boundary, not just to the end +* of the image. +*/ +unsigned long start =PFN_ALIGN (_text); +unsigned long end =ALIGN ((unsigned long )_end,PMD_PAGE_SIZE ); + +pr_debug ("set kernel image non-global\n" ); + +set_memory_nonglobal (start, (end - start) >>PAGE_SHIFT ); +} +/* * Initialize kernel page table isolation */
@@ -383,6 +404,10 @@ void __init pti_init(void)pr_info ("enabled\n" );pti_clone_user_shared (); + +/* Undo all global bits from the init pagetables in head_64.S: */ +pti_set_kernel_image_nonglobal (); +/* Replace some of the global bits just for shared entry text: */ pti_clone_entry_text ();pti_setup_espfix64 ();pti_setup_vsyscall ();
Dave Hansen
maintainerPATCH v5 11/11 x86/pti: leave kernel text global for !PCID
In reply to Dave HansenNote: This has changed since the last version. It now clones the kernel text PMDs at a much later point and also disables this functionality on AMD K8 processors. Details in the patch.
--
I'm sticking this at the end of the series because it's a bit weird. It can be dropped and the rest of the series is still useful without it.
Global pages are bad for hardening because they potentially let an exploit read the kernel image via a Meltdown-style attack which makes it easier to find gadgets.
But, global pages are good for performance because they reduce TLB misses when making user/kernel transitions, especially when PCIDs are not available, such as on older hardware, or where a hypervisor has disabled them for some reason.
This patch implements a basic, sane policy: If you have PCIDs, you only map a minimal amount of kernel text global. If you do not have PCIDs, you map all kernel text global.
This policy effectively makes PCIDs something that not only adds performance but a little bit of hardening as well.
I ran a simple "lseek" microbenchmark[1] to test the benefit on a modern Atom microserver. Most of the benefit comes from applying the series before this patch ("entry only"), but there is still a signifiant benefit from this patch.
No Global Lines (baseline ): 6077741 lseeks/sec 88 Global Lines (entry only): 7528609 lseeks/sec (+23.9%) 94 Global Lines (this patch): 8433111 lseeks/sec (+38.8%)
1. https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
---
b/arch/x86/include/asm/pti.h | 2 + b/arch/x86/mm/init_64.c | 6 +++ b/arch/x86/mm/pti.c | 78 ++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 82 insertions(+), 4 deletions(-)
arch/x86/include/asm/pti.h renamed from arch/x86/include/asm/pti.h~kpti-global-text-option +2 -0
@@ -6,8 +6,10 @@#ifdef CONFIG_PAGE_TABLE_ISOLATION extern void pti_init (void );extern void pti_check_boottime_disable (void ); +extern void pti_clone_kernel_text (void );#else static inline void pti_check_boottime_disable (void ) { } +static inline void pti_clone_kernel_text (void ) { }#endif #endif /* __ASSEMBLY__ */
arch/x86/mm/init_64.c renamed from arch/x86/mm/init_64.c~kpti-global-text-option +6 -0
@@ -1294,6 +1294,12 @@ void mark_rodata_ro(void) (unsigned long) __va(__pa_symbol(_sdata)));debug_checkwx (); + +/* +* Do this after all of the manipulation of the +* kernel text page tables are complete. +*/ +pti_clone_kernel_text (); }int kern_addr_valid (unsigned long addr)
arch/x86/mm/pti.c renamed from arch/x86/mm/pti.c~kpti-global-text-option +74 -4
137 lines not on this page · raw message
_
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/pti: Leave kernel text global for !PCID
x86/pti: Leave kernel text global for !PCID
Commit-ID: 0564258fb2cfe6876738665314445bf391f450e2 Gitweb: https://git.kernel.org/tip/0564258fb2cfe6876738665314445bf391f450e2 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:18 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 9 Apr 2018 18:27:34 +0200
x86/pti: Leave kernel text global for !PCID
Global pages are bad for hardening because they potentially let an exploit read the kernel image via a Meltdown-style attack which makes it easier to find gadgets.
But, global pages are good for performance because they reduce TLB misses when making user/kernel transitions, especially when PCIDs are not available, such as on older hardware, or where a hypervisor has disabled them for some reason.
This patch implements a basic, sane policy: If you have PCIDs, you only map a minimal amount of kernel text global. If you do not have PCIDs, you map all kernel text global.
This policy effectively makes PCIDs something that not only adds performance but a little bit of hardening as well.
I ran a simple "lseek" microbenchmark[1] to test the benefit on a modern Atom microserver. Most of the benefit comes from applying the series before this patch ("entry only"), but there is still a signifiant benefit from this patch.
No Global Lines (baseline ): 6077741 lseeks/sec 88 Global Lines (entry only): 7528609 lseeks/sec (+23.9%) 94 Global Lines (this patch): 8433111 lseeks/sec (+38.8%)
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
--- arch/x86/include/asm/pti.h | 2 ++ arch/x86/mm/init_64.c | 6 ++++ arch/x86/mm/pti.c | 78 +++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 82 insertions(+), 4 deletions(-)
arch/x86/include/asm/pti.h +2 -0
@@ -6,8 +6,10 @@#ifdef CONFIG_PAGE_TABLE_ISOLATION extern void pti_init (void );extern void pti_check_boottime_disable (void ); +extern void pti_clone_kernel_text (void );#else static inline void pti_check_boottime_disable (void ) { } +static inline void pti_clone_kernel_text (void ) { }#endif #endif /* __ASSEMBLY__ */
arch/x86/mm/init_64.c +6 -0
@@ -1290,6 +1290,12 @@ void mark_rodata_ro(void) (unsigned long) __va(__pa_symbol(_sdata)));debug_checkwx (); + +/* +* Do this after all of the manipulation of the +* kernel text page tables are complete. +*/ +pti_clone_kernel_text (); }int kern_addr_valid (unsigned long addr)
arch/x86/mm/pti.c +74 -4
137 lines not on this page · raw message
tip-bot for Dave Hansen
merge bot[tip:x86/pti] x86/pti: Leave kernel text global for !PCID
In reply to Dave Hansenx86/pti: Leave kernel text global for !PCID
Commit-ID: 8c06c7740d191b9055cb9be920579d5ecdd26303 Gitweb: https://git.kernel.org/tip/8c06c7740d191b9055cb9be920579d5ecdd26303 Author: Dave Hansen <[email protected]> AuthorDate: Fri, 6 Apr 2018 13:55:18 -0700 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 12 Apr 2018 09:06:00 +0200
x86/pti: Leave kernel text global for !PCID
Global pages are bad for hardening because they potentially let an exploit read the kernel image via a Meltdown-style attack which makes it easier to find gadgets.
But, global pages are good for performance because they reduce TLB misses when making user/kernel transitions, especially when PCIDs are not available, such as on older hardware, or where a hypervisor has disabled them for some reason.
This patch implements a basic, sane policy: If you have PCIDs, you only map a minimal amount of kernel text global. If you do not have PCIDs, you map all kernel text global.
This policy effectively makes PCIDs something that not only adds performance but a little bit of hardening as well.
I ran a simple "lseek" microbenchmark[1] to test the benefit on a modern Atom microserver. Most of the benefit comes from applying the series before this patch ("entry only"), but there is still a signifiant benefit from this patch.
No Global Lines (baseline ): 6077741 lseeks/sec 88 Global Lines (entry only): 7528609 lseeks/sec (+23.9%) 94 Global Lines (this patch): 8433111 lseeks/sec (+38.8%)
[1.] https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
--- arch/x86/include/asm/pti.h | 2 ++ arch/x86/mm/init_64.c | 6 ++++ arch/x86/mm/pti.c | 78 +++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 82 insertions(+), 4 deletions(-)
arch/x86/include/asm/pti.h +2 -0
@@ -6,8 +6,10 @@#ifdef CONFIG_PAGE_TABLE_ISOLATION extern void pti_init (void );extern void pti_check_boottime_disable (void ); +extern void pti_clone_kernel_text (void );#else static inline void pti_check_boottime_disable (void ) { } +static inline void pti_clone_kernel_text (void ) { }#endif #endif /* __ASSEMBLY__ */
arch/x86/mm/init_64.c +6 -0
@@ -1290,6 +1290,12 @@ void mark_rodata_ro(void) (unsigned long) __va(__pa_symbol(_sdata)));debug_checkwx (); + +/* +* Do this after all of the manipulation of the +* kernel text page tables are complete. +*/ +pti_clone_kernel_text (); }int kern_addr_valid (unsigned long addr)
arch/x86/mm/pti.c +74 -4
137 lines not on this page · raw message
Re: [PATCH 11/11] x86/pti: leave kernel text global for !PCID
In reply to Dave Hansenarch/x86/mm/pti.c static void __init pti_clone_entry_text( · line 434
Quoted 8 lines · Dave Hansen
arch/x86/mm/pti.c renamed from arch/x86/mm/pti.c~kpti-global-text-option +8
-0+/* +* For some configurations, map all of kernel text into the user page +* tables. This reduces TLB misses, especially on non-PCID systems. +*/ +void pti_clone_kernel_text (void ) +{ +unsigned long start =PFN_ALIGN (_text); +unsigned long end =ALIGN ((unsigned long )_end,PMD_PAGE_SIZE );
I think this is too much set global: _end is after data, bss, and brk, and all kinds of other stuff that could hold secrets. I think this should match what mark_rodata_ro() is doing and use __end_rodata_hpage_align. (And on i386, this should be maybe _etext.)
-Kees
Signature · 2 lines
Kees Cook Pixel Security
Dave Hansen
maintainerRe: [PATCH 11/11] x86/pti: leave kernel text global for !PCID
Quoted 13 lines · Kees Cook
arch/x86/mm/pti.c static void __init pti_clone_entry_text( · line 434
Quoted 8 lines · Dave Hansen
arch/x86/mm/pti.c renamed from arch/x86/mm/pti.c~kpti-global-text-option +8
-0+/* +* For some configurations, map all of kernel text into the user page +* tables. This reduces TLB misses, especially on non-PCID systems. +*/ +void pti_clone_kernel_text (void ) +{ +unsigned long start =PFN_ALIGN (_text); +unsigned long end =ALIGN ((unsigned long )_end,PMD_PAGE_SIZE );I think this is too much set global:
_endis after data, bss, and brk, and all kinds of other stuff that could hold secrets. I think this should match whatmark_rodata_ro()is doing and use__end_rodata_hpage_align. (And on i386, this should be maybe_etext.)
Sounds reasonable to me. This does assume that there are no secrets built into the kernel image, right?
Re: [PATCH 11/11] x86/pti: leave kernel text global for !PCID
Quoted 15 lines · Dave Hansen
Quoted 13 lines · Kees Cook
arch/x86/mm/pti.c static void __init pti_clone_entry_text( · line 434
Quoted 8 lines · Dave Hansen
arch/x86/mm/pti.c renamed from arch/x86/mm/pti.c~kpti-global-text-option +8
-0+/* +* For some configurations, map all of kernel text into the user page +* tables. This reduces TLB misses, especially on non-PCID systems. +*/ +void pti_clone_kernel_text (void ) +{ +unsigned long start =PFN_ALIGN (_text); +unsigned long end =ALIGN ((unsigned long )_end,PMD_PAGE_SIZE );I think this is too much set global:
_endis after data, bss, and brk, and all kinds of other stuff that could hold secrets. I think this should match whatmark_rodata_ro()is doing and use__end_rodata_hpage_align. (And on i386, this should be maybe_etext.)
Quoted 2 lines
Sounds reasonable to me. This does assume that there are no secrets built into the kernel image, right?
It's hard to say, but I was trying to consider the basic threat model of having your kernel image available to an attacker (i.e. a distro kernel can be examined from packages, etc). In that case, the text and rodata are readable through much more direct mechanisms. Everything after rodata is run-time state, and should be excluded in the general case.
I would expect more paranoid system builders to boot with "pti=on", but perhaps we should disable Global under other specific CONFIGs, or make a specific CONFIG for it that other options can select, probably.
-Kees
Signature · 2 lines
Kees Cook Pixel Security
Quoted 2 lines · Dave Hansen
Changes from v4
* Fix compile error reported by Tom Lendacky
This built with CONFIG_RANDOMIZE_BASE=y, but failed to boot successfully. I think you're missing the initialization of __default_kernel_pte_mask in kaslr.c.
Thanks,
Tom
Quoted 60 lines
* Avoid setting
_PAGE_GLOBALon non-present entriesChanges from v3:
* Fix whitespace issue noticed by willy
* Clarify comments aboutX86_FEATURE_PGEchecks
* Clarify commit message around the necessity of_PAGE_GLOBALfiltering when CR4.PGE=0 or PGE is unsupported.Changes from v2:
* Add performance numbers to changelogs
* Fix compile error resulting from use of x86-specific__default_kernel_pte_maskin arch-genericmm/early_ioremap.c
* Delay kernel text cloning until after we are done messing with it (patch 11).
* Blacklist K8 explicitly from mapping all kernel text as global (this should never happen because K8 does not use pti when pti=auto, but we on the safe side). (patch 11)--
The later versions of the KAISER patches (pre-PTI) allowed the user/kernel shared areas to be GLOBAL. The thought was that this would reduce the TLB overhead of keeping two copies of these mappings.
During the switch over to PTI, we seem to have lost our ability to have GLOBAL mappings. This adds them back.
To measure the benefits of this, I took a modern Atom system without PCIDs and ran a microbenchmark[1] (higher is better):
No Global Lines (baseline ): 6077741 lseeks/sec 88 Global Lines (kern entry): 7528609 lseeks/sec (+23.9%) 94 Global Lines (all ktext ): 8433111 lseeks/sec (+38.8%)
On a modern Skylake desktop with PCIDs, the benefits are tangible, but not huge:
No Global pages (baseline): 15783951 lseeks/sec
28 Global pages (this set): 16054688 lseeks/sec+270737 lseeks/sec (+1.71%)I also double-checked with a kernel compile on the Skylake system (lower is better):
No Global pages (baseline): 186.951 seconds time elapsed ( +- 0.35% ) 28 Global pages (this set): 185.756 seconds time elapsed ( +- 0.09% ) -1.195 seconds (-0.64%)1. https://github.com/antonblanchard/will-it-scale/blob/master/tests/lseek1.c
Cc Andrea Arcangeli <[email protected]>Cc Andy Lutomirski <[email protected]>Cc Linus Torvalds <[email protected]>Cc Kees Cook <[email protected]>Cc Hugh Dickins <[email protected]>Cc Juergen Gross <[email protected]>Cc Nadav Amit <[email protected]>
Dave Hansen
maintainerQuoted 6 lines · Tom Lendacky
Quoted 2 lines · Dave Hansen
Changes from v4
* Fix compile error reported by Tom LendackyThis built with
CONFIG_RANDOMIZE_BASE=y, but failed to boot successfully. I think you're missing the initialization of__default_kernel_pte_maskinkaslr.c.
This should be simple to fix (just add a -1 instead of 0), but let me double-check and actually boot the fix.
Quoted 10 lines · Dave Hansen
Quoted 6 lines · Tom Lendacky
Quoted 2 lines · Dave Hansen
Changes from v4
* Fix compile error reported by Tom LendackyThis built with
CONFIG_RANDOMIZE_BASE=y, but failed to boot successfully. I think you're missing the initialization of__default_kernel_pte_maskinkaslr.c.This should be simple to fix (just add a -1 instead of 0), but let me double-check and actually boot the fix.
Yup, added an "= ~0" and everything is good.
Thanks,
Tom
Quoted 1 line
Dave Hansen
maintainerQuoted 5 lines · Tom Lendacky
Quoted 4 lines · Dave Hansen
Quoted 3 lines · Tom Lendacky
Quoted 2 lines · Dave Hansen
Changes from v4
* Fix compile error reported by Tom Lendacky
Quoted 8 lines
Quoted 6 lines
Quoted 3 lines
This built with
CONFIG_RANDOMIZE_BASE=y, but failed to boot successfully. I think you're missing the initialization of__default_kernel_pte_maskinkaslr.c.This should be simple to fix (just add a -1 instead of 0), but let me double-check and actually boot the fix.
Yup, added an "= ~0" and everything is good.
I'm testing at this commit in the tip tree:
0564258... x86/pti: Leave kernel text global for !PCID
It seems to boot OK with RANDOMIZE_BASE=y for both PCID and non-PCID configuration. Could you send along your .config so I can try to reproduce?
Quoted 13 lines · Dave Hansen
Quoted 12 lines · Tom Lendacky
Quoted 10 lines · Dave Hansen
Quoted 6 lines · Tom Lendacky
Quoted 2 lines · Dave Hansen
Changes from v4
* Fix compile error reported by Tom LendackyThis built with
CONFIG_RANDOMIZE_BASE=y, but failed to boot successfully. I think you're missing the initialization of__default_kernel_pte_maskinkaslr.c.This should be simple to fix (just add a -1 instead of 0), but let me double-check and actually boot the fix.
Quoted 9 lines
Quoted 1 line
Yup, added an "= ~0" and everything is good.
I'm testing at this commit in the tip tree:
0564258... x86/pti: Leave kernel text global for !PCID
It seems to boot OK with RANDOMIZE_BASE=y for both PCID and non-PCID configuration. Could you send along your .config so I can try to reproduce?
Sure, I'll send it to you directly as an attachment.
Thanks,
Tom